1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/clkdev.h>
20 #include <linux/delay.h>
21
22 #include "clk-mtk.h"
23
24 #define REG_CON0 0
25 #define REG_CON1 4
26
27 #define CON0_BASE_EN BIT(0)
28 #define CON0_PWR_ON BIT(0)
29 #define CON0_ISO_EN BIT(1)
30 #define CON0_PCW_CHG BIT(31)
31
32 #define AUDPLL_TUNER_EN BIT(31)
33
34 #define POSTDIV_MASK 0x7
35 #define INTEGER_BITS 7
36
37 /*
38 * MediaTek PLLs are configured through their pcw value. The pcw value describes
39 * a divider in the PLL feedback loop which consists of 7 bits for the integer
40 * part and the remaining bits (if present) for the fractional part. Also they
41 * have a 3 bit power-of-two post divider.
42 */
43
44 struct mtk_clk_pll {
45 struct clk_hw hw;
46 void __iomem *base_addr;
47 void __iomem *pd_addr;
48 void __iomem *pwr_addr;
49 void __iomem *tuner_addr;
50 void __iomem *tuner_en_addr;
51 void __iomem *pcw_addr;
52 const struct mtk_pll_data *data;
53 };
54
to_mtk_clk_pll(struct clk_hw * hw)55 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
56 {
57 return container_of(hw, struct mtk_clk_pll, hw);
58 }
59
mtk_pll_is_prepared(struct clk_hw * hw)60 static int mtk_pll_is_prepared(struct clk_hw *hw)
61 {
62 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
63
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
65 }
66
__mtk_pll_recalc_rate(struct mtk_clk_pll * pll,u32 fin,u32 pcw,int postdiv)67 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
68 u32 pcw, int postdiv)
69 {
70 int pcwbits = pll->data->pcwbits;
71 int pcwfbits;
72 u64 vco;
73 u8 c = 0;
74
75 /* The fractional part of the PLL divider. */
76 pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
77
78 vco = (u64)fin * pcw;
79
80 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
81 c = 1;
82
83 vco >>= pcwfbits;
84
85 if (c)
86 vco++;
87
88 return ((unsigned long)vco + postdiv - 1) / postdiv;
89 }
90
__mtk_pll_tuner_enable(struct mtk_clk_pll * pll)91 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
92 {
93 u32 r;
94
95 if (pll->tuner_en_addr) {
96 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
97 writel(r, pll->tuner_en_addr);
98 } else if (pll->tuner_addr) {
99 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
100 writel(r, pll->tuner_addr);
101 }
102 }
103
__mtk_pll_tuner_disable(struct mtk_clk_pll * pll)104 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
105 {
106 u32 r;
107
108 if (pll->tuner_en_addr) {
109 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
110 writel(r, pll->tuner_en_addr);
111 } else if (pll->tuner_addr) {
112 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
113 writel(r, pll->tuner_addr);
114 }
115 }
116
mtk_pll_set_rate_regs(struct mtk_clk_pll * pll,u32 pcw,int postdiv)117 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
118 int postdiv)
119 {
120 u32 con1, val;
121 int pll_en;
122
123 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
124
125 /* disable tuner */
126 __mtk_pll_tuner_disable(pll);
127
128 /* set postdiv */
129 val = readl(pll->pd_addr);
130 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
131 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
132
133 /* postdiv and pcw need to set at the same time if on same register */
134 if (pll->pd_addr != pll->pcw_addr) {
135 writel(val, pll->pd_addr);
136 val = readl(pll->pcw_addr);
137 }
138
139 /* set pcw */
140 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
141 pll->data->pcw_shift);
142 val |= pcw << pll->data->pcw_shift;
143 writel(val, pll->pcw_addr);
144
145 con1 = readl(pll->base_addr + REG_CON1);
146
147 if (pll_en)
148 con1 |= CON0_PCW_CHG;
149
150 writel(con1, pll->base_addr + REG_CON1);
151 if (pll->tuner_addr)
152 writel(con1 + 1, pll->tuner_addr);
153
154 /* restore tuner_en */
155 __mtk_pll_tuner_enable(pll);
156
157 if (pll_en)
158 udelay(20);
159 }
160
161 /*
162 * mtk_pll_calc_values - calculate good values for a given input frequency.
163 * @pll: The pll
164 * @pcw: The pcw value (output)
165 * @postdiv: The post divider (output)
166 * @freq: The desired target frequency
167 * @fin: The input frequency
168 *
169 */
mtk_pll_calc_values(struct mtk_clk_pll * pll,u32 * pcw,u32 * postdiv,u32 freq,u32 fin)170 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
171 u32 freq, u32 fin)
172 {
173 unsigned long fmin = 1000 * MHZ;
174 const struct mtk_pll_div_table *div_table = pll->data->div_table;
175 u64 _pcw;
176 u32 val;
177
178 if (freq > pll->data->fmax)
179 freq = pll->data->fmax;
180
181 if (div_table) {
182 if (freq > div_table[0].freq)
183 freq = div_table[0].freq;
184
185 for (val = 0; div_table[val + 1].freq != 0; val++) {
186 if (freq > div_table[val + 1].freq)
187 break;
188 }
189 *postdiv = 1 << val;
190 } else {
191 for (val = 0; val < 5; val++) {
192 *postdiv = 1 << val;
193 if ((u64)freq * *postdiv >= fmin)
194 break;
195 }
196 }
197
198 /* _pcw = freq * postdiv / fin * 2^pcwfbits */
199 _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
200 do_div(_pcw, fin);
201
202 *pcw = (u32)_pcw;
203 }
204
mtk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)205 static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
206 unsigned long parent_rate)
207 {
208 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
209 u32 pcw = 0;
210 u32 postdiv;
211
212 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
213 mtk_pll_set_rate_regs(pll, pcw, postdiv);
214
215 return 0;
216 }
217
mtk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)218 static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
220 {
221 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
222 u32 postdiv;
223 u32 pcw;
224
225 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
226 postdiv = 1 << postdiv;
227
228 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
229 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
230
231 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
232 }
233
mtk_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)234 static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
235 unsigned long *prate)
236 {
237 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
238 u32 pcw = 0;
239 int postdiv;
240
241 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
242
243 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
244 }
245
mtk_pll_prepare(struct clk_hw * hw)246 static int mtk_pll_prepare(struct clk_hw *hw)
247 {
248 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
249 u32 r;
250
251 r = readl(pll->pwr_addr) | CON0_PWR_ON;
252 writel(r, pll->pwr_addr);
253 udelay(1);
254
255 r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
256 writel(r, pll->pwr_addr);
257 udelay(1);
258
259 r = readl(pll->base_addr + REG_CON0);
260 r |= pll->data->en_mask;
261 writel(r, pll->base_addr + REG_CON0);
262
263 __mtk_pll_tuner_enable(pll);
264
265 udelay(20);
266
267 if (pll->data->flags & HAVE_RST_BAR) {
268 r = readl(pll->base_addr + REG_CON0);
269 r |= pll->data->rst_bar_mask;
270 writel(r, pll->base_addr + REG_CON0);
271 }
272
273 return 0;
274 }
275
mtk_pll_unprepare(struct clk_hw * hw)276 static void mtk_pll_unprepare(struct clk_hw *hw)
277 {
278 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
279 u32 r;
280
281 if (pll->data->flags & HAVE_RST_BAR) {
282 r = readl(pll->base_addr + REG_CON0);
283 r &= ~pll->data->rst_bar_mask;
284 writel(r, pll->base_addr + REG_CON0);
285 }
286
287 __mtk_pll_tuner_disable(pll);
288
289 r = readl(pll->base_addr + REG_CON0);
290 r &= ~CON0_BASE_EN;
291 writel(r, pll->base_addr + REG_CON0);
292
293 r = readl(pll->pwr_addr) | CON0_ISO_EN;
294 writel(r, pll->pwr_addr);
295
296 r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
297 writel(r, pll->pwr_addr);
298 }
299
300 static const struct clk_ops mtk_pll_ops = {
301 .is_prepared = mtk_pll_is_prepared,
302 .prepare = mtk_pll_prepare,
303 .unprepare = mtk_pll_unprepare,
304 .recalc_rate = mtk_pll_recalc_rate,
305 .round_rate = mtk_pll_round_rate,
306 .set_rate = mtk_pll_set_rate,
307 };
308
mtk_clk_register_pll(const struct mtk_pll_data * data,void __iomem * base)309 static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
310 void __iomem *base)
311 {
312 struct mtk_clk_pll *pll;
313 struct clk_init_data init = {};
314 struct clk *clk;
315 const char *parent_name = "clk26m";
316
317 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
318 if (!pll)
319 return ERR_PTR(-ENOMEM);
320
321 pll->base_addr = base + data->reg;
322 pll->pwr_addr = base + data->pwr_reg;
323 pll->pd_addr = base + data->pd_reg;
324 pll->pcw_addr = base + data->pcw_reg;
325 if (data->tuner_reg)
326 pll->tuner_addr = base + data->tuner_reg;
327 if (data->tuner_en_reg)
328 pll->tuner_en_addr = base + data->tuner_en_reg;
329 pll->hw.init = &init;
330 pll->data = data;
331
332 init.name = data->name;
333 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
334 init.ops = &mtk_pll_ops;
335 if (data->parent_name)
336 init.parent_names = &data->parent_name;
337 else
338 init.parent_names = &parent_name;
339 init.num_parents = 1;
340
341 clk = clk_register(NULL, &pll->hw);
342
343 if (IS_ERR(clk))
344 kfree(pll);
345
346 return clk;
347 }
348
mtk_clk_register_plls(struct device_node * node,const struct mtk_pll_data * plls,int num_plls,struct clk_onecell_data * clk_data)349 void mtk_clk_register_plls(struct device_node *node,
350 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
351 {
352 void __iomem *base;
353 int i;
354 struct clk *clk;
355
356 base = of_iomap(node, 0);
357 if (!base) {
358 pr_err("%s(): ioremap failed\n", __func__);
359 return;
360 }
361
362 for (i = 0; i < num_plls; i++) {
363 const struct mtk_pll_data *pll = &plls[i];
364
365 clk = mtk_clk_register_pll(pll, base);
366
367 if (IS_ERR(clk)) {
368 pr_err("Failed to register clk %s: %ld\n",
369 pll->name, PTR_ERR(clk));
370 continue;
371 }
372
373 clk_data->clks[pll->id] = clk;
374 }
375 }
376