1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_platform.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/pm_runtime.h>
34
35 #include <linux/platform_data/mtd-nand-omap2.h>
36
37 #include <asm/mach-types.h>
38
39 #define DEVICE_NAME "omap-gpmc"
40
41 /* GPMC register offsets */
42 #define GPMC_REVISION 0x00
43 #define GPMC_SYSCONFIG 0x10
44 #define GPMC_SYSSTATUS 0x14
45 #define GPMC_IRQSTATUS 0x18
46 #define GPMC_IRQENABLE 0x1c
47 #define GPMC_TIMEOUT_CONTROL 0x40
48 #define GPMC_ERR_ADDRESS 0x44
49 #define GPMC_ERR_TYPE 0x48
50 #define GPMC_CONFIG 0x50
51 #define GPMC_STATUS 0x54
52 #define GPMC_PREFETCH_CONFIG1 0x1e0
53 #define GPMC_PREFETCH_CONFIG2 0x1e4
54 #define GPMC_PREFETCH_CONTROL 0x1ec
55 #define GPMC_PREFETCH_STATUS 0x1f0
56 #define GPMC_ECC_CONFIG 0x1f4
57 #define GPMC_ECC_CONTROL 0x1f8
58 #define GPMC_ECC_SIZE_CONFIG 0x1fc
59 #define GPMC_ECC1_RESULT 0x200
60 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
67
68 /* GPMC ECC control settings */
69 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
70 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
71 #define GPMC_ECC_CTRL_ECCREG1 0x001
72 #define GPMC_ECC_CTRL_ECCREG2 0x002
73 #define GPMC_ECC_CTRL_ECCREG3 0x003
74 #define GPMC_ECC_CTRL_ECCREG4 0x004
75 #define GPMC_ECC_CTRL_ECCREG5 0x005
76 #define GPMC_ECC_CTRL_ECCREG6 0x006
77 #define GPMC_ECC_CTRL_ECCREG7 0x007
78 #define GPMC_ECC_CTRL_ECCREG8 0x008
79 #define GPMC_ECC_CTRL_ECCREG9 0x009
80
81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
82
83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
84
85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91
92 #define GPMC_CS0_OFFSET 0x60
93 #define GPMC_CS_SIZE 0x30
94 #define GPMC_BCH_SIZE 0x10
95
96 /*
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
100 * As GPMC minimum partition size is 16MB we can only start from
101 * there.
102 */
103 #define GPMC_MEM_START 0x1000000
104 #define GPMC_MEM_END 0x3FFFFFFF
105
106 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
107 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
108
109 #define CS_NUM_SHIFT 24
110 #define ENABLE_PREFETCH (0x1 << 7)
111 #define DMA_MPU_MODE 2
112
113 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
114 #define GPMC_REVISION_MINOR(l) (l & 0xf)
115
116 #define GPMC_HAS_WR_ACCESS 0x1
117 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
118 #define GPMC_HAS_MUX_AAD 0x4
119
120 #define GPMC_NR_WAITPINS 4
121
122 #define GPMC_CS_CONFIG1 0x00
123 #define GPMC_CS_CONFIG2 0x04
124 #define GPMC_CS_CONFIG3 0x08
125 #define GPMC_CS_CONFIG4 0x0c
126 #define GPMC_CS_CONFIG5 0x10
127 #define GPMC_CS_CONFIG6 0x14
128 #define GPMC_CS_CONFIG7 0x18
129 #define GPMC_CS_NAND_COMMAND 0x1c
130 #define GPMC_CS_NAND_ADDRESS 0x20
131 #define GPMC_CS_NAND_DATA 0x24
132
133 /* Control Commands */
134 #define GPMC_CONFIG_RDY_BSY 0x00000001
135 #define GPMC_CONFIG_DEV_SIZE 0x00000002
136 #define GPMC_CONFIG_DEV_TYPE 0x00000003
137
138 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
139 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
140 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
141 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
142 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
143 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
144 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
146 /** CLKACTIVATIONTIME Max Ticks */
147 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
148 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
149 /** ATTACHEDDEVICEPAGELENGTH Max Value */
150 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
151 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
152 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
154 /** WAITMONITORINGTIME Max Ticks */
155 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
157 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
158 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
159 /** DEVICESIZE Max Value */
160 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
161 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
162 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
163 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
164 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
165 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
166 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
167 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
168 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
169 #define GPMC_CONFIG7_CSVALID (1 << 6)
170
171 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
172 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
173 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
174 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
175 /* All CONFIG7 bits except reserved bits */
176 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
177 GPMC_CONFIG7_CSVALID_MASK | \
178 GPMC_CONFIG7_MASKADDRESS_MASK)
179
180 #define GPMC_DEVICETYPE_NOR 0
181 #define GPMC_DEVICETYPE_NAND 2
182 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
183 #define WR_RD_PIN_MONITORING 0x00600000
184
185 /* ECC commands */
186 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
187 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
188 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
189
190 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
191
192 enum gpmc_clk_domain {
193 GPMC_CD_FCLK,
194 GPMC_CD_CLK
195 };
196
197 struct gpmc_cs_data {
198 const char *name;
199
200 #define GPMC_CS_RESERVED (1 << 0)
201 u32 flags;
202
203 struct resource mem;
204 };
205
206 /* Structure to save gpmc cs context */
207 struct gpmc_cs_config {
208 u32 config1;
209 u32 config2;
210 u32 config3;
211 u32 config4;
212 u32 config5;
213 u32 config6;
214 u32 config7;
215 int is_valid;
216 };
217
218 /*
219 * Structure to save/restore gpmc context
220 * to support core off on OMAP3
221 */
222 struct omap3_gpmc_regs {
223 u32 sysconfig;
224 u32 irqenable;
225 u32 timeout_ctrl;
226 u32 config;
227 u32 prefetch_config1;
228 u32 prefetch_config2;
229 u32 prefetch_control;
230 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
231 };
232
233 struct gpmc_device {
234 struct device *dev;
235 int irq;
236 struct irq_chip irq_chip;
237 struct gpio_chip gpio_chip;
238 int nirqs;
239 };
240
241 static struct irq_domain *gpmc_irq_domain;
242
243 static struct resource gpmc_mem_root;
244 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
245 static DEFINE_SPINLOCK(gpmc_mem_lock);
246 /* Define chip-selects as reserved by default until probe completes */
247 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
248 static unsigned int gpmc_nr_waitpins;
249 static resource_size_t phys_base, mem_size;
250 static unsigned gpmc_capability;
251 static void __iomem *gpmc_base;
252
253 static struct clk *gpmc_l3_clk;
254
255 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
256
gpmc_write_reg(int idx,u32 val)257 static void gpmc_write_reg(int idx, u32 val)
258 {
259 writel_relaxed(val, gpmc_base + idx);
260 }
261
gpmc_read_reg(int idx)262 static u32 gpmc_read_reg(int idx)
263 {
264 return readl_relaxed(gpmc_base + idx);
265 }
266
gpmc_cs_write_reg(int cs,int idx,u32 val)267 void gpmc_cs_write_reg(int cs, int idx, u32 val)
268 {
269 void __iomem *reg_addr;
270
271 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
272 writel_relaxed(val, reg_addr);
273 }
274
gpmc_cs_read_reg(int cs,int idx)275 static u32 gpmc_cs_read_reg(int cs, int idx)
276 {
277 void __iomem *reg_addr;
278
279 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
280 return readl_relaxed(reg_addr);
281 }
282
283 /* TODO: Add support for gpmc_fck to clock framework and use it */
gpmc_get_fclk_period(void)284 static unsigned long gpmc_get_fclk_period(void)
285 {
286 unsigned long rate = clk_get_rate(gpmc_l3_clk);
287
288 rate /= 1000;
289 rate = 1000000000 / rate; /* In picoseconds */
290
291 return rate;
292 }
293
294 /**
295 * gpmc_get_clk_period - get period of selected clock domain in ps
296 * @cs Chip Select Region.
297 * @cd Clock Domain.
298 *
299 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
300 * prior to calling this function with GPMC_CD_CLK.
301 */
gpmc_get_clk_period(int cs,enum gpmc_clk_domain cd)302 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303 {
304
305 unsigned long tick_ps = gpmc_get_fclk_period();
306 u32 l;
307 int div;
308
309 switch (cd) {
310 case GPMC_CD_CLK:
311 /* get current clk divider */
312 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
313 div = (l & 0x03) + 1;
314 /* get GPMC_CLK period */
315 tick_ps *= div;
316 break;
317 case GPMC_CD_FCLK:
318 /* FALL-THROUGH */
319 default:
320 break;
321 }
322
323 return tick_ps;
324
325 }
326
gpmc_ns_to_clk_ticks(unsigned int time_ns,int cs,enum gpmc_clk_domain cd)327 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
328 enum gpmc_clk_domain cd)
329 {
330 unsigned long tick_ps;
331
332 /* Calculate in picosecs to yield more exact results */
333 tick_ps = gpmc_get_clk_period(cs, cd);
334
335 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
336 }
337
gpmc_ns_to_ticks(unsigned int time_ns)338 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
339 {
340 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
341 }
342
gpmc_ps_to_ticks(unsigned int time_ps)343 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
344 {
345 unsigned long tick_ps;
346
347 /* Calculate in picosecs to yield more exact results */
348 tick_ps = gpmc_get_fclk_period();
349
350 return (time_ps + tick_ps - 1) / tick_ps;
351 }
352
gpmc_clk_ticks_to_ns(unsigned int ticks,int cs,enum gpmc_clk_domain cd)353 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
354 enum gpmc_clk_domain cd)
355 {
356 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
357 }
358
gpmc_ticks_to_ns(unsigned int ticks)359 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
360 {
361 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
362 }
363
gpmc_ticks_to_ps(unsigned int ticks)364 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
365 {
366 return ticks * gpmc_get_fclk_period();
367 }
368
gpmc_round_ps_to_ticks(unsigned int time_ps)369 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
370 {
371 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
372
373 return ticks * gpmc_get_fclk_period();
374 }
375
gpmc_cs_modify_reg(int cs,int reg,u32 mask,bool value)376 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
377 {
378 u32 l;
379
380 l = gpmc_cs_read_reg(cs, reg);
381 if (value)
382 l |= mask;
383 else
384 l &= ~mask;
385 gpmc_cs_write_reg(cs, reg, l);
386 }
387
gpmc_cs_bool_timings(int cs,const struct gpmc_bool_timings * p)388 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
389 {
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
391 GPMC_CONFIG1_TIME_PARA_GRAN,
392 p->time_para_granularity);
393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
394 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
396 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
397 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
398 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
399 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
400 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
403 p->cycle2cyclesamecsen);
404 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
405 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
406 p->cycle2cyclediffcsen);
407 }
408
409 #ifdef CONFIG_OMAP_GPMC_DEBUG
410 /**
411 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
412 * @cs: Chip Select Region
413 * @reg: GPMC_CS_CONFIGn register offset.
414 * @st_bit: Start Bit
415 * @end_bit: End Bit. Must be >= @st_bit.
416 * @ma:x Maximum parameter value (before optional @shift).
417 * If 0, maximum is as high as @st_bit and @end_bit allow.
418 * @name: DTS node name, w/o "gpmc,"
419 * @cd: Clock Domain of timing parameter.
420 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
421 * @raw: Raw Format Option.
422 * raw format: gpmc,name = <value>
423 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
424 * Where x ns -- y ns result in the same tick value.
425 * When @max is exceeded, "invalid" is printed inside comment.
426 * @noval: Parameter values equal to 0 are not printed.
427 * @return: Specified timing parameter (after optional @shift).
428 *
429 */
get_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,const char * name,const enum gpmc_clk_domain cd,int shift,bool raw,bool noval)430 static int get_gpmc_timing_reg(
431 /* timing specifiers */
432 int cs, int reg, int st_bit, int end_bit, int max,
433 const char *name, const enum gpmc_clk_domain cd,
434 /* value transform */
435 int shift,
436 /* format specifiers */
437 bool raw, bool noval)
438 {
439 u32 l;
440 int nr_bits;
441 int mask;
442 bool invalid;
443
444 l = gpmc_cs_read_reg(cs, reg);
445 nr_bits = end_bit - st_bit + 1;
446 mask = (1 << nr_bits) - 1;
447 l = (l >> st_bit) & mask;
448 if (!max)
449 max = mask;
450 invalid = l > max;
451 if (shift)
452 l = (shift << l);
453 if (noval && (l == 0))
454 return 0;
455 if (!raw) {
456 /* DTS tick format for timings in ns */
457 unsigned int time_ns;
458 unsigned int time_ns_min = 0;
459
460 if (l)
461 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
462 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
463 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
464 name, time_ns, time_ns_min, time_ns, l,
465 invalid ? "; invalid " : " ");
466 } else {
467 /* raw format */
468 pr_info("gpmc,%s = <%u>;%s\n", name, l,
469 invalid ? " /* invalid */" : "");
470 }
471
472 return l;
473 }
474
475 #define GPMC_PRINT_CONFIG(cs, config) \
476 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
477 gpmc_cs_read_reg(cs, config))
478 #define GPMC_GET_RAW(reg, st, end, field) \
479 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
480 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
481 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
482 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
484 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
486 #define GPMC_GET_TICKS(reg, st, end, field) \
487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
488 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
489 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
490 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
491 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
492
gpmc_show_regs(int cs,const char * desc)493 static void gpmc_show_regs(int cs, const char *desc)
494 {
495 pr_info("gpmc cs%i %s:\n", cs, desc);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
502 }
503
504 /*
505 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
506 * see commit c9fb809.
507 */
gpmc_cs_show_timings(int cs,const char * desc)508 static void gpmc_cs_show_timings(int cs, const char *desc)
509 {
510 gpmc_show_regs(cs, desc);
511
512 pr_info("gpmc cs%i access configuration:\n", cs);
513 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
515 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
516 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
517 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
520 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
521 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
522 "burst-length");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
528
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
530
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
532
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
535
536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
538
539 pr_info("gpmc cs%i timings configuration:\n", cs);
540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
543
544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
547 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
550 "adv-aad-mux-rd-off-ns");
551 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
552 "adv-aad-mux-wr-off-ns");
553 }
554
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
557 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
560 }
561 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
563
564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
567
568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
569
570 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
571 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
572
573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
574 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
575 "wait-monitoring-ns", GPMC_CD_CLK);
576 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
577 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
578 "clk-activation-ns", GPMC_CD_FCLK);
579
580 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
581 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
582 }
583 #else
gpmc_cs_show_timings(int cs,const char * desc)584 static inline void gpmc_cs_show_timings(int cs, const char *desc)
585 {
586 }
587 #endif
588
589 /**
590 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
591 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
592 * prior to calling this function with @cd equal to GPMC_CD_CLK.
593 *
594 * @cs: Chip Select Region.
595 * @reg: GPMC_CS_CONFIGn register offset.
596 * @st_bit: Start Bit
597 * @end_bit: End Bit. Must be >= @st_bit.
598 * @max: Maximum parameter value.
599 * If 0, maximum is as high as @st_bit and @end_bit allow.
600 * @time: Timing parameter in ns.
601 * @cd: Timing parameter clock domain.
602 * @name: Timing parameter name.
603 * @return: 0 on success, -1 on error.
604 */
set_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,int time,enum gpmc_clk_domain cd,const char * name)605 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
606 int time, enum gpmc_clk_domain cd, const char *name)
607 {
608 u32 l;
609 int ticks, mask, nr_bits;
610
611 if (time == 0)
612 ticks = 0;
613 else
614 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
615 nr_bits = end_bit - st_bit + 1;
616 mask = (1 << nr_bits) - 1;
617
618 if (!max)
619 max = mask;
620
621 if (ticks > max) {
622 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
623 __func__, cs, name, time, ticks, max);
624
625 return -1;
626 }
627
628 l = gpmc_cs_read_reg(cs, reg);
629 #ifdef CONFIG_OMAP_GPMC_DEBUG
630 pr_info(
631 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
632 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
633 (l >> st_bit) & mask, time);
634 #endif
635 l &= ~(mask << st_bit);
636 l |= ticks << st_bit;
637 gpmc_cs_write_reg(cs, reg, l);
638
639 return 0;
640 }
641
642 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
643 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
644 t->field, (cd), #field) < 0) \
645 return -1
646
647 #define GPMC_SET_ONE(reg, st, end, field) \
648 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
649
650 /**
651 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
652 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
653 * read --> don't sample bus too early
654 * write --> data is longer on bus
655 *
656 * Formula:
657 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
658 * / waitmonitoring_ticks)
659 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
660 * div <= 0 check.
661 *
662 * @wait_monitoring: WAITMONITORINGTIME in ns.
663 * @return: -1 on failure to scale, else proper divider > 0.
664 */
gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)665 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
666 {
667
668 int div = gpmc_ns_to_ticks(wait_monitoring);
669
670 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
671 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
672
673 if (div > 4)
674 return -1;
675 if (div <= 0)
676 div = 1;
677
678 return div;
679
680 }
681
682 /**
683 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
684 * @sync_clk: GPMC_CLK period in ps.
685 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
686 * Else, returns -1.
687 */
gpmc_calc_divider(unsigned int sync_clk)688 int gpmc_calc_divider(unsigned int sync_clk)
689 {
690 int div = gpmc_ps_to_ticks(sync_clk);
691
692 if (div > 4)
693 return -1;
694 if (div <= 0)
695 div = 1;
696
697 return div;
698 }
699
700 /**
701 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
702 * @cs: Chip Select Region.
703 * @t: GPMC timing parameters.
704 * @s: GPMC timing settings.
705 * @return: 0 on success, -1 on error.
706 */
gpmc_cs_set_timings(int cs,const struct gpmc_timings * t,const struct gpmc_settings * s)707 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
708 const struct gpmc_settings *s)
709 {
710 int div;
711 u32 l;
712
713 div = gpmc_calc_divider(t->sync_clk);
714 if (div < 0)
715 return div;
716
717 /*
718 * See if we need to change the divider for waitmonitoringtime.
719 *
720 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
721 * pure asynchronous accesses, i.e. both read and write asynchronous.
722 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
723 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
724 *
725 * This statement must not change div to scale async WAITMONITORINGTIME
726 * to protect mixed synchronous and asynchronous accesses.
727 *
728 * We raise an error later if WAITMONITORINGTIME does not fit.
729 */
730 if (!s->sync_read && !s->sync_write &&
731 (s->wait_on_read || s->wait_on_write)
732 ) {
733
734 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
735 if (div < 0) {
736 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
737 __func__,
738 t->wait_monitoring
739 );
740 return -1;
741 }
742 }
743
744 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
745 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
746 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
747
748 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
749 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
751 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
752 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
753 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
754 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
755 }
756
757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
759 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
760 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
762 }
763 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
764 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
765
766 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
767 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
769
770 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
771
772 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
773 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
774
775 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
776 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
777 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
778 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
779
780 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
781 l &= ~0x03;
782 l |= (div - 1);
783 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
784
785 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
786 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
787 wait_monitoring, GPMC_CD_CLK);
788 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
789 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
790 clk_activation, GPMC_CD_FCLK);
791
792 #ifdef CONFIG_OMAP_GPMC_DEBUG
793 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
794 cs, (div * gpmc_get_fclk_period()) / 1000, div);
795 #endif
796
797 gpmc_cs_bool_timings(cs, &t->bool_timings);
798 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
799
800 return 0;
801 }
802
gpmc_cs_set_memconf(int cs,u32 base,u32 size)803 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
804 {
805 u32 l;
806 u32 mask;
807
808 /*
809 * Ensure that base address is aligned on a
810 * boundary equal to or greater than size.
811 */
812 if (base & (size - 1))
813 return -EINVAL;
814
815 base >>= GPMC_CHUNK_SHIFT;
816 mask = (1 << GPMC_SECTION_SHIFT) - size;
817 mask >>= GPMC_CHUNK_SHIFT;
818 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
819
820 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
821 l &= ~GPMC_CONFIG7_MASK;
822 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
823 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
824 l |= GPMC_CONFIG7_CSVALID;
825 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
826
827 return 0;
828 }
829
gpmc_cs_enable_mem(int cs)830 static void gpmc_cs_enable_mem(int cs)
831 {
832 u32 l;
833
834 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
835 l |= GPMC_CONFIG7_CSVALID;
836 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
837 }
838
gpmc_cs_disable_mem(int cs)839 static void gpmc_cs_disable_mem(int cs)
840 {
841 u32 l;
842
843 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
844 l &= ~GPMC_CONFIG7_CSVALID;
845 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
846 }
847
gpmc_cs_get_memconf(int cs,u32 * base,u32 * size)848 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
849 {
850 u32 l;
851 u32 mask;
852
853 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
854 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
855 mask = (l >> 8) & 0x0f;
856 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
857 }
858
gpmc_cs_mem_enabled(int cs)859 static int gpmc_cs_mem_enabled(int cs)
860 {
861 u32 l;
862
863 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
864 return l & GPMC_CONFIG7_CSVALID;
865 }
866
gpmc_cs_set_reserved(int cs,int reserved)867 static void gpmc_cs_set_reserved(int cs, int reserved)
868 {
869 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
870
871 gpmc->flags |= GPMC_CS_RESERVED;
872 }
873
gpmc_cs_reserved(int cs)874 static bool gpmc_cs_reserved(int cs)
875 {
876 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
877
878 return gpmc->flags & GPMC_CS_RESERVED;
879 }
880
gpmc_cs_set_name(int cs,const char * name)881 static void gpmc_cs_set_name(int cs, const char *name)
882 {
883 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
884
885 gpmc->name = name;
886 }
887
gpmc_cs_get_name(int cs)888 static const char *gpmc_cs_get_name(int cs)
889 {
890 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
891
892 return gpmc->name;
893 }
894
gpmc_mem_align(unsigned long size)895 static unsigned long gpmc_mem_align(unsigned long size)
896 {
897 int order;
898
899 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
900 order = GPMC_CHUNK_SHIFT - 1;
901 do {
902 size >>= 1;
903 order++;
904 } while (size);
905 size = 1 << order;
906 return size;
907 }
908
gpmc_cs_insert_mem(int cs,unsigned long base,unsigned long size)909 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
910 {
911 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
912 struct resource *res = &gpmc->mem;
913 int r;
914
915 size = gpmc_mem_align(size);
916 spin_lock(&gpmc_mem_lock);
917 res->start = base;
918 res->end = base + size - 1;
919 r = request_resource(&gpmc_mem_root, res);
920 spin_unlock(&gpmc_mem_lock);
921
922 return r;
923 }
924
gpmc_cs_delete_mem(int cs)925 static int gpmc_cs_delete_mem(int cs)
926 {
927 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
928 struct resource *res = &gpmc->mem;
929 int r;
930
931 spin_lock(&gpmc_mem_lock);
932 r = release_resource(res);
933 res->start = 0;
934 res->end = 0;
935 spin_unlock(&gpmc_mem_lock);
936
937 return r;
938 }
939
940 /**
941 * gpmc_cs_remap - remaps a chip-select physical base address
942 * @cs: chip-select to remap
943 * @base: physical base address to re-map chip-select to
944 *
945 * Re-maps a chip-select to a new physical base address specified by
946 * "base". Returns 0 on success and appropriate negative error code
947 * on failure.
948 */
gpmc_cs_remap(int cs,u32 base)949 static int gpmc_cs_remap(int cs, u32 base)
950 {
951 int ret;
952 u32 old_base, size;
953
954 if (cs >= gpmc_cs_num) {
955 pr_err("%s: requested chip-select is disabled\n", __func__);
956 return -ENODEV;
957 }
958
959 /*
960 * Make sure we ignore any device offsets from the GPMC partition
961 * allocated for the chip select and that the new base confirms
962 * to the GPMC 16MB minimum granularity.
963 */
964 base &= ~(SZ_16M - 1);
965
966 gpmc_cs_get_memconf(cs, &old_base, &size);
967 if (base == old_base)
968 return 0;
969
970 ret = gpmc_cs_delete_mem(cs);
971 if (ret < 0)
972 return ret;
973
974 ret = gpmc_cs_insert_mem(cs, base, size);
975 if (ret < 0)
976 return ret;
977
978 ret = gpmc_cs_set_memconf(cs, base, size);
979
980 return ret;
981 }
982
gpmc_cs_request(int cs,unsigned long size,unsigned long * base)983 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
984 {
985 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
986 struct resource *res = &gpmc->mem;
987 int r = -1;
988
989 if (cs >= gpmc_cs_num) {
990 pr_err("%s: requested chip-select is disabled\n", __func__);
991 return -ENODEV;
992 }
993 size = gpmc_mem_align(size);
994 if (size > (1 << GPMC_SECTION_SHIFT))
995 return -ENOMEM;
996
997 spin_lock(&gpmc_mem_lock);
998 if (gpmc_cs_reserved(cs)) {
999 r = -EBUSY;
1000 goto out;
1001 }
1002 if (gpmc_cs_mem_enabled(cs))
1003 r = adjust_resource(res, res->start & ~(size - 1), size);
1004 if (r < 0)
1005 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1006 size, NULL, NULL);
1007 if (r < 0)
1008 goto out;
1009
1010 /* Disable CS while changing base address and size mask */
1011 gpmc_cs_disable_mem(cs);
1012
1013 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1014 if (r < 0) {
1015 release_resource(res);
1016 goto out;
1017 }
1018
1019 /* Enable CS */
1020 gpmc_cs_enable_mem(cs);
1021 *base = res->start;
1022 gpmc_cs_set_reserved(cs, 1);
1023 out:
1024 spin_unlock(&gpmc_mem_lock);
1025 return r;
1026 }
1027 EXPORT_SYMBOL(gpmc_cs_request);
1028
gpmc_cs_free(int cs)1029 void gpmc_cs_free(int cs)
1030 {
1031 struct gpmc_cs_data *gpmc;
1032 struct resource *res;
1033
1034 spin_lock(&gpmc_mem_lock);
1035 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1036 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037 BUG();
1038 spin_unlock(&gpmc_mem_lock);
1039 return;
1040 }
1041 gpmc = &gpmc_cs[cs];
1042 res = &gpmc->mem;
1043
1044 gpmc_cs_disable_mem(cs);
1045 if (res->flags)
1046 release_resource(res);
1047 gpmc_cs_set_reserved(cs, 0);
1048 spin_unlock(&gpmc_mem_lock);
1049 }
1050 EXPORT_SYMBOL(gpmc_cs_free);
1051
1052 /**
1053 * gpmc_configure - write request to configure gpmc
1054 * @cmd: command type
1055 * @wval: value to write
1056 * @return status of the operation
1057 */
gpmc_configure(int cmd,int wval)1058 int gpmc_configure(int cmd, int wval)
1059 {
1060 u32 regval;
1061
1062 switch (cmd) {
1063 case GPMC_CONFIG_WP:
1064 regval = gpmc_read_reg(GPMC_CONFIG);
1065 if (wval)
1066 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1067 else
1068 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1069 gpmc_write_reg(GPMC_CONFIG, regval);
1070 break;
1071
1072 default:
1073 pr_err("%s: command not supported\n", __func__);
1074 return -EINVAL;
1075 }
1076
1077 return 0;
1078 }
1079 EXPORT_SYMBOL(gpmc_configure);
1080
gpmc_nand_writebuffer_empty(void)1081 static bool gpmc_nand_writebuffer_empty(void)
1082 {
1083 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1084 return true;
1085
1086 return false;
1087 }
1088
1089 static struct gpmc_nand_ops nand_ops = {
1090 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1091 };
1092
1093 /**
1094 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1095 * @regs: the GPMC NAND register map exclusive for NAND use.
1096 * @cs: GPMC chip select number on which the NAND sits. The
1097 * register map returned will be specific to this chip select.
1098 *
1099 * Returns NULL on error e.g. invalid cs.
1100 */
gpmc_omap_get_nand_ops(struct gpmc_nand_regs * reg,int cs)1101 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1102 {
1103 int i;
1104
1105 if (cs >= gpmc_cs_num)
1106 return NULL;
1107
1108 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1109 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1110 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1111 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1112 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1113 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1114 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1115 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1116 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1117 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1118 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1119 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1120 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1121 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1122
1123 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1124 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1125 GPMC_BCH_SIZE * i;
1126 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1127 GPMC_BCH_SIZE * i;
1128 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1129 GPMC_BCH_SIZE * i;
1130 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1131 GPMC_BCH_SIZE * i;
1132 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1133 i * GPMC_BCH_SIZE;
1134 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1135 i * GPMC_BCH_SIZE;
1136 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1137 i * GPMC_BCH_SIZE;
1138 }
1139
1140 return &nand_ops;
1141 }
1142 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1143
gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings * t,struct gpmc_settings * s,int freq,int latency)1144 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1145 struct gpmc_settings *s,
1146 int freq, int latency)
1147 {
1148 struct gpmc_device_timings dev_t;
1149 const int t_cer = 15;
1150 const int t_avdp = 12;
1151 const int t_cez = 20; /* max of t_cez, t_oez */
1152 const int t_wpl = 40;
1153 const int t_wph = 30;
1154 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1155
1156 switch (freq) {
1157 case 104:
1158 min_gpmc_clk_period = 9600; /* 104 MHz */
1159 t_ces = 3;
1160 t_avds = 4;
1161 t_avdh = 2;
1162 t_ach = 3;
1163 t_aavdh = 6;
1164 t_rdyo = 6;
1165 break;
1166 case 83:
1167 min_gpmc_clk_period = 12000; /* 83 MHz */
1168 t_ces = 5;
1169 t_avds = 4;
1170 t_avdh = 2;
1171 t_ach = 6;
1172 t_aavdh = 6;
1173 t_rdyo = 9;
1174 break;
1175 case 66:
1176 min_gpmc_clk_period = 15000; /* 66 MHz */
1177 t_ces = 6;
1178 t_avds = 5;
1179 t_avdh = 2;
1180 t_ach = 6;
1181 t_aavdh = 6;
1182 t_rdyo = 11;
1183 break;
1184 default:
1185 min_gpmc_clk_period = 18500; /* 54 MHz */
1186 t_ces = 7;
1187 t_avds = 7;
1188 t_avdh = 7;
1189 t_ach = 9;
1190 t_aavdh = 7;
1191 t_rdyo = 15;
1192 break;
1193 }
1194
1195 /* Set synchronous read timings */
1196 memset(&dev_t, 0, sizeof(dev_t));
1197
1198 if (!s->sync_write) {
1199 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1200 dev_t.t_wpl = t_wpl * 1000;
1201 dev_t.t_wph = t_wph * 1000;
1202 dev_t.t_aavdh = t_aavdh * 1000;
1203 }
1204 dev_t.ce_xdelay = true;
1205 dev_t.avd_xdelay = true;
1206 dev_t.oe_xdelay = true;
1207 dev_t.we_xdelay = true;
1208 dev_t.clk = min_gpmc_clk_period;
1209 dev_t.t_bacc = dev_t.clk;
1210 dev_t.t_ces = t_ces * 1000;
1211 dev_t.t_avds = t_avds * 1000;
1212 dev_t.t_avdh = t_avdh * 1000;
1213 dev_t.t_ach = t_ach * 1000;
1214 dev_t.cyc_iaa = (latency + 1);
1215 dev_t.t_cez_r = t_cez * 1000;
1216 dev_t.t_cez_w = dev_t.t_cez_r;
1217 dev_t.cyc_aavdh_oe = 1;
1218 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1219
1220 gpmc_calc_timings(t, s, &dev_t);
1221 }
1222
gpmc_omap_onenand_set_timings(struct device * dev,int cs,int freq,int latency,struct gpmc_onenand_info * info)1223 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1224 int latency,
1225 struct gpmc_onenand_info *info)
1226 {
1227 int ret;
1228 struct gpmc_timings gpmc_t;
1229 struct gpmc_settings gpmc_s;
1230
1231 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1232
1233 info->sync_read = gpmc_s.sync_read;
1234 info->sync_write = gpmc_s.sync_write;
1235 info->burst_len = gpmc_s.burst_len;
1236
1237 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1238 return 0;
1239
1240 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1241
1242 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1243 if (ret < 0)
1244 return ret;
1245
1246 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1247 }
1248 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1249
gpmc_get_client_irq(unsigned irq_config)1250 int gpmc_get_client_irq(unsigned irq_config)
1251 {
1252 if (!gpmc_irq_domain) {
1253 pr_warn("%s called before GPMC IRQ domain available\n",
1254 __func__);
1255 return 0;
1256 }
1257
1258 /* we restrict this to NAND IRQs only */
1259 if (irq_config >= GPMC_NR_NAND_IRQS)
1260 return 0;
1261
1262 return irq_create_mapping(gpmc_irq_domain, irq_config);
1263 }
1264
gpmc_irq_endis(unsigned long hwirq,bool endis)1265 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1266 {
1267 u32 regval;
1268
1269 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1270 if (hwirq >= GPMC_NR_NAND_IRQS)
1271 hwirq += 8 - GPMC_NR_NAND_IRQS;
1272
1273 regval = gpmc_read_reg(GPMC_IRQENABLE);
1274 if (endis)
1275 regval |= BIT(hwirq);
1276 else
1277 regval &= ~BIT(hwirq);
1278 gpmc_write_reg(GPMC_IRQENABLE, regval);
1279
1280 return 0;
1281 }
1282
gpmc_irq_disable(struct irq_data * p)1283 static void gpmc_irq_disable(struct irq_data *p)
1284 {
1285 gpmc_irq_endis(p->hwirq, false);
1286 }
1287
gpmc_irq_enable(struct irq_data * p)1288 static void gpmc_irq_enable(struct irq_data *p)
1289 {
1290 gpmc_irq_endis(p->hwirq, true);
1291 }
1292
gpmc_irq_mask(struct irq_data * d)1293 static void gpmc_irq_mask(struct irq_data *d)
1294 {
1295 gpmc_irq_endis(d->hwirq, false);
1296 }
1297
gpmc_irq_unmask(struct irq_data * d)1298 static void gpmc_irq_unmask(struct irq_data *d)
1299 {
1300 gpmc_irq_endis(d->hwirq, true);
1301 }
1302
gpmc_irq_edge_config(unsigned long hwirq,bool rising_edge)1303 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1304 {
1305 u32 regval;
1306
1307 /* NAND IRQs polarity is not configurable */
1308 if (hwirq < GPMC_NR_NAND_IRQS)
1309 return;
1310
1311 /* WAITPIN starts at BIT 8 */
1312 hwirq += 8 - GPMC_NR_NAND_IRQS;
1313
1314 regval = gpmc_read_reg(GPMC_CONFIG);
1315 if (rising_edge)
1316 regval &= ~BIT(hwirq);
1317 else
1318 regval |= BIT(hwirq);
1319
1320 gpmc_write_reg(GPMC_CONFIG, regval);
1321 }
1322
gpmc_irq_ack(struct irq_data * d)1323 static void gpmc_irq_ack(struct irq_data *d)
1324 {
1325 unsigned int hwirq = d->hwirq;
1326
1327 /* skip reserved bits */
1328 if (hwirq >= GPMC_NR_NAND_IRQS)
1329 hwirq += 8 - GPMC_NR_NAND_IRQS;
1330
1331 /* Setting bit to 1 clears (or Acks) the interrupt */
1332 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1333 }
1334
gpmc_irq_set_type(struct irq_data * d,unsigned int trigger)1335 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1336 {
1337 /* can't set type for NAND IRQs */
1338 if (d->hwirq < GPMC_NR_NAND_IRQS)
1339 return -EINVAL;
1340
1341 /* We can support either rising or falling edge at a time */
1342 if (trigger == IRQ_TYPE_EDGE_FALLING)
1343 gpmc_irq_edge_config(d->hwirq, false);
1344 else if (trigger == IRQ_TYPE_EDGE_RISING)
1345 gpmc_irq_edge_config(d->hwirq, true);
1346 else
1347 return -EINVAL;
1348
1349 return 0;
1350 }
1351
gpmc_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)1352 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1353 irq_hw_number_t hw)
1354 {
1355 struct gpmc_device *gpmc = d->host_data;
1356
1357 irq_set_chip_data(virq, gpmc);
1358 if (hw < GPMC_NR_NAND_IRQS) {
1359 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1360 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1361 handle_simple_irq);
1362 } else {
1363 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1364 handle_edge_irq);
1365 }
1366
1367 return 0;
1368 }
1369
1370 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1371 .map = gpmc_irq_map,
1372 .xlate = irq_domain_xlate_twocell,
1373 };
1374
gpmc_handle_irq(int irq,void * data)1375 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1376 {
1377 int hwirq, virq;
1378 u32 regval, regvalx;
1379 struct gpmc_device *gpmc = data;
1380
1381 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1382 regvalx = regval;
1383
1384 if (!regval)
1385 return IRQ_NONE;
1386
1387 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1388 /* skip reserved status bits */
1389 if (hwirq == GPMC_NR_NAND_IRQS)
1390 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1391
1392 if (regvalx & BIT(hwirq)) {
1393 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1394 if (!virq) {
1395 dev_warn(gpmc->dev,
1396 "spurious irq detected hwirq %d, virq %d\n",
1397 hwirq, virq);
1398 }
1399
1400 generic_handle_irq(virq);
1401 }
1402 }
1403
1404 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1405
1406 return IRQ_HANDLED;
1407 }
1408
gpmc_setup_irq(struct gpmc_device * gpmc)1409 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1410 {
1411 u32 regval;
1412 int rc;
1413
1414 /* Disable interrupts */
1415 gpmc_write_reg(GPMC_IRQENABLE, 0);
1416
1417 /* clear interrupts */
1418 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1419 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1420
1421 gpmc->irq_chip.name = "gpmc";
1422 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1423 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1424 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1425 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1426 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1427 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1428
1429 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1430 gpmc->nirqs,
1431 &gpmc_irq_domain_ops,
1432 gpmc);
1433 if (!gpmc_irq_domain) {
1434 dev_err(gpmc->dev, "IRQ domain add failed\n");
1435 return -ENODEV;
1436 }
1437
1438 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1439 if (rc) {
1440 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1441 gpmc->irq, rc);
1442 irq_domain_remove(gpmc_irq_domain);
1443 gpmc_irq_domain = NULL;
1444 }
1445
1446 return rc;
1447 }
1448
gpmc_free_irq(struct gpmc_device * gpmc)1449 static int gpmc_free_irq(struct gpmc_device *gpmc)
1450 {
1451 int hwirq;
1452
1453 free_irq(gpmc->irq, gpmc);
1454
1455 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1456 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1457
1458 irq_domain_remove(gpmc_irq_domain);
1459 gpmc_irq_domain = NULL;
1460
1461 return 0;
1462 }
1463
gpmc_mem_exit(void)1464 static void gpmc_mem_exit(void)
1465 {
1466 int cs;
1467
1468 for (cs = 0; cs < gpmc_cs_num; cs++) {
1469 if (!gpmc_cs_mem_enabled(cs))
1470 continue;
1471 gpmc_cs_delete_mem(cs);
1472 }
1473
1474 }
1475
gpmc_mem_init(void)1476 static void gpmc_mem_init(void)
1477 {
1478 int cs;
1479
1480 gpmc_mem_root.start = GPMC_MEM_START;
1481 gpmc_mem_root.end = GPMC_MEM_END;
1482
1483 /* Reserve all regions that has been set up by bootloader */
1484 for (cs = 0; cs < gpmc_cs_num; cs++) {
1485 u32 base, size;
1486
1487 if (!gpmc_cs_mem_enabled(cs))
1488 continue;
1489 gpmc_cs_get_memconf(cs, &base, &size);
1490 if (gpmc_cs_insert_mem(cs, base, size)) {
1491 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1492 __func__, cs, base, base + size);
1493 gpmc_cs_disable_mem(cs);
1494 }
1495 }
1496 }
1497
gpmc_round_ps_to_sync_clk(u32 time_ps,u32 sync_clk)1498 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1499 {
1500 u32 temp;
1501 int div;
1502
1503 div = gpmc_calc_divider(sync_clk);
1504 temp = gpmc_ps_to_ticks(time_ps);
1505 temp = (temp + div - 1) / div;
1506 return gpmc_ticks_to_ps(temp * div);
1507 }
1508
1509 /* XXX: can the cycles be avoided ? */
gpmc_calc_sync_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1510 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1511 struct gpmc_device_timings *dev_t,
1512 bool mux)
1513 {
1514 u32 temp;
1515
1516 /* adv_rd_off */
1517 temp = dev_t->t_avdp_r;
1518 /* XXX: mux check required ? */
1519 if (mux) {
1520 /* XXX: t_avdp not to be required for sync, only added for tusb
1521 * this indirectly necessitates requirement of t_avdp_r and
1522 * t_avdp_w instead of having a single t_avdp
1523 */
1524 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1525 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1526 }
1527 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1528
1529 /* oe_on */
1530 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1531 if (mux) {
1532 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1533 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1534 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1535 }
1536 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1537
1538 /* access */
1539 /* XXX: any scope for improvement ?, by combining oe_on
1540 * and clk_activation, need to check whether
1541 * access = clk_activation + round to sync clk ?
1542 */
1543 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1544 temp += gpmc_t->clk_activation;
1545 if (dev_t->cyc_oe)
1546 temp = max_t(u32, temp, gpmc_t->oe_on +
1547 gpmc_ticks_to_ps(dev_t->cyc_oe));
1548 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1549
1550 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1551 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1552
1553 /* rd_cycle */
1554 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1555 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1556 gpmc_t->access;
1557 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1558 if (dev_t->t_ce_rdyz)
1559 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1560 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1561
1562 return 0;
1563 }
1564
gpmc_calc_sync_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1565 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1566 struct gpmc_device_timings *dev_t,
1567 bool mux)
1568 {
1569 u32 temp;
1570
1571 /* adv_wr_off */
1572 temp = dev_t->t_avdp_w;
1573 if (mux) {
1574 temp = max_t(u32, temp,
1575 gpmc_t->clk_activation + dev_t->t_avdh);
1576 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1577 }
1578 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1579
1580 /* wr_data_mux_bus */
1581 temp = max_t(u32, dev_t->t_weasu,
1582 gpmc_t->clk_activation + dev_t->t_rdyo);
1583 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1584 * and in that case remember to handle we_on properly
1585 */
1586 if (mux) {
1587 temp = max_t(u32, temp,
1588 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1589 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1590 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1591 }
1592 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1593
1594 /* we_on */
1595 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1596 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1597 else
1598 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1599
1600 /* wr_access */
1601 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1602 gpmc_t->wr_access = gpmc_t->access;
1603
1604 /* we_off */
1605 temp = gpmc_t->we_on + dev_t->t_wpl;
1606 temp = max_t(u32, temp,
1607 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1608 temp = max_t(u32, temp,
1609 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1610 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1611
1612 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1613 dev_t->t_wph);
1614
1615 /* wr_cycle */
1616 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1617 temp += gpmc_t->wr_access;
1618 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1619 if (dev_t->t_ce_rdyz)
1620 temp = max_t(u32, temp,
1621 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1622 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1623
1624 return 0;
1625 }
1626
gpmc_calc_async_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1627 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1628 struct gpmc_device_timings *dev_t,
1629 bool mux)
1630 {
1631 u32 temp;
1632
1633 /* adv_rd_off */
1634 temp = dev_t->t_avdp_r;
1635 if (mux)
1636 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1637 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1638
1639 /* oe_on */
1640 temp = dev_t->t_oeasu;
1641 if (mux)
1642 temp = max_t(u32, temp,
1643 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1644 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1645
1646 /* access */
1647 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1648 gpmc_t->oe_on + dev_t->t_oe);
1649 temp = max_t(u32, temp,
1650 gpmc_t->cs_on + dev_t->t_ce);
1651 temp = max_t(u32, temp,
1652 gpmc_t->adv_on + dev_t->t_aa);
1653 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1654
1655 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1656 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1657
1658 /* rd_cycle */
1659 temp = max_t(u32, dev_t->t_rd_cycle,
1660 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1661 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1662 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1663
1664 return 0;
1665 }
1666
gpmc_calc_async_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1667 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1668 struct gpmc_device_timings *dev_t,
1669 bool mux)
1670 {
1671 u32 temp;
1672
1673 /* adv_wr_off */
1674 temp = dev_t->t_avdp_w;
1675 if (mux)
1676 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1677 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1678
1679 /* wr_data_mux_bus */
1680 temp = dev_t->t_weasu;
1681 if (mux) {
1682 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1683 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1684 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1685 }
1686 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1687
1688 /* we_on */
1689 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1690 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1691 else
1692 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1693
1694 /* we_off */
1695 temp = gpmc_t->we_on + dev_t->t_wpl;
1696 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1697
1698 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1699 dev_t->t_wph);
1700
1701 /* wr_cycle */
1702 temp = max_t(u32, dev_t->t_wr_cycle,
1703 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1704 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1705
1706 return 0;
1707 }
1708
gpmc_calc_sync_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t)1709 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1710 struct gpmc_device_timings *dev_t)
1711 {
1712 u32 temp;
1713
1714 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1715 gpmc_get_fclk_period();
1716
1717 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1718 dev_t->t_bacc,
1719 gpmc_t->sync_clk);
1720
1721 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1722 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1723
1724 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1725 return 0;
1726
1727 if (dev_t->ce_xdelay)
1728 gpmc_t->bool_timings.cs_extra_delay = true;
1729 if (dev_t->avd_xdelay)
1730 gpmc_t->bool_timings.adv_extra_delay = true;
1731 if (dev_t->oe_xdelay)
1732 gpmc_t->bool_timings.oe_extra_delay = true;
1733 if (dev_t->we_xdelay)
1734 gpmc_t->bool_timings.we_extra_delay = true;
1735
1736 return 0;
1737 }
1738
gpmc_calc_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool sync)1739 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1740 struct gpmc_device_timings *dev_t,
1741 bool sync)
1742 {
1743 u32 temp;
1744
1745 /* cs_on */
1746 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1747
1748 /* adv_on */
1749 temp = dev_t->t_avdasu;
1750 if (dev_t->t_ce_avd)
1751 temp = max_t(u32, temp,
1752 gpmc_t->cs_on + dev_t->t_ce_avd);
1753 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1754
1755 if (sync)
1756 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1757
1758 return 0;
1759 }
1760
1761 /* TODO: remove this function once all peripherals are confirmed to
1762 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1763 * has to be modified to handle timings in ps instead of ns
1764 */
gpmc_convert_ps_to_ns(struct gpmc_timings * t)1765 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1766 {
1767 t->cs_on /= 1000;
1768 t->cs_rd_off /= 1000;
1769 t->cs_wr_off /= 1000;
1770 t->adv_on /= 1000;
1771 t->adv_rd_off /= 1000;
1772 t->adv_wr_off /= 1000;
1773 t->we_on /= 1000;
1774 t->we_off /= 1000;
1775 t->oe_on /= 1000;
1776 t->oe_off /= 1000;
1777 t->page_burst_access /= 1000;
1778 t->access /= 1000;
1779 t->rd_cycle /= 1000;
1780 t->wr_cycle /= 1000;
1781 t->bus_turnaround /= 1000;
1782 t->cycle2cycle_delay /= 1000;
1783 t->wait_monitoring /= 1000;
1784 t->clk_activation /= 1000;
1785 t->wr_access /= 1000;
1786 t->wr_data_mux_bus /= 1000;
1787 }
1788
gpmc_calc_timings(struct gpmc_timings * gpmc_t,struct gpmc_settings * gpmc_s,struct gpmc_device_timings * dev_t)1789 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1790 struct gpmc_settings *gpmc_s,
1791 struct gpmc_device_timings *dev_t)
1792 {
1793 bool mux = false, sync = false;
1794
1795 if (gpmc_s) {
1796 mux = gpmc_s->mux_add_data ? true : false;
1797 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1798 }
1799
1800 memset(gpmc_t, 0, sizeof(*gpmc_t));
1801
1802 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1803
1804 if (gpmc_s && gpmc_s->sync_read)
1805 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1806 else
1807 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1808
1809 if (gpmc_s && gpmc_s->sync_write)
1810 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1811 else
1812 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1813
1814 /* TODO: remove, see function definition */
1815 gpmc_convert_ps_to_ns(gpmc_t);
1816
1817 return 0;
1818 }
1819
1820 /**
1821 * gpmc_cs_program_settings - programs non-timing related settings
1822 * @cs: GPMC chip-select to program
1823 * @p: pointer to GPMC settings structure
1824 *
1825 * Programs non-timing related settings for a GPMC chip-select, such as
1826 * bus-width, burst configuration, etc. Function should be called once
1827 * for each chip-select that is being used and must be called before
1828 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1829 * register will be initialised to zero by this function. Returns 0 on
1830 * success and appropriate negative error code on failure.
1831 */
gpmc_cs_program_settings(int cs,struct gpmc_settings * p)1832 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1833 {
1834 u32 config1;
1835
1836 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1837 pr_err("%s: invalid width %d!", __func__, p->device_width);
1838 return -EINVAL;
1839 }
1840
1841 /* Address-data multiplexing not supported for NAND devices */
1842 if (p->device_nand && p->mux_add_data) {
1843 pr_err("%s: invalid configuration!\n", __func__);
1844 return -EINVAL;
1845 }
1846
1847 if ((p->mux_add_data > GPMC_MUX_AD) ||
1848 ((p->mux_add_data == GPMC_MUX_AAD) &&
1849 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1850 pr_err("%s: invalid multiplex configuration!\n", __func__);
1851 return -EINVAL;
1852 }
1853
1854 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1855 if (p->burst_read || p->burst_write) {
1856 switch (p->burst_len) {
1857 case GPMC_BURST_4:
1858 case GPMC_BURST_8:
1859 case GPMC_BURST_16:
1860 break;
1861 default:
1862 pr_err("%s: invalid page/burst-length (%d)\n",
1863 __func__, p->burst_len);
1864 return -EINVAL;
1865 }
1866 }
1867
1868 if (p->wait_pin > gpmc_nr_waitpins) {
1869 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1870 return -EINVAL;
1871 }
1872
1873 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1874
1875 if (p->sync_read)
1876 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1877 if (p->sync_write)
1878 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1879 if (p->wait_on_read)
1880 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1881 if (p->wait_on_write)
1882 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1883 if (p->wait_on_read || p->wait_on_write)
1884 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1885 if (p->device_nand)
1886 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1887 if (p->mux_add_data)
1888 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1889 if (p->burst_read)
1890 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1891 if (p->burst_write)
1892 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1893 if (p->burst_read || p->burst_write) {
1894 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1895 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1896 }
1897
1898 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1899
1900 return 0;
1901 }
1902
1903 #ifdef CONFIG_OF
1904 static const struct of_device_id gpmc_dt_ids[] = {
1905 { .compatible = "ti,omap2420-gpmc" },
1906 { .compatible = "ti,omap2430-gpmc" },
1907 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1908 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1909 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1910 { }
1911 };
1912
1913 /**
1914 * gpmc_read_settings_dt - read gpmc settings from device-tree
1915 * @np: pointer to device-tree node for a gpmc child device
1916 * @p: pointer to gpmc settings structure
1917 *
1918 * Reads the GPMC settings for a GPMC child device from device-tree and
1919 * stores them in the GPMC settings structure passed. The GPMC settings
1920 * structure is initialised to zero by this function and so any
1921 * previously stored settings will be cleared.
1922 */
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)1923 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1924 {
1925 memset(p, 0, sizeof(struct gpmc_settings));
1926
1927 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1928 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1929 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1930 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1931
1932 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1933 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1934 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1935 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1936 if (!p->burst_read && !p->burst_write)
1937 pr_warn("%s: page/burst-length set but not used!\n",
1938 __func__);
1939 }
1940
1941 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1942 p->wait_on_read = of_property_read_bool(np,
1943 "gpmc,wait-on-read");
1944 p->wait_on_write = of_property_read_bool(np,
1945 "gpmc,wait-on-write");
1946 if (!p->wait_on_read && !p->wait_on_write)
1947 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1948 __func__);
1949 }
1950 }
1951
gpmc_read_timings_dt(struct device_node * np,struct gpmc_timings * gpmc_t)1952 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1953 struct gpmc_timings *gpmc_t)
1954 {
1955 struct gpmc_bool_timings *p;
1956
1957 if (!np || !gpmc_t)
1958 return;
1959
1960 memset(gpmc_t, 0, sizeof(*gpmc_t));
1961
1962 /* minimum clock period for syncronous mode */
1963 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1964
1965 /* chip select timtings */
1966 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1967 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1968 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1969
1970 /* ADV signal timings */
1971 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1972 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1973 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1974 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1975 &gpmc_t->adv_aad_mux_on);
1976 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1977 &gpmc_t->adv_aad_mux_rd_off);
1978 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1979 &gpmc_t->adv_aad_mux_wr_off);
1980
1981 /* WE signal timings */
1982 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1983 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1984
1985 /* OE signal timings */
1986 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1987 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1988 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1989 &gpmc_t->oe_aad_mux_on);
1990 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1991 &gpmc_t->oe_aad_mux_off);
1992
1993 /* access and cycle timings */
1994 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1995 &gpmc_t->page_burst_access);
1996 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1997 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1998 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1999 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2000 &gpmc_t->bus_turnaround);
2001 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2002 &gpmc_t->cycle2cycle_delay);
2003 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2004 &gpmc_t->wait_monitoring);
2005 of_property_read_u32(np, "gpmc,clk-activation-ns",
2006 &gpmc_t->clk_activation);
2007
2008 /* only applicable to OMAP3+ */
2009 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2010 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2011 &gpmc_t->wr_data_mux_bus);
2012
2013 /* bool timing parameters */
2014 p = &gpmc_t->bool_timings;
2015
2016 p->cycle2cyclediffcsen =
2017 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2018 p->cycle2cyclesamecsen =
2019 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2020 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2021 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2022 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2023 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2024 p->time_para_granularity =
2025 of_property_read_bool(np, "gpmc,time-para-granularity");
2026 }
2027
2028 /**
2029 * gpmc_probe_generic_child - configures the gpmc for a child device
2030 * @pdev: pointer to gpmc platform device
2031 * @child: pointer to device-tree node for child device
2032 *
2033 * Allocates and configures a GPMC chip-select for a child device.
2034 * Returns 0 on success and appropriate negative error code on failure.
2035 */
gpmc_probe_generic_child(struct platform_device * pdev,struct device_node * child)2036 static int gpmc_probe_generic_child(struct platform_device *pdev,
2037 struct device_node *child)
2038 {
2039 struct gpmc_settings gpmc_s;
2040 struct gpmc_timings gpmc_t;
2041 struct resource res;
2042 unsigned long base;
2043 const char *name;
2044 int ret, cs;
2045 u32 val;
2046 struct gpio_desc *waitpin_desc = NULL;
2047 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2048
2049 if (of_property_read_u32(child, "reg", &cs) < 0) {
2050 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2051 child);
2052 return -ENODEV;
2053 }
2054
2055 if (of_address_to_resource(child, 0, &res) < 0) {
2056 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2057 child);
2058 return -ENODEV;
2059 }
2060
2061 /*
2062 * Check if we have multiple instances of the same device
2063 * on a single chip select. If so, use the already initialized
2064 * timings.
2065 */
2066 name = gpmc_cs_get_name(cs);
2067 if (name && of_node_cmp(child->name, name) == 0)
2068 goto no_timings;
2069
2070 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2071 if (ret < 0) {
2072 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2073 return ret;
2074 }
2075 gpmc_cs_set_name(cs, child->name);
2076
2077 gpmc_read_settings_dt(child, &gpmc_s);
2078 gpmc_read_timings_dt(child, &gpmc_t);
2079
2080 /*
2081 * For some GPMC devices we still need to rely on the bootloader
2082 * timings because the devices can be connected via FPGA.
2083 * REVISIT: Add timing support from slls644g.pdf.
2084 */
2085 if (!gpmc_t.cs_rd_off) {
2086 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2087 cs);
2088 gpmc_cs_show_timings(cs,
2089 "please add GPMC bootloader timings to .dts");
2090 goto no_timings;
2091 }
2092
2093 /* CS must be disabled while making changes to gpmc configuration */
2094 gpmc_cs_disable_mem(cs);
2095
2096 /*
2097 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2098 * location in the gpmc address space. When booting with
2099 * device-tree we want the NOR flash to be mapped to the
2100 * location specified in the device-tree blob. So remap the
2101 * CS to this location. Once DT migration is complete should
2102 * just make gpmc_cs_request() map a specific address.
2103 */
2104 ret = gpmc_cs_remap(cs, res.start);
2105 if (ret < 0) {
2106 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2107 cs, &res.start);
2108 if (res.start < GPMC_MEM_START) {
2109 dev_info(&pdev->dev,
2110 "GPMC CS %d start cannot be lesser than 0x%x\n",
2111 cs, GPMC_MEM_START);
2112 } else if (res.end > GPMC_MEM_END) {
2113 dev_info(&pdev->dev,
2114 "GPMC CS %d end cannot be greater than 0x%x\n",
2115 cs, GPMC_MEM_END);
2116 }
2117 goto err;
2118 }
2119
2120 if (of_node_cmp(child->name, "nand") == 0) {
2121 /* Warn about older DT blobs with no compatible property */
2122 if (!of_property_read_bool(child, "compatible")) {
2123 dev_warn(&pdev->dev,
2124 "Incompatible NAND node: missing compatible");
2125 ret = -EINVAL;
2126 goto err;
2127 }
2128 }
2129
2130 if (of_node_cmp(child->name, "onenand") == 0) {
2131 /* Warn about older DT blobs with no compatible property */
2132 if (!of_property_read_bool(child, "compatible")) {
2133 dev_warn(&pdev->dev,
2134 "Incompatible OneNAND node: missing compatible");
2135 ret = -EINVAL;
2136 goto err;
2137 }
2138 }
2139
2140 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2141 /* NAND specific setup */
2142 val = 8;
2143 of_property_read_u32(child, "nand-bus-width", &val);
2144 switch (val) {
2145 case 8:
2146 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2147 break;
2148 case 16:
2149 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2150 break;
2151 default:
2152 dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2153 child->name);
2154 ret = -EINVAL;
2155 goto err;
2156 }
2157
2158 /* disable write protect */
2159 gpmc_configure(GPMC_CONFIG_WP, 0);
2160 gpmc_s.device_nand = true;
2161 } else {
2162 ret = of_property_read_u32(child, "bank-width",
2163 &gpmc_s.device_width);
2164 if (ret < 0 && !gpmc_s.device_width) {
2165 dev_err(&pdev->dev,
2166 "%pOF has no 'gpmc,device-width' property\n",
2167 child);
2168 goto err;
2169 }
2170 }
2171
2172 /* Reserve wait pin if it is required and valid */
2173 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2174 unsigned int wait_pin = gpmc_s.wait_pin;
2175
2176 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2177 wait_pin, "WAITPIN");
2178 if (IS_ERR(waitpin_desc)) {
2179 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2180 ret = PTR_ERR(waitpin_desc);
2181 goto err;
2182 }
2183 }
2184
2185 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2186
2187 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2188 if (ret < 0)
2189 goto err_cs;
2190
2191 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2192 if (ret) {
2193 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2194 child->name);
2195 goto err_cs;
2196 }
2197
2198 /* Clear limited address i.e. enable A26-A11 */
2199 val = gpmc_read_reg(GPMC_CONFIG);
2200 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2201 gpmc_write_reg(GPMC_CONFIG, val);
2202
2203 /* Enable CS region */
2204 gpmc_cs_enable_mem(cs);
2205
2206 no_timings:
2207
2208 /* create platform device, NULL on error or when disabled */
2209 if (!of_platform_device_create(child, NULL, &pdev->dev))
2210 goto err_child_fail;
2211
2212 /* is child a common bus? */
2213 if (of_match_node(of_default_bus_match_table, child))
2214 /* create children and other common bus children */
2215 if (of_platform_default_populate(child, NULL, &pdev->dev))
2216 goto err_child_fail;
2217
2218 return 0;
2219
2220 err_child_fail:
2221
2222 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2223 ret = -ENODEV;
2224
2225 err_cs:
2226 gpiochip_free_own_desc(waitpin_desc);
2227 err:
2228 gpmc_cs_free(cs);
2229
2230 return ret;
2231 }
2232
gpmc_probe_dt(struct platform_device * pdev)2233 static int gpmc_probe_dt(struct platform_device *pdev)
2234 {
2235 int ret;
2236 const struct of_device_id *of_id =
2237 of_match_device(gpmc_dt_ids, &pdev->dev);
2238
2239 if (!of_id)
2240 return 0;
2241
2242 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2243 &gpmc_cs_num);
2244 if (ret < 0) {
2245 pr_err("%s: number of chip-selects not defined\n", __func__);
2246 return ret;
2247 } else if (gpmc_cs_num < 1) {
2248 pr_err("%s: all chip-selects are disabled\n", __func__);
2249 return -EINVAL;
2250 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2251 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2252 __func__, GPMC_CS_NUM);
2253 return -EINVAL;
2254 }
2255
2256 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2257 &gpmc_nr_waitpins);
2258 if (ret < 0) {
2259 pr_err("%s: number of wait pins not found!\n", __func__);
2260 return ret;
2261 }
2262
2263 return 0;
2264 }
2265
gpmc_probe_dt_children(struct platform_device * pdev)2266 static void gpmc_probe_dt_children(struct platform_device *pdev)
2267 {
2268 int ret;
2269 struct device_node *child;
2270
2271 for_each_available_child_of_node(pdev->dev.of_node, child) {
2272
2273 if (!child->name)
2274 continue;
2275
2276 ret = gpmc_probe_generic_child(pdev, child);
2277 if (ret) {
2278 dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2279 child->name, ret);
2280 }
2281 }
2282 }
2283 #else
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)2284 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2285 {
2286 memset(p, 0, sizeof(*p));
2287 }
gpmc_probe_dt(struct platform_device * pdev)2288 static int gpmc_probe_dt(struct platform_device *pdev)
2289 {
2290 return 0;
2291 }
2292
gpmc_probe_dt_children(struct platform_device * pdev)2293 static void gpmc_probe_dt_children(struct platform_device *pdev)
2294 {
2295 }
2296 #endif /* CONFIG_OF */
2297
gpmc_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)2298 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2299 {
2300 return 1; /* we're input only */
2301 }
2302
gpmc_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)2303 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2304 unsigned int offset)
2305 {
2306 return 0; /* we're input only */
2307 }
2308
gpmc_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)2309 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2310 unsigned int offset, int value)
2311 {
2312 return -EINVAL; /* we're input only */
2313 }
2314
gpmc_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)2315 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2316 int value)
2317 {
2318 }
2319
gpmc_gpio_get(struct gpio_chip * chip,unsigned int offset)2320 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2321 {
2322 u32 reg;
2323
2324 offset += 8;
2325
2326 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2327
2328 return !!reg;
2329 }
2330
gpmc_gpio_init(struct gpmc_device * gpmc)2331 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2332 {
2333 int ret;
2334
2335 gpmc->gpio_chip.parent = gpmc->dev;
2336 gpmc->gpio_chip.owner = THIS_MODULE;
2337 gpmc->gpio_chip.label = DEVICE_NAME;
2338 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2339 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2340 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2341 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2342 gpmc->gpio_chip.set = gpmc_gpio_set;
2343 gpmc->gpio_chip.get = gpmc_gpio_get;
2344 gpmc->gpio_chip.base = -1;
2345
2346 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2347 if (ret < 0) {
2348 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2349 return ret;
2350 }
2351
2352 return 0;
2353 }
2354
gpmc_probe(struct platform_device * pdev)2355 static int gpmc_probe(struct platform_device *pdev)
2356 {
2357 int rc;
2358 u32 l;
2359 struct resource *res;
2360 struct gpmc_device *gpmc;
2361
2362 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2363 if (!gpmc)
2364 return -ENOMEM;
2365
2366 gpmc->dev = &pdev->dev;
2367 platform_set_drvdata(pdev, gpmc);
2368
2369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2370 if (res == NULL)
2371 return -ENOENT;
2372
2373 phys_base = res->start;
2374 mem_size = resource_size(res);
2375
2376 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2377 if (IS_ERR(gpmc_base))
2378 return PTR_ERR(gpmc_base);
2379
2380 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2381 if (!res) {
2382 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2383 return -ENOENT;
2384 }
2385
2386 gpmc->irq = res->start;
2387
2388 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2389 if (IS_ERR(gpmc_l3_clk)) {
2390 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2391 return PTR_ERR(gpmc_l3_clk);
2392 }
2393
2394 if (!clk_get_rate(gpmc_l3_clk)) {
2395 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2396 return -EINVAL;
2397 }
2398
2399 if (pdev->dev.of_node) {
2400 rc = gpmc_probe_dt(pdev);
2401 if (rc)
2402 return rc;
2403 } else {
2404 gpmc_cs_num = GPMC_CS_NUM;
2405 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2406 }
2407
2408 pm_runtime_enable(&pdev->dev);
2409 pm_runtime_get_sync(&pdev->dev);
2410
2411 l = gpmc_read_reg(GPMC_REVISION);
2412
2413 /*
2414 * FIXME: Once device-tree migration is complete the below flags
2415 * should be populated based upon the device-tree compatible
2416 * string. For now just use the IP revision. OMAP3+ devices have
2417 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2418 * devices support the addr-addr-data multiplex protocol.
2419 *
2420 * GPMC IP revisions:
2421 * - OMAP24xx = 2.0
2422 * - OMAP3xxx = 5.0
2423 * - OMAP44xx/54xx/AM335x = 6.0
2424 */
2425 if (GPMC_REVISION_MAJOR(l) > 0x4)
2426 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2427 if (GPMC_REVISION_MAJOR(l) > 0x5)
2428 gpmc_capability |= GPMC_HAS_MUX_AAD;
2429 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2430 GPMC_REVISION_MINOR(l));
2431
2432 gpmc_mem_init();
2433 rc = gpmc_gpio_init(gpmc);
2434 if (rc)
2435 goto gpio_init_failed;
2436
2437 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2438 rc = gpmc_setup_irq(gpmc);
2439 if (rc) {
2440 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2441 goto gpio_init_failed;
2442 }
2443
2444 gpmc_probe_dt_children(pdev);
2445
2446 return 0;
2447
2448 gpio_init_failed:
2449 gpmc_mem_exit();
2450 pm_runtime_put_sync(&pdev->dev);
2451 pm_runtime_disable(&pdev->dev);
2452
2453 return rc;
2454 }
2455
gpmc_remove(struct platform_device * pdev)2456 static int gpmc_remove(struct platform_device *pdev)
2457 {
2458 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2459
2460 gpmc_free_irq(gpmc);
2461 gpmc_mem_exit();
2462 pm_runtime_put_sync(&pdev->dev);
2463 pm_runtime_disable(&pdev->dev);
2464
2465 return 0;
2466 }
2467
2468 #ifdef CONFIG_PM_SLEEP
gpmc_suspend(struct device * dev)2469 static int gpmc_suspend(struct device *dev)
2470 {
2471 omap3_gpmc_save_context();
2472 pm_runtime_put_sync(dev);
2473 return 0;
2474 }
2475
gpmc_resume(struct device * dev)2476 static int gpmc_resume(struct device *dev)
2477 {
2478 pm_runtime_get_sync(dev);
2479 omap3_gpmc_restore_context();
2480 return 0;
2481 }
2482 #endif
2483
2484 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2485
2486 static struct platform_driver gpmc_driver = {
2487 .probe = gpmc_probe,
2488 .remove = gpmc_remove,
2489 .driver = {
2490 .name = DEVICE_NAME,
2491 .of_match_table = of_match_ptr(gpmc_dt_ids),
2492 .pm = &gpmc_pm_ops,
2493 },
2494 };
2495
gpmc_init(void)2496 static __init int gpmc_init(void)
2497 {
2498 return platform_driver_register(&gpmc_driver);
2499 }
2500 postcore_initcall(gpmc_init);
2501
2502 static struct omap3_gpmc_regs gpmc_context;
2503
omap3_gpmc_save_context(void)2504 void omap3_gpmc_save_context(void)
2505 {
2506 int i;
2507
2508 if (!gpmc_base)
2509 return;
2510
2511 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2512 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2513 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2514 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2515 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2516 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2517 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2518 for (i = 0; i < gpmc_cs_num; i++) {
2519 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2520 if (gpmc_context.cs_context[i].is_valid) {
2521 gpmc_context.cs_context[i].config1 =
2522 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2523 gpmc_context.cs_context[i].config2 =
2524 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2525 gpmc_context.cs_context[i].config3 =
2526 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2527 gpmc_context.cs_context[i].config4 =
2528 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2529 gpmc_context.cs_context[i].config5 =
2530 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2531 gpmc_context.cs_context[i].config6 =
2532 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2533 gpmc_context.cs_context[i].config7 =
2534 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2535 }
2536 }
2537 }
2538
omap3_gpmc_restore_context(void)2539 void omap3_gpmc_restore_context(void)
2540 {
2541 int i;
2542
2543 if (!gpmc_base)
2544 return;
2545
2546 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2547 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2548 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2549 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2550 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2551 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2552 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2553 for (i = 0; i < gpmc_cs_num; i++) {
2554 if (gpmc_context.cs_context[i].is_valid) {
2555 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2556 gpmc_context.cs_context[i].config1);
2557 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2558 gpmc_context.cs_context[i].config2);
2559 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2560 gpmc_context.cs_context[i].config3);
2561 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2562 gpmc_context.cs_context[i].config4);
2563 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2564 gpmc_context.cs_context[i].config5);
2565 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2566 gpmc_context.cs_context[i].config6);
2567 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2568 gpmc_context.cs_context[i].config7);
2569 }
2570 }
2571 }
2572