1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
11 *
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Resource sorting
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/cache.h>
22 #include <linux/slab.h>
23 #include "pci.h"
24
pci_std_update_resource(struct pci_dev * dev,int resno)25 static void pci_std_update_resource(struct pci_dev *dev, int resno)
26 {
27 struct pci_bus_region region;
28 bool disable;
29 u16 cmd;
30 u32 new, check, mask;
31 int reg;
32 struct resource *res = dev->resource + resno;
33
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
35 if (dev->is_virtfn)
36 return;
37
38 /*
39 * Ignore resources for unimplemented BARs and unused resource slots
40 * for 64 bit BARs.
41 */
42 if (!res->flags)
43 return;
44
45 if (res->flags & IORESOURCE_UNSET)
46 return;
47
48 /*
49 * Ignore non-moveable resources. This might be legacy resources for
50 * which no functional BAR register exists or another important
51 * system resource we shouldn't move around.
52 */
53 if (res->flags & IORESOURCE_PCI_FIXED)
54 return;
55
56 pcibios_resource_to_bus(dev->bus, ®ion, res);
57 new = region.start;
58
59 if (res->flags & IORESOURCE_IO) {
60 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
61 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
62 } else if (resno == PCI_ROM_RESOURCE) {
63 mask = PCI_ROM_ADDRESS_MASK;
64 } else {
65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
67 }
68
69 if (resno < PCI_ROM_RESOURCE) {
70 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
71 } else if (resno == PCI_ROM_RESOURCE) {
72
73 /*
74 * Apparently some Matrox devices have ROM BARs that read
75 * as zero when disabled, so don't update ROM BARs unless
76 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
77 */
78 if (!(res->flags & IORESOURCE_ROM_ENABLE))
79 return;
80
81 reg = dev->rom_base_reg;
82 new |= PCI_ROM_ADDRESS_ENABLE;
83 } else
84 return;
85
86 /*
87 * We can't update a 64-bit BAR atomically, so when possible,
88 * disable decoding so that a half-updated BAR won't conflict
89 * with another device.
90 */
91 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
92 if (disable) {
93 pci_read_config_word(dev, PCI_COMMAND, &cmd);
94 pci_write_config_word(dev, PCI_COMMAND,
95 cmd & ~PCI_COMMAND_MEMORY);
96 }
97
98 pci_write_config_dword(dev, reg, new);
99 pci_read_config_dword(dev, reg, &check);
100
101 if ((new ^ check) & mask) {
102 pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
103 resno, new, check);
104 }
105
106 if (res->flags & IORESOURCE_MEM_64) {
107 new = region.start >> 16 >> 16;
108 pci_write_config_dword(dev, reg + 4, new);
109 pci_read_config_dword(dev, reg + 4, &check);
110 if (check != new) {
111 pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
112 resno, new, check);
113 }
114 }
115
116 if (disable)
117 pci_write_config_word(dev, PCI_COMMAND, cmd);
118 }
119
pci_update_resource(struct pci_dev * dev,int resno)120 void pci_update_resource(struct pci_dev *dev, int resno)
121 {
122 if (resno <= PCI_ROM_RESOURCE)
123 pci_std_update_resource(dev, resno);
124 #ifdef CONFIG_PCI_IOV
125 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
126 pci_iov_update_resource(dev, resno);
127 #endif
128 }
129
pci_claim_resource(struct pci_dev * dev,int resource)130 int pci_claim_resource(struct pci_dev *dev, int resource)
131 {
132 struct resource *res = &dev->resource[resource];
133 struct resource *root, *conflict;
134
135 if (res->flags & IORESOURCE_UNSET) {
136 pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
137 resource, res);
138 return -EINVAL;
139 }
140
141 /*
142 * If we have a shadow copy in RAM, the PCI device doesn't respond
143 * to the shadow range, so we don't need to claim it, and upstream
144 * bridges don't need to route the range to the device.
145 */
146 if (res->flags & IORESOURCE_ROM_SHADOW)
147 return 0;
148
149 root = pci_find_parent_resource(dev, res);
150 if (!root) {
151 pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
152 resource, res);
153 res->flags |= IORESOURCE_UNSET;
154 return -EINVAL;
155 }
156
157 conflict = request_resource_conflict(root, res);
158 if (conflict) {
159 pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
160 resource, res, conflict->name, conflict);
161 res->flags |= IORESOURCE_UNSET;
162 return -EBUSY;
163 }
164
165 return 0;
166 }
167 EXPORT_SYMBOL(pci_claim_resource);
168
pci_disable_bridge_window(struct pci_dev * dev)169 void pci_disable_bridge_window(struct pci_dev *dev)
170 {
171 /* MMIO Base/Limit */
172 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
173
174 /* Prefetchable MMIO Base/Limit */
175 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
176 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
177 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
178 }
179
180 /*
181 * Generic function that returns a value indicating that the device's
182 * original BIOS BAR address was not saved and so is not available for
183 * reinstatement.
184 *
185 * Can be over-ridden by architecture specific code that implements
186 * reinstatement functionality rather than leaving it disabled when
187 * normal allocation attempts fail.
188 */
pcibios_retrieve_fw_addr(struct pci_dev * dev,int idx)189 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
190 {
191 return 0;
192 }
193
pci_revert_fw_address(struct resource * res,struct pci_dev * dev,int resno,resource_size_t size)194 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
195 int resno, resource_size_t size)
196 {
197 struct resource *root, *conflict;
198 resource_size_t fw_addr, start, end;
199
200 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
201 if (!fw_addr)
202 return -ENOMEM;
203
204 start = res->start;
205 end = res->end;
206 res->start = fw_addr;
207 res->end = res->start + size - 1;
208 res->flags &= ~IORESOURCE_UNSET;
209
210 root = pci_find_parent_resource(dev, res);
211 if (!root) {
212 /*
213 * If dev is behind a bridge, accesses will only reach it
214 * if res is inside the relevant bridge window.
215 */
216 if (pci_upstream_bridge(dev))
217 return -ENXIO;
218
219 /*
220 * On the root bus, assume the host bridge will forward
221 * everything.
222 */
223 if (res->flags & IORESOURCE_IO)
224 root = &ioport_resource;
225 else
226 root = &iomem_resource;
227 }
228
229 pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
230 resno, res);
231 conflict = request_resource_conflict(root, res);
232 if (conflict) {
233 pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
234 resno, res, conflict->name, conflict);
235 res->start = start;
236 res->end = end;
237 res->flags |= IORESOURCE_UNSET;
238 return -EBUSY;
239 }
240 return 0;
241 }
242
243 /*
244 * We don't have to worry about legacy ISA devices, so nothing to do here.
245 * This is marked as __weak because multiple architectures define it; it should
246 * eventually go away.
247 */
pcibios_align_resource(void * data,const struct resource * res,resource_size_t size,resource_size_t align)248 resource_size_t __weak pcibios_align_resource(void *data,
249 const struct resource *res,
250 resource_size_t size,
251 resource_size_t align)
252 {
253 return res->start;
254 }
255
__pci_assign_resource(struct pci_bus * bus,struct pci_dev * dev,int resno,resource_size_t size,resource_size_t align)256 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
257 int resno, resource_size_t size, resource_size_t align)
258 {
259 struct resource *res = dev->resource + resno;
260 resource_size_t min;
261 int ret;
262
263 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
264
265 /*
266 * First, try exact prefetching match. Even if a 64-bit
267 * prefetchable bridge window is below 4GB, we can't put a 32-bit
268 * prefetchable resource in it because pbus_size_mem() assumes a
269 * 64-bit window will contain no 32-bit resources. If we assign
270 * things differently than they were sized, not everything will fit.
271 */
272 ret = pci_bus_alloc_resource(bus, res, size, align, min,
273 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
274 pcibios_align_resource, dev);
275 if (ret == 0)
276 return 0;
277
278 /*
279 * If the prefetchable window is only 32 bits wide, we can put
280 * 64-bit prefetchable resources in it.
281 */
282 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
283 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
284 ret = pci_bus_alloc_resource(bus, res, size, align, min,
285 IORESOURCE_PREFETCH,
286 pcibios_align_resource, dev);
287 if (ret == 0)
288 return 0;
289 }
290
291 /*
292 * If we didn't find a better match, we can put any memory resource
293 * in a non-prefetchable window. If this resource is 32 bits and
294 * non-prefetchable, the first call already tried the only possibility
295 * so we don't need to try again.
296 */
297 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
298 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
299 pcibios_align_resource, dev);
300
301 return ret;
302 }
303
_pci_assign_resource(struct pci_dev * dev,int resno,resource_size_t size,resource_size_t min_align)304 static int _pci_assign_resource(struct pci_dev *dev, int resno,
305 resource_size_t size, resource_size_t min_align)
306 {
307 struct pci_bus *bus;
308 int ret;
309
310 bus = dev->bus;
311 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
312 if (!bus->parent || !bus->self->transparent)
313 break;
314 bus = bus->parent;
315 }
316
317 return ret;
318 }
319
pci_assign_resource(struct pci_dev * dev,int resno)320 int pci_assign_resource(struct pci_dev *dev, int resno)
321 {
322 struct resource *res = dev->resource + resno;
323 resource_size_t align, size;
324 int ret;
325
326 if (res->flags & IORESOURCE_PCI_FIXED)
327 return 0;
328
329 res->flags |= IORESOURCE_UNSET;
330 align = pci_resource_alignment(dev, res);
331 if (!align) {
332 pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
333 resno, res);
334 return -EINVAL;
335 }
336
337 size = resource_size(res);
338 ret = _pci_assign_resource(dev, resno, size, align);
339
340 /*
341 * If we failed to assign anything, let's try the address
342 * where firmware left it. That at least has a chance of
343 * working, which is better than just leaving it disabled.
344 */
345 if (ret < 0) {
346 pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
347 ret = pci_revert_fw_address(res, dev, resno, size);
348 }
349
350 if (ret < 0) {
351 pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
352 return ret;
353 }
354
355 res->flags &= ~IORESOURCE_UNSET;
356 res->flags &= ~IORESOURCE_STARTALIGN;
357 pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
358 if (resno < PCI_BRIDGE_RESOURCES)
359 pci_update_resource(dev, resno);
360
361 return 0;
362 }
363 EXPORT_SYMBOL(pci_assign_resource);
364
pci_reassign_resource(struct pci_dev * dev,int resno,resource_size_t addsize,resource_size_t min_align)365 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
366 resource_size_t min_align)
367 {
368 struct resource *res = dev->resource + resno;
369 unsigned long flags;
370 resource_size_t new_size;
371 int ret;
372
373 if (res->flags & IORESOURCE_PCI_FIXED)
374 return 0;
375
376 flags = res->flags;
377 res->flags |= IORESOURCE_UNSET;
378 if (!res->parent) {
379 pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
380 resno, res);
381 return -EINVAL;
382 }
383
384 /* already aligned with min_align */
385 new_size = resource_size(res) + addsize;
386 ret = _pci_assign_resource(dev, resno, new_size, min_align);
387 if (ret) {
388 res->flags = flags;
389 pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
390 resno, res, (unsigned long long) addsize);
391 return ret;
392 }
393
394 res->flags &= ~IORESOURCE_UNSET;
395 res->flags &= ~IORESOURCE_STARTALIGN;
396 pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
397 resno, res, (unsigned long long) addsize);
398 if (resno < PCI_BRIDGE_RESOURCES)
399 pci_update_resource(dev, resno);
400
401 return 0;
402 }
403
pci_release_resource(struct pci_dev * dev,int resno)404 void pci_release_resource(struct pci_dev *dev, int resno)
405 {
406 struct resource *res = dev->resource + resno;
407
408 pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
409
410 if (!res->parent)
411 return;
412
413 release_resource(res);
414 res->end = resource_size(res) - 1;
415 res->start = 0;
416 res->flags |= IORESOURCE_UNSET;
417 }
418 EXPORT_SYMBOL(pci_release_resource);
419
pci_resize_resource(struct pci_dev * dev,int resno,int size)420 int pci_resize_resource(struct pci_dev *dev, int resno, int size)
421 {
422 struct resource *res = dev->resource + resno;
423 int old, ret;
424 u32 sizes;
425 u16 cmd;
426
427 /* Make sure the resource isn't assigned before resizing it. */
428 if (!(res->flags & IORESOURCE_UNSET))
429 return -EBUSY;
430
431 pci_read_config_word(dev, PCI_COMMAND, &cmd);
432 if (cmd & PCI_COMMAND_MEMORY)
433 return -EBUSY;
434
435 sizes = pci_rebar_get_possible_sizes(dev, resno);
436 if (!sizes)
437 return -ENOTSUPP;
438
439 if (!(sizes & BIT(size)))
440 return -EINVAL;
441
442 old = pci_rebar_get_current_size(dev, resno);
443 if (old < 0)
444 return old;
445
446 ret = pci_rebar_set_size(dev, resno, size);
447 if (ret)
448 return ret;
449
450 res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
451
452 /* Check if the new config works by trying to assign everything. */
453 if (dev->bus->self) {
454 ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
455 if (ret)
456 goto error_resize;
457 }
458 return 0;
459
460 error_resize:
461 pci_rebar_set_size(dev, resno, old);
462 res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
463 return ret;
464 }
465 EXPORT_SYMBOL(pci_resize_resource);
466
pci_enable_resources(struct pci_dev * dev,int mask)467 int pci_enable_resources(struct pci_dev *dev, int mask)
468 {
469 u16 cmd, old_cmd;
470 int i;
471 struct resource *r;
472
473 pci_read_config_word(dev, PCI_COMMAND, &cmd);
474 old_cmd = cmd;
475
476 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
477 if (!(mask & (1 << i)))
478 continue;
479
480 r = &dev->resource[i];
481
482 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
483 continue;
484 if ((i == PCI_ROM_RESOURCE) &&
485 (!(r->flags & IORESOURCE_ROM_ENABLE)))
486 continue;
487
488 if (r->flags & IORESOURCE_UNSET) {
489 pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
490 i, r);
491 return -EINVAL;
492 }
493
494 if (!r->parent) {
495 pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
496 i, r);
497 return -EINVAL;
498 }
499
500 if (r->flags & IORESOURCE_IO)
501 cmd |= PCI_COMMAND_IO;
502 if (r->flags & IORESOURCE_MEM)
503 cmd |= PCI_COMMAND_MEMORY;
504 }
505
506 if (cmd != old_cmd) {
507 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
508 pci_write_config_word(dev, PCI_COMMAND, cmd);
509 }
510 return 0;
511 }
512