1 /*
2 * linux/include/linux/clk-provider.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
13
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_clk.h>
17
18 #ifdef CONFIG_COMMON_CLK
19
20 /*
21 * flags used across common struct clk. these flags should only affect the
22 * top-level framework. custom flags for dealing with hardware specifics
23 * belong in struct clk_foo
24 *
25 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
26 */
27 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
28 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
29 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
30 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
31 /* unused */
32 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
33 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
34 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
35 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
36 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
37 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
38 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
39 /* parents need enable during gate/ungate, set rate and re-parent */
40 #define CLK_OPS_PARENT_ENABLE BIT(12)
41 /* duty cycle call may be forwarded to the parent clock */
42 #define CLK_DUTY_CYCLE_PARENT BIT(13)
43
44 struct clk;
45 struct clk_hw;
46 struct clk_core;
47 struct dentry;
48
49 /**
50 * struct clk_rate_request - Structure encoding the clk constraints that
51 * a clock user might require.
52 *
53 * @rate: Requested clock rate. This field will be adjusted by
54 * clock drivers according to hardware capabilities.
55 * @min_rate: Minimum rate imposed by clk users.
56 * @max_rate: Maximum rate imposed by clk users.
57 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
58 * requested constraints.
59 * @best_parent_hw: The most appropriate parent clock that fulfills the
60 * requested constraints.
61 *
62 */
63 struct clk_rate_request {
64 unsigned long rate;
65 unsigned long min_rate;
66 unsigned long max_rate;
67 unsigned long best_parent_rate;
68 struct clk_hw *best_parent_hw;
69 };
70
71 /**
72 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
73 *
74 * @num: Numerator of the duty cycle ratio
75 * @den: Denominator of the duty cycle ratio
76 */
77 struct clk_duty {
78 unsigned int num;
79 unsigned int den;
80 };
81
82 /**
83 * struct clk_ops - Callback operations for hardware clocks; these are to
84 * be provided by the clock implementation, and will be called by drivers
85 * through the clk_* api.
86 *
87 * @prepare: Prepare the clock for enabling. This must not return until
88 * the clock is fully prepared, and it's safe to call clk_enable.
89 * This callback is intended to allow clock implementations to
90 * do any initialisation that may sleep. Called with
91 * prepare_lock held.
92 *
93 * @unprepare: Release the clock from its prepared state. This will typically
94 * undo any work done in the @prepare callback. Called with
95 * prepare_lock held.
96 *
97 * @is_prepared: Queries the hardware to determine if the clock is prepared.
98 * This function is allowed to sleep. Optional, if this op is not
99 * set then the prepare count will be used.
100 *
101 * @unprepare_unused: Unprepare the clock atomically. Only called from
102 * clk_disable_unused for prepare clocks with special needs.
103 * Called with prepare mutex held. This function may sleep.
104 *
105 * @enable: Enable the clock atomically. This must not return until the
106 * clock is generating a valid clock signal, usable by consumer
107 * devices. Called with enable_lock held. This function must not
108 * sleep.
109 *
110 * @disable: Disable the clock atomically. Called with enable_lock held.
111 * This function must not sleep.
112 *
113 * @is_enabled: Queries the hardware to determine if the clock is enabled.
114 * This function must not sleep. Optional, if this op is not
115 * set then the enable count will be used.
116 *
117 * @disable_unused: Disable the clock atomically. Only called from
118 * clk_disable_unused for gate clocks with special needs.
119 * Called with enable_lock held. This function must not
120 * sleep.
121 *
122 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
123 * parent rate is an input parameter. It is up to the caller to
124 * ensure that the prepare_mutex is held across this call.
125 * Returns the calculated rate. Optional, but recommended - if
126 * this op is not set then clock rate will be initialized to 0.
127 *
128 * @round_rate: Given a target rate as input, returns the closest rate actually
129 * supported by the clock. The parent rate is an input/output
130 * parameter.
131 *
132 * @determine_rate: Given a target rate as input, returns the closest rate
133 * actually supported by the clock, and optionally the parent clock
134 * that should be used to provide the clock rate.
135 *
136 * @set_parent: Change the input source of this clock; for clocks with multiple
137 * possible parents specify a new parent by passing in the index
138 * as a u8 corresponding to the parent in either the .parent_names
139 * or .parents arrays. This function in affect translates an
140 * array index into the value programmed into the hardware.
141 * Returns 0 on success, -EERROR otherwise.
142 *
143 * @get_parent: Queries the hardware to determine the parent of a clock. The
144 * return value is a u8 which specifies the index corresponding to
145 * the parent clock. This index can be applied to either the
146 * .parent_names or .parents arrays. In short, this function
147 * translates the parent value read from hardware into an array
148 * index. Currently only called when the clock is initialized by
149 * __clk_init. This callback is mandatory for clocks with
150 * multiple parents. It is optional (and unnecessary) for clocks
151 * with 0 or 1 parents.
152 *
153 * @set_rate: Change the rate of this clock. The requested rate is specified
154 * by the second argument, which should typically be the return
155 * of .round_rate call. The third argument gives the parent rate
156 * which is likely helpful for most .set_rate implementation.
157 * Returns 0 on success, -EERROR otherwise.
158 *
159 * @set_rate_and_parent: Change the rate and the parent of this clock. The
160 * requested rate is specified by the second argument, which
161 * should typically be the return of .round_rate call. The
162 * third argument gives the parent rate which is likely helpful
163 * for most .set_rate_and_parent implementation. The fourth
164 * argument gives the parent index. This callback is optional (and
165 * unnecessary) for clocks with 0 or 1 parents as well as
166 * for clocks that can tolerate switching the rate and the parent
167 * separately via calls to .set_parent and .set_rate.
168 * Returns 0 on success, -EERROR otherwise.
169 *
170 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
171 * is expressed in ppb (parts per billion). The parent accuracy is
172 * an input parameter.
173 * Returns the calculated accuracy. Optional - if this op is not
174 * set then clock accuracy will be initialized to parent accuracy
175 * or 0 (perfect clock) if clock has no parent.
176 *
177 * @get_phase: Queries the hardware to get the current phase of a clock.
178 * Returned values are 0-359 degrees on success, negative
179 * error codes on failure.
180 *
181 * @set_phase: Shift the phase this clock signal in degrees specified
182 * by the second argument. Valid values for degrees are
183 * 0-359. Return 0 on success, otherwise -EERROR.
184 *
185 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
186 * of a clock. Returned values denominator cannot be 0 and must be
187 * superior or equal to the numerator.
188 *
189 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
190 * the numerator (2nd argurment) and denominator (3rd argument).
191 * Argument must be a valid ratio (denominator > 0
192 * and >= numerator) Return 0 on success, otherwise -EERROR.
193 *
194 * @init: Perform platform-specific initialization magic.
195 * This is not not used by any of the basic clock types.
196 * Please consider other ways of solving initialization problems
197 * before using this callback, as its use is discouraged.
198 *
199 * @debug_init: Set up type-specific debugfs entries for this clock. This
200 * is called once, after the debugfs directory entry for this
201 * clock has been created. The dentry pointer representing that
202 * directory is provided as an argument. Called with
203 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
204 *
205 *
206 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
207 * implementations to split any work between atomic (enable) and sleepable
208 * (prepare) contexts. If enabling a clock requires code that might sleep,
209 * this must be done in clk_prepare. Clock enable code that will never be
210 * called in a sleepable context may be implemented in clk_enable.
211 *
212 * Typically, drivers will call clk_prepare when a clock may be needed later
213 * (eg. when a device is opened), and clk_enable when the clock is actually
214 * required (eg. from an interrupt). Note that clk_prepare MUST have been
215 * called before clk_enable.
216 */
217 struct clk_ops {
218 int (*prepare)(struct clk_hw *hw);
219 void (*unprepare)(struct clk_hw *hw);
220 int (*is_prepared)(struct clk_hw *hw);
221 void (*unprepare_unused)(struct clk_hw *hw);
222 int (*enable)(struct clk_hw *hw);
223 void (*disable)(struct clk_hw *hw);
224 int (*is_enabled)(struct clk_hw *hw);
225 void (*disable_unused)(struct clk_hw *hw);
226 unsigned long (*recalc_rate)(struct clk_hw *hw,
227 unsigned long parent_rate);
228 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
229 unsigned long *parent_rate);
230 int (*determine_rate)(struct clk_hw *hw,
231 struct clk_rate_request *req);
232 int (*set_parent)(struct clk_hw *hw, u8 index);
233 u8 (*get_parent)(struct clk_hw *hw);
234 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
235 unsigned long parent_rate);
236 int (*set_rate_and_parent)(struct clk_hw *hw,
237 unsigned long rate,
238 unsigned long parent_rate, u8 index);
239 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
240 unsigned long parent_accuracy);
241 int (*get_phase)(struct clk_hw *hw);
242 int (*set_phase)(struct clk_hw *hw, int degrees);
243 int (*get_duty_cycle)(struct clk_hw *hw,
244 struct clk_duty *duty);
245 int (*set_duty_cycle)(struct clk_hw *hw,
246 struct clk_duty *duty);
247 void (*init)(struct clk_hw *hw);
248 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
249 };
250
251 /**
252 * struct clk_init_data - holds init data that's common to all clocks and is
253 * shared between the clock provider and the common clock framework.
254 *
255 * @name: clock name
256 * @ops: operations this clock supports
257 * @parent_names: array of string names for all possible parents
258 * @num_parents: number of possible parents
259 * @flags: framework-level hints and quirks
260 */
261 struct clk_init_data {
262 const char *name;
263 const struct clk_ops *ops;
264 const char * const *parent_names;
265 u8 num_parents;
266 unsigned long flags;
267 };
268
269 /**
270 * struct clk_hw - handle for traversing from a struct clk to its corresponding
271 * hardware-specific structure. struct clk_hw should be declared within struct
272 * clk_foo and then referenced by the struct clk instance that uses struct
273 * clk_foo's clk_ops
274 *
275 * @core: pointer to the struct clk_core instance that points back to this
276 * struct clk_hw instance
277 *
278 * @clk: pointer to the per-user struct clk instance that can be used to call
279 * into the clk API
280 *
281 * @init: pointer to struct clk_init_data that contains the init data shared
282 * with the common clock framework.
283 */
284 struct clk_hw {
285 struct clk_core *core;
286 struct clk *clk;
287 const struct clk_init_data *init;
288 };
289
290 /*
291 * DOC: Basic clock implementations common to many platforms
292 *
293 * Each basic clock hardware type is comprised of a structure describing the
294 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
295 * unique flags for that hardware type, a registration function and an
296 * alternative macro for static initialization
297 */
298
299 /**
300 * struct clk_fixed_rate - fixed-rate clock
301 * @hw: handle between common and hardware-specific interfaces
302 * @fixed_rate: constant frequency of clock
303 */
304 struct clk_fixed_rate {
305 struct clk_hw hw;
306 unsigned long fixed_rate;
307 unsigned long fixed_accuracy;
308 u8 flags;
309 };
310
311 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
312
313 extern const struct clk_ops clk_fixed_rate_ops;
314 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
315 const char *parent_name, unsigned long flags,
316 unsigned long fixed_rate);
317 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
318 const char *parent_name, unsigned long flags,
319 unsigned long fixed_rate);
320 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
321 const char *name, const char *parent_name, unsigned long flags,
322 unsigned long fixed_rate, unsigned long fixed_accuracy);
323 void clk_unregister_fixed_rate(struct clk *clk);
324 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
325 const char *name, const char *parent_name, unsigned long flags,
326 unsigned long fixed_rate, unsigned long fixed_accuracy);
327 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
328
329 void of_fixed_clk_setup(struct device_node *np);
330
331 /**
332 * struct clk_gate - gating clock
333 *
334 * @hw: handle between common and hardware-specific interfaces
335 * @reg: register controlling gate
336 * @bit_idx: single bit controlling gate
337 * @flags: hardware-specific flags
338 * @lock: register lock
339 *
340 * Clock which can gate its output. Implements .enable & .disable
341 *
342 * Flags:
343 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
344 * enable the clock. Setting this flag does the opposite: setting the bit
345 * disable the clock and clearing it enables the clock
346 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
347 * of this register, and mask of gate bits are in higher 16-bit of this
348 * register. While setting the gate bits, higher 16-bit should also be
349 * updated to indicate changing gate bits.
350 */
351 struct clk_gate {
352 struct clk_hw hw;
353 void __iomem *reg;
354 u8 bit_idx;
355 u8 flags;
356 spinlock_t *lock;
357 };
358
359 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
360
361 #define CLK_GATE_SET_TO_DISABLE BIT(0)
362 #define CLK_GATE_HIWORD_MASK BIT(1)
363
364 extern const struct clk_ops clk_gate_ops;
365 struct clk *clk_register_gate(struct device *dev, const char *name,
366 const char *parent_name, unsigned long flags,
367 void __iomem *reg, u8 bit_idx,
368 u8 clk_gate_flags, spinlock_t *lock);
369 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
370 const char *parent_name, unsigned long flags,
371 void __iomem *reg, u8 bit_idx,
372 u8 clk_gate_flags, spinlock_t *lock);
373 void clk_unregister_gate(struct clk *clk);
374 void clk_hw_unregister_gate(struct clk_hw *hw);
375 int clk_gate_is_enabled(struct clk_hw *hw);
376
377 struct clk_div_table {
378 unsigned int val;
379 unsigned int div;
380 };
381
382 /**
383 * struct clk_divider - adjustable divider clock
384 *
385 * @hw: handle between common and hardware-specific interfaces
386 * @reg: register containing the divider
387 * @shift: shift to the divider bit field
388 * @width: width of the divider bit field
389 * @table: array of value/divider pairs, last entry should have div = 0
390 * @lock: register lock
391 *
392 * Clock with an adjustable divider affecting its output frequency. Implements
393 * .recalc_rate, .set_rate and .round_rate
394 *
395 * Flags:
396 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
397 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
398 * the raw value read from the register, with the value of zero considered
399 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
400 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
401 * the hardware register
402 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
403 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
404 * Some hardware implementations gracefully handle this case and allow a
405 * zero divisor by not modifying their input clock
406 * (divide by one / bypass).
407 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
408 * of this register, and mask of divider bits are in higher 16-bit of this
409 * register. While setting the divider bits, higher 16-bit should also be
410 * updated to indicate changing divider bits.
411 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
412 * to the closest integer instead of the up one.
413 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
414 * not be changed by the clock framework.
415 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
416 * except when the value read from the register is zero, the divisor is
417 * 2^width of the field.
418 */
419 struct clk_divider {
420 struct clk_hw hw;
421 void __iomem *reg;
422 u8 shift;
423 u8 width;
424 u8 flags;
425 const struct clk_div_table *table;
426 spinlock_t *lock;
427 };
428
429 #define clk_div_mask(width) ((1 << (width)) - 1)
430 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
431
432 #define CLK_DIVIDER_ONE_BASED BIT(0)
433 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
434 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
435 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
436 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
437 #define CLK_DIVIDER_READ_ONLY BIT(5)
438 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
439
440 extern const struct clk_ops clk_divider_ops;
441 extern const struct clk_ops clk_divider_ro_ops;
442
443 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
444 unsigned int val, const struct clk_div_table *table,
445 unsigned long flags, unsigned long width);
446 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
447 unsigned long rate, unsigned long *prate,
448 const struct clk_div_table *table,
449 u8 width, unsigned long flags);
450 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
451 unsigned long rate, unsigned long *prate,
452 const struct clk_div_table *table, u8 width,
453 unsigned long flags, unsigned int val);
454 int divider_get_val(unsigned long rate, unsigned long parent_rate,
455 const struct clk_div_table *table, u8 width,
456 unsigned long flags);
457
458 struct clk *clk_register_divider(struct device *dev, const char *name,
459 const char *parent_name, unsigned long flags,
460 void __iomem *reg, u8 shift, u8 width,
461 u8 clk_divider_flags, spinlock_t *lock);
462 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
463 const char *parent_name, unsigned long flags,
464 void __iomem *reg, u8 shift, u8 width,
465 u8 clk_divider_flags, spinlock_t *lock);
466 struct clk *clk_register_divider_table(struct device *dev, const char *name,
467 const char *parent_name, unsigned long flags,
468 void __iomem *reg, u8 shift, u8 width,
469 u8 clk_divider_flags, const struct clk_div_table *table,
470 spinlock_t *lock);
471 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
472 const char *name, const char *parent_name, unsigned long flags,
473 void __iomem *reg, u8 shift, u8 width,
474 u8 clk_divider_flags, const struct clk_div_table *table,
475 spinlock_t *lock);
476 void clk_unregister_divider(struct clk *clk);
477 void clk_hw_unregister_divider(struct clk_hw *hw);
478
479 /**
480 * struct clk_mux - multiplexer clock
481 *
482 * @hw: handle between common and hardware-specific interfaces
483 * @reg: register controlling multiplexer
484 * @table: array of register values corresponding to the parent index
485 * @shift: shift to multiplexer bit field
486 * @mask: mask of mutliplexer bit field
487 * @flags: hardware-specific flags
488 * @lock: register lock
489 *
490 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
491 * and .recalc_rate
492 *
493 * Flags:
494 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
495 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
496 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
497 * register, and mask of mux bits are in higher 16-bit of this register.
498 * While setting the mux bits, higher 16-bit should also be updated to
499 * indicate changing mux bits.
500 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
501 * frequency.
502 */
503 struct clk_mux {
504 struct clk_hw hw;
505 void __iomem *reg;
506 u32 *table;
507 u32 mask;
508 u8 shift;
509 u8 flags;
510 spinlock_t *lock;
511 };
512
513 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
514
515 #define CLK_MUX_INDEX_ONE BIT(0)
516 #define CLK_MUX_INDEX_BIT BIT(1)
517 #define CLK_MUX_HIWORD_MASK BIT(2)
518 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
519 #define CLK_MUX_ROUND_CLOSEST BIT(4)
520
521 extern const struct clk_ops clk_mux_ops;
522 extern const struct clk_ops clk_mux_ro_ops;
523
524 struct clk *clk_register_mux(struct device *dev, const char *name,
525 const char * const *parent_names, u8 num_parents,
526 unsigned long flags,
527 void __iomem *reg, u8 shift, u8 width,
528 u8 clk_mux_flags, spinlock_t *lock);
529 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
530 const char * const *parent_names, u8 num_parents,
531 unsigned long flags,
532 void __iomem *reg, u8 shift, u8 width,
533 u8 clk_mux_flags, spinlock_t *lock);
534
535 struct clk *clk_register_mux_table(struct device *dev, const char *name,
536 const char * const *parent_names, u8 num_parents,
537 unsigned long flags,
538 void __iomem *reg, u8 shift, u32 mask,
539 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
540 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
541 const char * const *parent_names, u8 num_parents,
542 unsigned long flags,
543 void __iomem *reg, u8 shift, u32 mask,
544 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
545
546 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
547 unsigned int val);
548 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
549
550 void clk_unregister_mux(struct clk *clk);
551 void clk_hw_unregister_mux(struct clk_hw *hw);
552
553 void of_fixed_factor_clk_setup(struct device_node *node);
554
555 /**
556 * struct clk_fixed_factor - fixed multiplier and divider clock
557 *
558 * @hw: handle between common and hardware-specific interfaces
559 * @mult: multiplier
560 * @div: divider
561 *
562 * Clock with a fixed multiplier and divider. The output frequency is the
563 * parent clock rate divided by div and multiplied by mult.
564 * Implements .recalc_rate, .set_rate and .round_rate
565 */
566
567 struct clk_fixed_factor {
568 struct clk_hw hw;
569 unsigned int mult;
570 unsigned int div;
571 };
572
573 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
574
575 extern const struct clk_ops clk_fixed_factor_ops;
576 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
577 const char *parent_name, unsigned long flags,
578 unsigned int mult, unsigned int div);
579 void clk_unregister_fixed_factor(struct clk *clk);
580 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
581 const char *name, const char *parent_name, unsigned long flags,
582 unsigned int mult, unsigned int div);
583 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
584
585 /**
586 * struct clk_fractional_divider - adjustable fractional divider clock
587 *
588 * @hw: handle between common and hardware-specific interfaces
589 * @reg: register containing the divider
590 * @mshift: shift to the numerator bit field
591 * @mwidth: width of the numerator bit field
592 * @nshift: shift to the denominator bit field
593 * @nwidth: width of the denominator bit field
594 * @lock: register lock
595 *
596 * Clock with adjustable fractional divider affecting its output frequency.
597 */
598 struct clk_fractional_divider {
599 struct clk_hw hw;
600 void __iomem *reg;
601 u8 mshift;
602 u8 mwidth;
603 u32 mmask;
604 u8 nshift;
605 u8 nwidth;
606 u32 nmask;
607 u8 flags;
608 void (*approximation)(struct clk_hw *hw,
609 unsigned long rate, unsigned long *parent_rate,
610 unsigned long *m, unsigned long *n);
611 spinlock_t *lock;
612 };
613
614 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
615
616 extern const struct clk_ops clk_fractional_divider_ops;
617 struct clk *clk_register_fractional_divider(struct device *dev,
618 const char *name, const char *parent_name, unsigned long flags,
619 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
620 u8 clk_divider_flags, spinlock_t *lock);
621 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
622 const char *name, const char *parent_name, unsigned long flags,
623 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
624 u8 clk_divider_flags, spinlock_t *lock);
625 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
626
627 /**
628 * struct clk_multiplier - adjustable multiplier clock
629 *
630 * @hw: handle between common and hardware-specific interfaces
631 * @reg: register containing the multiplier
632 * @shift: shift to the multiplier bit field
633 * @width: width of the multiplier bit field
634 * @lock: register lock
635 *
636 * Clock with an adjustable multiplier affecting its output frequency.
637 * Implements .recalc_rate, .set_rate and .round_rate
638 *
639 * Flags:
640 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
641 * from the register, with 0 being a valid value effectively
642 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
643 * set, then a null multiplier will be considered as a bypass,
644 * leaving the parent rate unmodified.
645 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
646 * rounded to the closest integer instead of the down one.
647 */
648 struct clk_multiplier {
649 struct clk_hw hw;
650 void __iomem *reg;
651 u8 shift;
652 u8 width;
653 u8 flags;
654 spinlock_t *lock;
655 };
656
657 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
658
659 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
660 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
661
662 extern const struct clk_ops clk_multiplier_ops;
663
664 /***
665 * struct clk_composite - aggregate clock of mux, divider and gate clocks
666 *
667 * @hw: handle between common and hardware-specific interfaces
668 * @mux_hw: handle between composite and hardware-specific mux clock
669 * @rate_hw: handle between composite and hardware-specific rate clock
670 * @gate_hw: handle between composite and hardware-specific gate clock
671 * @mux_ops: clock ops for mux
672 * @rate_ops: clock ops for rate
673 * @gate_ops: clock ops for gate
674 */
675 struct clk_composite {
676 struct clk_hw hw;
677 struct clk_ops ops;
678
679 struct clk_hw *mux_hw;
680 struct clk_hw *rate_hw;
681 struct clk_hw *gate_hw;
682
683 const struct clk_ops *mux_ops;
684 const struct clk_ops *rate_ops;
685 const struct clk_ops *gate_ops;
686 };
687
688 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
689
690 struct clk *clk_register_composite(struct device *dev, const char *name,
691 const char * const *parent_names, int num_parents,
692 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
693 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
694 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
695 unsigned long flags);
696 void clk_unregister_composite(struct clk *clk);
697 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
698 const char * const *parent_names, int num_parents,
699 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
700 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
701 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
702 unsigned long flags);
703 void clk_hw_unregister_composite(struct clk_hw *hw);
704
705 /***
706 * struct clk_gpio_gate - gpio gated clock
707 *
708 * @hw: handle between common and hardware-specific interfaces
709 * @gpiod: gpio descriptor
710 *
711 * Clock with a gpio control for enabling and disabling the parent clock.
712 * Implements .enable, .disable and .is_enabled
713 */
714
715 struct clk_gpio {
716 struct clk_hw hw;
717 struct gpio_desc *gpiod;
718 };
719
720 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
721
722 extern const struct clk_ops clk_gpio_gate_ops;
723 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
724 const char *parent_name, struct gpio_desc *gpiod,
725 unsigned long flags);
726 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
727 const char *parent_name, struct gpio_desc *gpiod,
728 unsigned long flags);
729 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
730
731 /**
732 * struct clk_gpio_mux - gpio controlled clock multiplexer
733 *
734 * @hw: see struct clk_gpio
735 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
736 *
737 * Clock with a gpio control for selecting the parent clock.
738 * Implements .get_parent, .set_parent and .determine_rate
739 */
740
741 extern const struct clk_ops clk_gpio_mux_ops;
742 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
743 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
744 unsigned long flags);
745 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
746 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
747 unsigned long flags);
748 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
749
750 /**
751 * clk_register - allocate a new clock, register it and return an opaque cookie
752 * @dev: device that is registering this clock
753 * @hw: link to hardware-specific clock data
754 *
755 * clk_register is the primary interface for populating the clock tree with new
756 * clock nodes. It returns a pointer to the newly allocated struct clk which
757 * cannot be dereferenced by driver code but may be used in conjuction with the
758 * rest of the clock API. In the event of an error clk_register will return an
759 * error code; drivers must test for an error code after calling clk_register.
760 */
761 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
762 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
763
764 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
765 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
766
767 void clk_unregister(struct clk *clk);
768 void devm_clk_unregister(struct device *dev, struct clk *clk);
769
770 void clk_hw_unregister(struct clk_hw *hw);
771 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
772
773 /* helper functions */
774 const char *__clk_get_name(const struct clk *clk);
775 const char *clk_hw_get_name(const struct clk_hw *hw);
776 struct clk_hw *__clk_get_hw(struct clk *clk);
777 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
778 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
779 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
780 unsigned int index);
781 unsigned int __clk_get_enable_count(struct clk *clk);
782 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
783 unsigned long __clk_get_flags(struct clk *clk);
784 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
785 #define clk_hw_can_set_rate_parent(hw) \
786 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
787
788 bool clk_hw_is_prepared(const struct clk_hw *hw);
789 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
790 bool clk_hw_is_enabled(const struct clk_hw *hw);
791 bool __clk_is_enabled(struct clk *clk);
792 struct clk *__clk_lookup(const char *name);
793 int __clk_mux_determine_rate(struct clk_hw *hw,
794 struct clk_rate_request *req);
795 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
796 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
797 struct clk_rate_request *req);
798 int clk_mux_determine_rate_flags(struct clk_hw *hw,
799 struct clk_rate_request *req,
800 unsigned long flags);
801 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
802 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
803 unsigned long max_rate);
804
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)805 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
806 {
807 dst->clk = src->clk;
808 dst->core = src->core;
809 }
810
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)811 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
812 unsigned long *prate,
813 const struct clk_div_table *table,
814 u8 width, unsigned long flags)
815 {
816 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
817 rate, prate, table, width, flags);
818 }
819
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)820 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
821 unsigned long *prate,
822 const struct clk_div_table *table,
823 u8 width, unsigned long flags,
824 unsigned int val)
825 {
826 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
827 rate, prate, table, width, flags,
828 val);
829 }
830
831 /*
832 * FIXME clock api without lock protection
833 */
834 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
835
836 struct of_device_id;
837
838 struct clk_onecell_data {
839 struct clk **clks;
840 unsigned int clk_num;
841 };
842
843 struct clk_hw_onecell_data {
844 unsigned int num;
845 struct clk_hw *hws[];
846 };
847
848 extern struct of_device_id __clk_of_table;
849
850 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
851
852 /*
853 * Use this macro when you have a driver that requires two initialization
854 * routines, one at of_clk_init(), and one at platform device probe
855 */
856 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
857 static void __init name##_of_clk_init_driver(struct device_node *np) \
858 { \
859 of_node_clear_flag(np, OF_POPULATED); \
860 fn(np); \
861 } \
862 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
863
864 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
865 (&(struct clk_init_data) { \
866 .flags = _flags, \
867 .name = _name, \
868 .parent_names = (const char *[]) { _parent }, \
869 .num_parents = 1, \
870 .ops = _ops, \
871 })
872
873 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
874 (&(struct clk_init_data) { \
875 .flags = _flags, \
876 .name = _name, \
877 .parent_names = _parents, \
878 .num_parents = ARRAY_SIZE(_parents), \
879 .ops = _ops, \
880 })
881
882 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
883 (&(struct clk_init_data) { \
884 .flags = _flags, \
885 .name = _name, \
886 .parent_names = NULL, \
887 .num_parents = 0, \
888 .ops = _ops, \
889 })
890
891 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
892 _div, _mult, _flags) \
893 struct clk_fixed_factor _struct = { \
894 .div = _div, \
895 .mult = _mult, \
896 .hw.init = CLK_HW_INIT(_name, \
897 _parent, \
898 &clk_fixed_factor_ops, \
899 _flags), \
900 }
901
902 #ifdef CONFIG_OF
903 int of_clk_add_provider(struct device_node *np,
904 struct clk *(*clk_src_get)(struct of_phandle_args *args,
905 void *data),
906 void *data);
907 int of_clk_add_hw_provider(struct device_node *np,
908 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
909 void *data),
910 void *data);
911 int devm_of_clk_add_hw_provider(struct device *dev,
912 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
913 void *data),
914 void *data);
915 void of_clk_del_provider(struct device_node *np);
916 void devm_of_clk_del_provider(struct device *dev);
917 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
918 void *data);
919 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
920 void *data);
921 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
922 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
923 void *data);
924 int of_clk_parent_fill(struct device_node *np, const char **parents,
925 unsigned int size);
926 int of_clk_detect_critical(struct device_node *np, int index,
927 unsigned long *flags);
928
929 #else /* !CONFIG_OF */
930
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)931 static inline int of_clk_add_provider(struct device_node *np,
932 struct clk *(*clk_src_get)(struct of_phandle_args *args,
933 void *data),
934 void *data)
935 {
936 return 0;
937 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)938 static inline int of_clk_add_hw_provider(struct device_node *np,
939 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
940 void *data),
941 void *data)
942 {
943 return 0;
944 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)945 static inline int devm_of_clk_add_hw_provider(struct device *dev,
946 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
947 void *data),
948 void *data)
949 {
950 return 0;
951 }
of_clk_del_provider(struct device_node * np)952 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)953 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)954 static inline struct clk *of_clk_src_simple_get(
955 struct of_phandle_args *clkspec, void *data)
956 {
957 return ERR_PTR(-ENOENT);
958 }
959 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)960 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
961 {
962 return ERR_PTR(-ENOENT);
963 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)964 static inline struct clk *of_clk_src_onecell_get(
965 struct of_phandle_args *clkspec, void *data)
966 {
967 return ERR_PTR(-ENOENT);
968 }
969 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)970 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
971 {
972 return ERR_PTR(-ENOENT);
973 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)974 static inline int of_clk_parent_fill(struct device_node *np,
975 const char **parents, unsigned int size)
976 {
977 return 0;
978 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)979 static inline int of_clk_detect_critical(struct device_node *np, int index,
980 unsigned long *flags)
981 {
982 return 0;
983 }
984 #endif /* CONFIG_OF */
985
986 /*
987 * wrap access to peripherals in accessor routines
988 * for improved portability across platforms
989 */
990
991 #if IS_ENABLED(CONFIG_PPC)
992
clk_readl(u32 __iomem * reg)993 static inline u32 clk_readl(u32 __iomem *reg)
994 {
995 return ioread32be(reg);
996 }
997
clk_writel(u32 val,u32 __iomem * reg)998 static inline void clk_writel(u32 val, u32 __iomem *reg)
999 {
1000 iowrite32be(val, reg);
1001 }
1002
1003 #else /* platform dependent I/O accessors */
1004
clk_readl(u32 __iomem * reg)1005 static inline u32 clk_readl(u32 __iomem *reg)
1006 {
1007 return readl(reg);
1008 }
1009
clk_writel(u32 val,u32 __iomem * reg)1010 static inline void clk_writel(u32 val, u32 __iomem *reg)
1011 {
1012 writel(val, reg);
1013 }
1014
1015 #endif /* platform dependent I/O accessors */
1016
1017 #endif /* CONFIG_COMMON_CLK */
1018 #endif /* CLK_PROVIDER_H */
1019