xref: /wlan-driver/qca-wifi-host-cmn/dp/wifi3.0/rh/dp_rh_tx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 #ifndef __DP_RH_TX_H
19 #define __DP_RH_TX_H
20 
21 #include <dp_types.h>
22 
23 #define DP_RH_TX_HDR_SIZE_NATIVE_WIFI	30
24 #define DP_RH_TX_HDR_SIZE_802_11_RAW	36
25 #define DP_RH_TX_HDR_SIZE_ETHERNET	14
26 #define DP_RH_TX_HDR_SIZE_IP		16
27 #define DP_RH_TX_HDR_SIZE_802_1Q	4
28 #define DP_RH_TX_HDR_SIZE_LLC_SNAP	8
29 
30 #define DP_RH_TX_HDR_SIZE_OUTER_HDR_MAX DP_RH_TX_HDR_SIZE_802_11_RAW
31 
32 #define DP_RH_TX_TLV_HDR_SIZE	sizeof(struct tlv_32_hdr)
33 #define DP_RH_TX_TCL_DESC_SIZE	(HAL_TX_DESC_LEN_BYTES + DP_RH_TX_TLV_HDR_SIZE)
34 
35 /*
36  * NB: intentionally not using kernel-doc comment because the kernel-doc
37  *     script does not handle the qdf_dma_mem_context macro
38  * struct dp_tx_tcl_desc_pool_s - Tx Extension Descriptor Pool
39  * @elem_count: Number of descriptors in the pool
40  * @elem_size: Size of each descriptor
41  * @desc_pages: multiple page allocation information for actual descriptors
42  * @freelist: freelist of TCL descriptors
43  * @memctx:
44  */
45 struct dp_tx_tcl_desc_pool_s {
46 	uint16_t elem_count;
47 	int elem_size;
48 	struct qdf_mem_multi_page_t desc_pages;
49 	uint32_t *freelist;
50 	qdf_dma_mem_context(memctx);
51 };
52 
53 /**
54  * dp_tx_hw_enqueue_rh() - Enqueue to TCL HW for transmit
55  * @soc: DP Soc Handle
56  * @vdev: DP vdev handle
57  * @tx_desc: Tx Descriptor Handle
58  * @fw_metadata: Metadata to send to Target Firmware along with frame
59  * @tx_exc_metadata: Handle that holds exception path meta data
60  * @msdu_info: Holds the MSDU information to be transmitted
61  *
62  *  Gets the next free TCL HW DMA descriptor and sets up required parameters
63  *  from software Tx descriptor
64  *
65  * Return: QDF_STATUS_SUCCESS: success
66  *         QDF_STATUS_E_RESOURCES: Error return
67  */
68 QDF_STATUS
69 dp_tx_hw_enqueue_rh(struct dp_soc *soc, struct dp_vdev *vdev,
70 		    struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
71 		    struct cdp_tx_exception_metadata *tx_exc_metadata,
72 		    struct dp_tx_msdu_info_s *msdu_info);
73 /**
74  * dp_tx_comp_get_params_from_hal_desc_rh() - Get TX desc from HAL comp desc
75  * @soc: DP soc handle
76  * @tx_comp_hal_desc: HAL TX Comp Descriptor
77  * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc.
78  *
79  * Return: QDF_STATUS return codes
80  */
81 QDF_STATUS
82 dp_tx_comp_get_params_from_hal_desc_rh(struct dp_soc *soc,
83 				       void *tx_comp_hal_desc,
84 				       struct dp_tx_desc_s **r_tx_desc);
85 
86 /**
87  * dp_tx_process_htt_completion_rh() - Tx HTT Completion Indication Handler
88  * @soc: Handle to DP soc structure
89  * @tx_desc: software descriptor head pointer
90  * @status : Tx completion status from HTT descriptor
91  * @ring_id: ring number
92  *
93  * This function will process HTT Tx indication messages from Target
94  *
95  * Return: none
96  */
97 void dp_tx_process_htt_completion_rh(struct dp_soc *soc,
98 				     struct dp_tx_desc_s *tx_desc,
99 				     uint8_t *status,
100 				     uint8_t ring_id);
101 
102 /**
103  * dp_tx_desc_pool_init_rh() - Initialize Tx Descriptor pool(s)
104  * @soc: Handle to DP Soc structure
105  * @num_elem: pool descriptor number
106  * @pool_id: pool to allocate
107  * @spcl_tx_desc: if special desc
108  *
109  * Return: QDF_STATUS_SUCCESS - success, others - failure
110  */
111 QDF_STATUS dp_tx_desc_pool_init_rh(struct dp_soc *soc,
112 				   uint32_t num_elem,
113 				   uint8_t pool_id,
114 				   bool spcl_tx_desc);
115 
116 /**
117  * dp_tx_desc_pool_deinit_rh() - De-initialize Tx Descriptor pool(s)
118  * @soc: Handle to DP Soc structure
119  * @tx_desc_pool: Tx descriptor pool handler
120  * @pool_id: pool to deinit
121  * @spcl_tx_desc: if special desc
122  *
123  * Return: None.
124  */
125 void dp_tx_desc_pool_deinit_rh(struct dp_soc *soc,
126 			       struct dp_tx_desc_pool_s *tx_desc_pool,
127 			       uint8_t pool_id, bool spcl_tx_desc);
128 
129 /**
130  * dp_tx_compute_tx_delay_rh() - Compute HW Tx completion delay
131  * @soc: Handle to DP Soc structure
132  * @vdev: vdev
133  * @ts: Tx completion status
134  * @delay_us: Delay to be calculated in microseconds
135  *
136  * Return: QDF_STATUS
137  */
138 QDF_STATUS dp_tx_compute_tx_delay_rh(struct dp_soc *soc,
139 				     struct dp_vdev *vdev,
140 				     struct hal_tx_completion_status *ts,
141 				     uint32_t *delay_us);
142 
143 /**
144  * dp_tx_desc_pool_alloc_rh() - Allocate coherent memory for TCL descriptors
145  * @soc: Handle to DP Soc structure
146  * @num_elem: Number of elements to allocate
147  * @pool_id: TCL descriptor pool ID
148  *
149  * Return: QDF_STATUS_SUCCESS - success, others - failure
150  */
151 QDF_STATUS dp_tx_desc_pool_alloc_rh(struct dp_soc *soc, uint32_t num_elem,
152 				    uint8_t pool_id);
153 
154 /**
155  * dp_tx_desc_pool_free_rh() - Free TCL descriptor memory
156  * @soc: Handle to DP Soc structure
157  * @pool_id: TCL descriptor pool ID
158  *
159  * Return: none
160  */
161 void dp_tx_desc_pool_free_rh(struct dp_soc *soc, uint8_t pool_id);
162 
163 /**
164  * dp_tx_compl_handler_rh() - TX completion handler for Rhine
165  * @soc: Handle to DP Soc structure
166  * @htt_msg: TX completion HTT message
167  *
168  * Return: none
169  */
170 void dp_tx_compl_handler_rh(struct dp_soc *soc, qdf_nbuf_t htt_msg);
171 
172 /**
173  * dp_flush_tx_ring_rh() - flush tx ring write index
174  * @pdev: dp pdev handle
175  * @ring_id: Tx ring id
176  *
177  * Return: 0 on success and error code on failure
178  */
179 int dp_flush_tx_ring_rh(struct dp_pdev *pdev, int ring_id);
180 #endif
181