1 /*
2 * Aspeed 24XX/25XX I2C Controller.
3 *
4 * Copyright (C) 2012-2017 ASPEED Technology Inc.
5 * Copyright 2017 IBM Corporation
6 * Copyright 2017 Google, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32
33 /* I2C Register */
34 #define ASPEED_I2C_FUN_CTRL_REG 0x00
35 #define ASPEED_I2C_AC_TIMING_REG1 0x04
36 #define ASPEED_I2C_AC_TIMING_REG2 0x08
37 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
38 #define ASPEED_I2C_INTR_STS_REG 0x10
39 #define ASPEED_I2C_CMD_REG 0x14
40 #define ASPEED_I2C_DEV_ADDR_REG 0x18
41 #define ASPEED_I2C_BYTE_BUF_REG 0x20
42
43 /* Global Register Definition */
44 /* 0x00 : I2C Interrupt Status Register */
45 /* 0x08 : I2C Interrupt Target Assignment */
46
47 /* Device Register Definition */
48 /* 0x00 : I2CD Function Control Register */
49 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
50 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
51 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
52 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
53 #define ASPEED_I2CD_SLAVE_EN BIT(1)
54 #define ASPEED_I2CD_MASTER_EN BIT(0)
55
56 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
57 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
58 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
59 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
60 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
61 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
62 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
63 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
64 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
65 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
66 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
67 #define ASPEED_NO_TIMEOUT_CTRL 0
68
69 /* 0x0c : I2CD Interrupt Control Register &
70 * 0x10 : I2CD Interrupt Status Register
71 *
72 * These share bit definitions, so use the same values for the enable &
73 * status bits.
74 */
75 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
76 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
77 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
78 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
79 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
80 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
81 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
82 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
83 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
84 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
85 #define ASPEED_I2CD_INTR_ALL \
86 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
87 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
88 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
89 ASPEED_I2CD_INTR_ABNORMAL | \
90 ASPEED_I2CD_INTR_NORMAL_STOP | \
91 ASPEED_I2CD_INTR_ARBIT_LOSS | \
92 ASPEED_I2CD_INTR_RX_DONE | \
93 ASPEED_I2CD_INTR_TX_NAK | \
94 ASPEED_I2CD_INTR_TX_ACK)
95
96 /* 0x14 : I2CD Command/Status Register */
97 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
98 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
99 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
100 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
101
102 /* Command Bit */
103 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
104 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
105 #define ASPEED_I2CD_M_RX_CMD BIT(3)
106 #define ASPEED_I2CD_S_TX_CMD BIT(2)
107 #define ASPEED_I2CD_M_TX_CMD BIT(1)
108 #define ASPEED_I2CD_M_START_CMD BIT(0)
109
110 /* 0x18 : I2CD Slave Device Address Register */
111 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
112
113 enum aspeed_i2c_master_state {
114 ASPEED_I2C_MASTER_INACTIVE,
115 ASPEED_I2C_MASTER_START,
116 ASPEED_I2C_MASTER_TX_FIRST,
117 ASPEED_I2C_MASTER_TX,
118 ASPEED_I2C_MASTER_RX_FIRST,
119 ASPEED_I2C_MASTER_RX,
120 ASPEED_I2C_MASTER_STOP,
121 };
122
123 enum aspeed_i2c_slave_state {
124 ASPEED_I2C_SLAVE_STOP,
125 ASPEED_I2C_SLAVE_START,
126 ASPEED_I2C_SLAVE_READ_REQUESTED,
127 ASPEED_I2C_SLAVE_READ_PROCESSED,
128 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
129 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
130 };
131
132 struct aspeed_i2c_bus {
133 struct i2c_adapter adap;
134 struct device *dev;
135 void __iomem *base;
136 struct reset_control *rst;
137 /* Synchronizes I/O mem access to base. */
138 spinlock_t lock;
139 struct completion cmd_complete;
140 u32 (*get_clk_reg_val)(struct device *dev,
141 u32 divisor);
142 unsigned long parent_clk_frequency;
143 u32 bus_frequency;
144 /* Transaction state. */
145 enum aspeed_i2c_master_state master_state;
146 struct i2c_msg *msgs;
147 size_t buf_index;
148 size_t msgs_index;
149 size_t msgs_count;
150 bool send_stop;
151 int cmd_err;
152 /* Protected only by i2c_lock_bus */
153 int master_xfer_result;
154 #if IS_ENABLED(CONFIG_I2C_SLAVE)
155 struct i2c_client *slave;
156 enum aspeed_i2c_slave_state slave_state;
157 #endif /* CONFIG_I2C_SLAVE */
158 };
159
160 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
161
aspeed_i2c_recover_bus(struct aspeed_i2c_bus * bus)162 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
163 {
164 unsigned long time_left, flags;
165 int ret = 0;
166 u32 command;
167
168 spin_lock_irqsave(&bus->lock, flags);
169 command = readl(bus->base + ASPEED_I2C_CMD_REG);
170
171 if (command & ASPEED_I2CD_SDA_LINE_STS) {
172 /* Bus is idle: no recovery needed. */
173 if (command & ASPEED_I2CD_SCL_LINE_STS)
174 goto out;
175 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
176 command);
177
178 reinit_completion(&bus->cmd_complete);
179 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
180 spin_unlock_irqrestore(&bus->lock, flags);
181
182 time_left = wait_for_completion_timeout(
183 &bus->cmd_complete, bus->adap.timeout);
184
185 spin_lock_irqsave(&bus->lock, flags);
186 if (time_left == 0)
187 goto reset_out;
188 else if (bus->cmd_err)
189 goto reset_out;
190 /* Recovery failed. */
191 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
192 ASPEED_I2CD_SCL_LINE_STS))
193 goto reset_out;
194 /* Bus error. */
195 } else {
196 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
197 command);
198
199 reinit_completion(&bus->cmd_complete);
200 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
201 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
202 bus->base + ASPEED_I2C_CMD_REG);
203 spin_unlock_irqrestore(&bus->lock, flags);
204
205 time_left = wait_for_completion_timeout(
206 &bus->cmd_complete, bus->adap.timeout);
207
208 spin_lock_irqsave(&bus->lock, flags);
209 if (time_left == 0)
210 goto reset_out;
211 else if (bus->cmd_err)
212 goto reset_out;
213 /* Recovery failed. */
214 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
215 ASPEED_I2CD_SDA_LINE_STS))
216 goto reset_out;
217 }
218
219 out:
220 spin_unlock_irqrestore(&bus->lock, flags);
221
222 return ret;
223
224 reset_out:
225 spin_unlock_irqrestore(&bus->lock, flags);
226
227 return aspeed_i2c_reset(bus);
228 }
229
230 #if IS_ENABLED(CONFIG_I2C_SLAVE)
aspeed_i2c_slave_irq(struct aspeed_i2c_bus * bus)231 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
232 {
233 u32 command, irq_status, status_ack = 0;
234 struct i2c_client *slave = bus->slave;
235 bool irq_handled = true;
236 u8 value;
237
238 if (!slave) {
239 irq_handled = false;
240 goto out;
241 }
242
243 command = readl(bus->base + ASPEED_I2C_CMD_REG);
244 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
245
246 /* Slave was requested, restart state machine. */
247 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
248 status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
249 bus->slave_state = ASPEED_I2C_SLAVE_START;
250 }
251
252 /* Slave is not currently active, irq was for someone else. */
253 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
254 irq_handled = false;
255 goto out;
256 }
257
258 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
259 irq_status, command);
260
261 /* Slave was sent something. */
262 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
263 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
264 /* Handle address frame. */
265 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
266 if (value & 0x1)
267 bus->slave_state =
268 ASPEED_I2C_SLAVE_READ_REQUESTED;
269 else
270 bus->slave_state =
271 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
272 }
273 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
274 }
275
276 /* Slave was asked to stop. */
277 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
278 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
279 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
280 }
281 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
282 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
283 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
284 }
285
286 switch (bus->slave_state) {
287 case ASPEED_I2C_SLAVE_READ_REQUESTED:
288 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
289 dev_err(bus->dev, "Unexpected ACK on read request.\n");
290 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
291
292 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
293 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
294 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
295 break;
296 case ASPEED_I2C_SLAVE_READ_PROCESSED:
297 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
298 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
299 dev_err(bus->dev,
300 "Expected ACK after processed read.\n");
301 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
302 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
303 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
304 break;
305 case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
306 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
307 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
308 break;
309 case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
310 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
311 break;
312 case ASPEED_I2C_SLAVE_STOP:
313 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
314 break;
315 default:
316 dev_err(bus->dev, "unhandled slave_state: %d\n",
317 bus->slave_state);
318 break;
319 }
320
321 if (status_ack != irq_status)
322 dev_err(bus->dev,
323 "irq handled != irq. expected %x, but was %x\n",
324 irq_status, status_ack);
325 writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG);
326
327 out:
328 return irq_handled;
329 }
330 #endif /* CONFIG_I2C_SLAVE */
331
332 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_start(struct aspeed_i2c_bus * bus)333 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
334 {
335 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
336 struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
337 u8 slave_addr = i2c_8bit_addr_from_msg(msg);
338
339 bus->master_state = ASPEED_I2C_MASTER_START;
340 bus->buf_index = 0;
341
342 if (msg->flags & I2C_M_RD) {
343 command |= ASPEED_I2CD_M_RX_CMD;
344 /* Need to let the hardware know to NACK after RX. */
345 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
346 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
347 }
348
349 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
350 writel(command, bus->base + ASPEED_I2C_CMD_REG);
351 }
352
353 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_stop(struct aspeed_i2c_bus * bus)354 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
355 {
356 bus->master_state = ASPEED_I2C_MASTER_STOP;
357 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
358 }
359
360 /* precondition: bus.lock has been acquired. */
aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus * bus)361 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
362 {
363 if (bus->msgs_index + 1 < bus->msgs_count) {
364 bus->msgs_index++;
365 aspeed_i2c_do_start(bus);
366 } else {
367 aspeed_i2c_do_stop(bus);
368 }
369 }
370
aspeed_i2c_is_irq_error(u32 irq_status)371 static int aspeed_i2c_is_irq_error(u32 irq_status)
372 {
373 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
374 return -EAGAIN;
375 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
376 ASPEED_I2CD_INTR_SCL_TIMEOUT))
377 return -EBUSY;
378 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
379 return -EPROTO;
380
381 return 0;
382 }
383
aspeed_i2c_master_irq(struct aspeed_i2c_bus * bus)384 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
385 {
386 u32 irq_status, status_ack = 0, command = 0;
387 struct i2c_msg *msg;
388 u8 recv_byte;
389 int ret;
390
391 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
392 /* Ack all interrupt bits. */
393 writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG);
394
395 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
396 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
397 status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
398 goto out_complete;
399 }
400
401 /*
402 * We encountered an interrupt that reports an error: the hardware
403 * should clear the command queue effectively taking us back to the
404 * INACTIVE state.
405 */
406 ret = aspeed_i2c_is_irq_error(irq_status);
407 if (ret < 0) {
408 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
409 irq_status);
410 bus->cmd_err = ret;
411 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
412 goto out_complete;
413 }
414
415 /* We are in an invalid state; reset bus to a known state. */
416 if (!bus->msgs) {
417 dev_err(bus->dev, "bus in unknown state\n");
418 bus->cmd_err = -EIO;
419 if (bus->master_state != ASPEED_I2C_MASTER_STOP)
420 aspeed_i2c_do_stop(bus);
421 goto out_no_complete;
422 }
423 msg = &bus->msgs[bus->msgs_index];
424
425 /*
426 * START is a special case because we still have to handle a subsequent
427 * TX or RX immediately after we handle it, so we handle it here and
428 * then update the state and handle the new state below.
429 */
430 if (bus->master_state == ASPEED_I2C_MASTER_START) {
431 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
432 pr_devel("no slave present at %02x\n", msg->addr);
433 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
434 bus->cmd_err = -ENXIO;
435 aspeed_i2c_do_stop(bus);
436 goto out_no_complete;
437 }
438 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
439 if (msg->len == 0) { /* SMBUS_QUICK */
440 aspeed_i2c_do_stop(bus);
441 goto out_no_complete;
442 }
443 if (msg->flags & I2C_M_RD)
444 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
445 else
446 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
447 }
448
449 switch (bus->master_state) {
450 case ASPEED_I2C_MASTER_TX:
451 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
452 dev_dbg(bus->dev, "slave NACKed TX\n");
453 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
454 goto error_and_stop;
455 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
456 dev_err(bus->dev, "slave failed to ACK TX\n");
457 goto error_and_stop;
458 }
459 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
460 /* fallthrough intended */
461 case ASPEED_I2C_MASTER_TX_FIRST:
462 if (bus->buf_index < msg->len) {
463 bus->master_state = ASPEED_I2C_MASTER_TX;
464 writel(msg->buf[bus->buf_index++],
465 bus->base + ASPEED_I2C_BYTE_BUF_REG);
466 writel(ASPEED_I2CD_M_TX_CMD,
467 bus->base + ASPEED_I2C_CMD_REG);
468 } else {
469 aspeed_i2c_next_msg_or_stop(bus);
470 }
471 goto out_no_complete;
472 case ASPEED_I2C_MASTER_RX_FIRST:
473 /* RX may not have completed yet (only address cycle) */
474 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
475 goto out_no_complete;
476 /* fallthrough intended */
477 case ASPEED_I2C_MASTER_RX:
478 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
479 dev_err(bus->dev, "master failed to RX\n");
480 goto error_and_stop;
481 }
482 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
483
484 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
485 msg->buf[bus->buf_index++] = recv_byte;
486
487 if (msg->flags & I2C_M_RECV_LEN) {
488 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
489 bus->cmd_err = -EPROTO;
490 aspeed_i2c_do_stop(bus);
491 goto out_no_complete;
492 }
493 msg->len = recv_byte +
494 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
495 msg->flags &= ~I2C_M_RECV_LEN;
496 }
497
498 if (bus->buf_index < msg->len) {
499 bus->master_state = ASPEED_I2C_MASTER_RX;
500 command = ASPEED_I2CD_M_RX_CMD;
501 if (bus->buf_index + 1 == msg->len)
502 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
503 writel(command, bus->base + ASPEED_I2C_CMD_REG);
504 } else {
505 aspeed_i2c_next_msg_or_stop(bus);
506 }
507 goto out_no_complete;
508 case ASPEED_I2C_MASTER_STOP:
509 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
510 dev_err(bus->dev, "master failed to STOP\n");
511 bus->cmd_err = -EIO;
512 /* Do not STOP as we have already tried. */
513 } else {
514 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
515 }
516
517 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
518 goto out_complete;
519 case ASPEED_I2C_MASTER_INACTIVE:
520 dev_err(bus->dev,
521 "master received interrupt 0x%08x, but is inactive\n",
522 irq_status);
523 bus->cmd_err = -EIO;
524 /* Do not STOP as we should be inactive. */
525 goto out_complete;
526 default:
527 WARN(1, "unknown master state\n");
528 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
529 bus->cmd_err = -EINVAL;
530 goto out_complete;
531 }
532 error_and_stop:
533 bus->cmd_err = -EIO;
534 aspeed_i2c_do_stop(bus);
535 goto out_no_complete;
536 out_complete:
537 bus->msgs = NULL;
538 if (bus->cmd_err)
539 bus->master_xfer_result = bus->cmd_err;
540 else
541 bus->master_xfer_result = bus->msgs_index + 1;
542 complete(&bus->cmd_complete);
543 out_no_complete:
544 if (irq_status != status_ack)
545 dev_err(bus->dev,
546 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
547 irq_status, status_ack);
548 return !!irq_status;
549 }
550
aspeed_i2c_bus_irq(int irq,void * dev_id)551 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
552 {
553 struct aspeed_i2c_bus *bus = dev_id;
554 bool ret;
555
556 spin_lock(&bus->lock);
557
558 #if IS_ENABLED(CONFIG_I2C_SLAVE)
559 if (IS_ENABLED(CONFIG_I2C_SLAVE) && aspeed_i2c_slave_irq(bus)) {
560 dev_dbg(bus->dev, "irq handled by slave.\n");
561 ret = true;
562 goto out;
563 }
564 #endif /* CONFIG_I2C_SLAVE */
565
566 ret = aspeed_i2c_master_irq(bus);
567
568 #if IS_ENABLED(CONFIG_I2C_SLAVE)
569 out:
570 #endif
571 spin_unlock(&bus->lock);
572 return ret ? IRQ_HANDLED : IRQ_NONE;
573 }
574
aspeed_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)575 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
576 struct i2c_msg *msgs, int num)
577 {
578 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
579 unsigned long time_left, flags;
580 int ret = 0;
581
582 spin_lock_irqsave(&bus->lock, flags);
583 bus->cmd_err = 0;
584
585 /* If bus is busy, attempt recovery. We assume a single master
586 * environment.
587 */
588 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
589 spin_unlock_irqrestore(&bus->lock, flags);
590 ret = aspeed_i2c_recover_bus(bus);
591 if (ret)
592 return ret;
593 spin_lock_irqsave(&bus->lock, flags);
594 }
595
596 bus->cmd_err = 0;
597 bus->msgs = msgs;
598 bus->msgs_index = 0;
599 bus->msgs_count = num;
600
601 reinit_completion(&bus->cmd_complete);
602 aspeed_i2c_do_start(bus);
603 spin_unlock_irqrestore(&bus->lock, flags);
604
605 time_left = wait_for_completion_timeout(&bus->cmd_complete,
606 bus->adap.timeout);
607
608 if (time_left == 0)
609 return -ETIMEDOUT;
610 else
611 return bus->master_xfer_result;
612 }
613
aspeed_i2c_functionality(struct i2c_adapter * adap)614 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
615 {
616 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
617 }
618
619 #if IS_ENABLED(CONFIG_I2C_SLAVE)
620 /* precondition: bus.lock has been acquired. */
__aspeed_i2c_reg_slave(struct aspeed_i2c_bus * bus,u16 slave_addr)621 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
622 {
623 u32 addr_reg_val, func_ctrl_reg_val;
624
625 /* Set slave addr. */
626 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
627 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
628 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
629 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
630
631 /* Turn on slave mode. */
632 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
633 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
634 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
635 }
636
aspeed_i2c_reg_slave(struct i2c_client * client)637 static int aspeed_i2c_reg_slave(struct i2c_client *client)
638 {
639 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
640 unsigned long flags;
641
642 spin_lock_irqsave(&bus->lock, flags);
643 if (bus->slave) {
644 spin_unlock_irqrestore(&bus->lock, flags);
645 return -EINVAL;
646 }
647
648 __aspeed_i2c_reg_slave(bus, client->addr);
649
650 bus->slave = client;
651 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
652 spin_unlock_irqrestore(&bus->lock, flags);
653
654 return 0;
655 }
656
aspeed_i2c_unreg_slave(struct i2c_client * client)657 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
658 {
659 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
660 u32 func_ctrl_reg_val;
661 unsigned long flags;
662
663 spin_lock_irqsave(&bus->lock, flags);
664 if (!bus->slave) {
665 spin_unlock_irqrestore(&bus->lock, flags);
666 return -EINVAL;
667 }
668
669 /* Turn off slave mode. */
670 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
671 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
672 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
673
674 bus->slave = NULL;
675 spin_unlock_irqrestore(&bus->lock, flags);
676
677 return 0;
678 }
679 #endif /* CONFIG_I2C_SLAVE */
680
681 static const struct i2c_algorithm aspeed_i2c_algo = {
682 .master_xfer = aspeed_i2c_master_xfer,
683 .functionality = aspeed_i2c_functionality,
684 #if IS_ENABLED(CONFIG_I2C_SLAVE)
685 .reg_slave = aspeed_i2c_reg_slave,
686 .unreg_slave = aspeed_i2c_unreg_slave,
687 #endif /* CONFIG_I2C_SLAVE */
688 };
689
aspeed_i2c_get_clk_reg_val(struct device * dev,u32 clk_high_low_mask,u32 divisor)690 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
691 u32 clk_high_low_mask,
692 u32 divisor)
693 {
694 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
695
696 /*
697 * SCL_high and SCL_low represent a value 1 greater than what is stored
698 * since a zero divider is meaningless. Thus, the max value each can
699 * store is every bit set + 1. Since SCL_high and SCL_low are added
700 * together (see below), the max value of both is the max value of one
701 * them times two.
702 */
703 clk_high_low_max = (clk_high_low_mask + 1) * 2;
704
705 /*
706 * The actual clock frequency of SCL is:
707 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
708 * = APB_freq / divisor
709 * where base_freq is a programmable clock divider; its value is
710 * base_freq = 1 << base_clk_divisor
711 * SCL_high is the number of base_freq clock cycles that SCL stays high
712 * and SCL_low is the number of base_freq clock cycles that SCL stays
713 * low for a period of SCL.
714 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
715 * thus, they start counting at zero. So
716 * SCL_high = clk_high + 1
717 * SCL_low = clk_low + 1
718 * Thus,
719 * SCL_freq = APB_freq /
720 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
721 * The documentation recommends clk_high >= clk_high_max / 2 and
722 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
723 * gives us the following solution:
724 */
725 base_clk_divisor = divisor > clk_high_low_max ?
726 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
727
728 if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
729 base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
730 clk_low = clk_high_low_mask;
731 clk_high = clk_high_low_mask;
732 dev_err(dev,
733 "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
734 divisor, (1 << base_clk_divisor) * clk_high_low_max);
735 } else {
736 tmp = (divisor + (1 << base_clk_divisor) - 1)
737 >> base_clk_divisor;
738 clk_low = tmp / 2;
739 clk_high = tmp - clk_low;
740
741 if (clk_high)
742 clk_high--;
743
744 if (clk_low)
745 clk_low--;
746 }
747
748
749 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
750 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
751 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
752 & ASPEED_I2CD_TIME_SCL_LOW_MASK)
753 | (base_clk_divisor
754 & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
755 }
756
aspeed_i2c_24xx_get_clk_reg_val(struct device * dev,u32 divisor)757 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
758 {
759 /*
760 * clk_high and clk_low are each 3 bits wide, so each can hold a max
761 * value of 8 giving a clk_high_low_max of 16.
762 */
763 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
764 }
765
aspeed_i2c_25xx_get_clk_reg_val(struct device * dev,u32 divisor)766 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
767 {
768 /*
769 * clk_high and clk_low are each 4 bits wide, so each can hold a max
770 * value of 16 giving a clk_high_low_max of 32.
771 */
772 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
773 }
774
775 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init_clk(struct aspeed_i2c_bus * bus)776 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
777 {
778 u32 divisor, clk_reg_val;
779
780 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
781 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
782 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
783 ASPEED_I2CD_TIME_THDSTA_MASK |
784 ASPEED_I2CD_TIME_TACST_MASK);
785 clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
786 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
787 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
788
789 return 0;
790 }
791
792 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init(struct aspeed_i2c_bus * bus,struct platform_device * pdev)793 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
794 struct platform_device *pdev)
795 {
796 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
797 int ret;
798
799 /* Disable everything. */
800 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
801
802 ret = aspeed_i2c_init_clk(bus);
803 if (ret < 0)
804 return ret;
805
806 if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
807 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
808
809 /* Enable Master Mode */
810 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
811 bus->base + ASPEED_I2C_FUN_CTRL_REG);
812
813 #if IS_ENABLED(CONFIG_I2C_SLAVE)
814 /* If slave has already been registered, re-enable it. */
815 if (bus->slave)
816 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
817 #endif /* CONFIG_I2C_SLAVE */
818
819 /* Set interrupt generation of I2C controller */
820 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
821
822 return 0;
823 }
824
aspeed_i2c_reset(struct aspeed_i2c_bus * bus)825 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
826 {
827 struct platform_device *pdev = to_platform_device(bus->dev);
828 unsigned long flags;
829 int ret;
830
831 spin_lock_irqsave(&bus->lock, flags);
832
833 /* Disable and ack all interrupts. */
834 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
835 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
836
837 ret = aspeed_i2c_init(bus, pdev);
838
839 spin_unlock_irqrestore(&bus->lock, flags);
840
841 return ret;
842 }
843
844 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
845 {
846 .compatible = "aspeed,ast2400-i2c-bus",
847 .data = aspeed_i2c_24xx_get_clk_reg_val,
848 },
849 {
850 .compatible = "aspeed,ast2500-i2c-bus",
851 .data = aspeed_i2c_25xx_get_clk_reg_val,
852 },
853 { },
854 };
855 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
856
aspeed_i2c_probe_bus(struct platform_device * pdev)857 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
858 {
859 const struct of_device_id *match;
860 struct aspeed_i2c_bus *bus;
861 struct clk *parent_clk;
862 struct resource *res;
863 int irq, ret;
864
865 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
866 if (!bus)
867 return -ENOMEM;
868
869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 bus->base = devm_ioremap_resource(&pdev->dev, res);
871 if (IS_ERR(bus->base))
872 return PTR_ERR(bus->base);
873
874 parent_clk = devm_clk_get(&pdev->dev, NULL);
875 if (IS_ERR(parent_clk))
876 return PTR_ERR(parent_clk);
877 bus->parent_clk_frequency = clk_get_rate(parent_clk);
878 /* We just need the clock rate, we don't actually use the clk object. */
879 devm_clk_put(&pdev->dev, parent_clk);
880
881 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
882 if (IS_ERR(bus->rst)) {
883 dev_err(&pdev->dev,
884 "missing or invalid reset controller device tree entry\n");
885 return PTR_ERR(bus->rst);
886 }
887 reset_control_deassert(bus->rst);
888
889 ret = of_property_read_u32(pdev->dev.of_node,
890 "bus-frequency", &bus->bus_frequency);
891 if (ret < 0) {
892 dev_err(&pdev->dev,
893 "Could not read bus-frequency property\n");
894 bus->bus_frequency = 100000;
895 }
896
897 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
898 if (!match)
899 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
900 else
901 bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
902 match->data;
903
904 /* Initialize the I2C adapter */
905 spin_lock_init(&bus->lock);
906 init_completion(&bus->cmd_complete);
907 bus->adap.owner = THIS_MODULE;
908 bus->adap.retries = 0;
909 bus->adap.timeout = 5 * HZ;
910 bus->adap.algo = &aspeed_i2c_algo;
911 bus->adap.dev.parent = &pdev->dev;
912 bus->adap.dev.of_node = pdev->dev.of_node;
913 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
914 i2c_set_adapdata(&bus->adap, bus);
915
916 bus->dev = &pdev->dev;
917
918 /* Clean up any left over interrupt state. */
919 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
920 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
921 /*
922 * bus.lock does not need to be held because the interrupt handler has
923 * not been enabled yet.
924 */
925 ret = aspeed_i2c_init(bus, pdev);
926 if (ret < 0)
927 return ret;
928
929 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
930 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
931 0, dev_name(&pdev->dev), bus);
932 if (ret < 0)
933 return ret;
934
935 ret = i2c_add_adapter(&bus->adap);
936 if (ret < 0)
937 return ret;
938
939 platform_set_drvdata(pdev, bus);
940
941 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
942 bus->adap.nr, irq);
943
944 return 0;
945 }
946
aspeed_i2c_remove_bus(struct platform_device * pdev)947 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
948 {
949 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
950 unsigned long flags;
951
952 spin_lock_irqsave(&bus->lock, flags);
953
954 /* Disable everything. */
955 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
956 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
957
958 spin_unlock_irqrestore(&bus->lock, flags);
959
960 reset_control_assert(bus->rst);
961
962 i2c_del_adapter(&bus->adap);
963
964 return 0;
965 }
966
967 static struct platform_driver aspeed_i2c_bus_driver = {
968 .probe = aspeed_i2c_probe_bus,
969 .remove = aspeed_i2c_remove_bus,
970 .driver = {
971 .name = "aspeed-i2c-bus",
972 .of_match_table = aspeed_i2c_bus_of_table,
973 },
974 };
975 module_platform_driver(aspeed_i2c_bus_driver);
976
977 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
978 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
979 MODULE_LICENSE("GPL v2");
980