1 /*
2 * I2C bus driver for the Cadence I2C controller.
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/of.h>
21 #include <linux/pm_runtime.h>
22
23 /* Register offsets for the I2C device. */
24 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
25 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
26 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
27 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
28 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
29 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
30 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
31 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
32 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
33
34 /* Control Register Bit mask definitions */
35 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
36 #define CDNS_I2C_CR_ACK_EN BIT(3)
37 #define CDNS_I2C_CR_NEA BIT(2)
38 #define CDNS_I2C_CR_MS BIT(1)
39 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
40 #define CDNS_I2C_CR_RW BIT(0)
41 /* 1 = Auto init FIFO to zeroes */
42 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
43 #define CDNS_I2C_CR_DIVA_SHIFT 14
44 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
45 #define CDNS_I2C_CR_DIVB_SHIFT 8
46 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
47
48 /* Status Register Bit mask definitions */
49 #define CDNS_I2C_SR_BA BIT(8)
50 #define CDNS_I2C_SR_RXDV BIT(5)
51
52 /*
53 * I2C Address Register Bit mask definitions
54 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
55 * bits. A write access to this register always initiates a transfer if the I2C
56 * is in master mode.
57 */
58 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
59
60 /*
61 * I2C Interrupt Registers Bit mask definitions
62 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
63 * bit definitions.
64 */
65 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
66 #define CDNS_I2C_IXR_RX_UNF BIT(7)
67 #define CDNS_I2C_IXR_TX_OVF BIT(6)
68 #define CDNS_I2C_IXR_RX_OVF BIT(5)
69 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
70 #define CDNS_I2C_IXR_TO BIT(3)
71 #define CDNS_I2C_IXR_NACK BIT(2)
72 #define CDNS_I2C_IXR_DATA BIT(1)
73 #define CDNS_I2C_IXR_COMP BIT(0)
74
75 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
76 CDNS_I2C_IXR_RX_UNF | \
77 CDNS_I2C_IXR_TX_OVF | \
78 CDNS_I2C_IXR_RX_OVF | \
79 CDNS_I2C_IXR_SLV_RDY | \
80 CDNS_I2C_IXR_TO | \
81 CDNS_I2C_IXR_NACK | \
82 CDNS_I2C_IXR_DATA | \
83 CDNS_I2C_IXR_COMP)
84
85 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
86 CDNS_I2C_IXR_RX_UNF | \
87 CDNS_I2C_IXR_TX_OVF | \
88 CDNS_I2C_IXR_RX_OVF | \
89 CDNS_I2C_IXR_NACK)
90
91 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
92 CDNS_I2C_IXR_RX_UNF | \
93 CDNS_I2C_IXR_TX_OVF | \
94 CDNS_I2C_IXR_RX_OVF | \
95 CDNS_I2C_IXR_NACK | \
96 CDNS_I2C_IXR_DATA | \
97 CDNS_I2C_IXR_COMP)
98
99 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
100 /* timeout for pm runtime autosuspend */
101 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
102
103 #define CDNS_I2C_FIFO_DEPTH 16
104 /* FIFO depth at which the DATA interrupt occurs */
105 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
106 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
107 /* Transfer size in multiples of data interrupt depth */
108 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
109
110 #define DRIVER_NAME "cdns-i2c"
111
112 #define CDNS_I2C_SPEED_MAX 400000
113 #define CDNS_I2C_SPEED_DEFAULT 100000
114
115 #define CDNS_I2C_DIVA_MAX 4
116 #define CDNS_I2C_DIVB_MAX 64
117
118 #define CDNS_I2C_TIMEOUT_MAX 0xFF
119
120 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
121
122 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
123 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
124
125 /**
126 * struct cdns_i2c - I2C device private data structure
127 *
128 * @dev: Pointer to device structure
129 * @membase: Base address of the I2C device
130 * @adap: I2C adapter instance
131 * @p_msg: Message pointer
132 * @err_status: Error status in Interrupt Status Register
133 * @xfer_done: Transfer complete status
134 * @p_send_buf: Pointer to transmit buffer
135 * @p_recv_buf: Pointer to receive buffer
136 * @send_count: Number of bytes still expected to send
137 * @recv_count: Number of bytes still expected to receive
138 * @curr_recv_count: Number of bytes to be received in current transfer
139 * @irq: IRQ number
140 * @input_clk: Input clock to I2C controller
141 * @i2c_clk: Maximum I2C clock speed
142 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
143 * @clk: Pointer to struct clk
144 * @clk_rate_change_nb: Notifier block for clock rate changes
145 * @quirks: flag for broken hold bit usage in r1p10
146 */
147 struct cdns_i2c {
148 struct device *dev;
149 void __iomem *membase;
150 struct i2c_adapter adap;
151 struct i2c_msg *p_msg;
152 int err_status;
153 struct completion xfer_done;
154 unsigned char *p_send_buf;
155 unsigned char *p_recv_buf;
156 unsigned int send_count;
157 unsigned int recv_count;
158 unsigned int curr_recv_count;
159 int irq;
160 unsigned long input_clk;
161 unsigned int i2c_clk;
162 unsigned int bus_hold_flag;
163 struct clk *clk;
164 struct notifier_block clk_rate_change_nb;
165 u32 quirks;
166 };
167
168 struct cdns_platform_data {
169 u32 quirks;
170 };
171
172 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
173 clk_rate_change_nb)
174
175 /**
176 * cdns_i2c_clear_bus_hold - Clear bus hold bit
177 * @id: Pointer to driver data struct
178 *
179 * Helper to clear the controller's bus hold bit.
180 */
cdns_i2c_clear_bus_hold(struct cdns_i2c * id)181 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
182 {
183 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
184 if (reg & CDNS_I2C_CR_HOLD)
185 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
186 }
187
cdns_is_holdquirk(struct cdns_i2c * id,bool hold_wrkaround)188 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
189 {
190 return (hold_wrkaround &&
191 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
192 }
193
194 /**
195 * cdns_i2c_isr - Interrupt handler for the I2C device
196 * @irq: irq number for the I2C device
197 * @ptr: void pointer to cdns_i2c structure
198 *
199 * This function handles the data interrupt, transfer complete interrupt and
200 * the error interrupts of the I2C device.
201 *
202 * Return: IRQ_HANDLED always
203 */
cdns_i2c_isr(int irq,void * ptr)204 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
205 {
206 unsigned int isr_status, avail_bytes;
207 unsigned int bytes_to_send;
208 bool updatetx;
209 struct cdns_i2c *id = ptr;
210 /* Signal completion only after everything is updated */
211 int done_flag = 0;
212 irqreturn_t status = IRQ_NONE;
213
214 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
215 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
216
217 /* Handling nack and arbitration lost interrupt */
218 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
219 done_flag = 1;
220 status = IRQ_HANDLED;
221 }
222
223 /*
224 * Check if transfer size register needs to be updated again for a
225 * large data receive operation.
226 */
227 updatetx = id->recv_count > id->curr_recv_count;
228
229 /* When receiving, handle data interrupt and completion interrupt */
230 if (id->p_recv_buf &&
231 ((isr_status & CDNS_I2C_IXR_COMP) ||
232 (isr_status & CDNS_I2C_IXR_DATA))) {
233 /* Read data if receive data valid is set */
234 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
235 CDNS_I2C_SR_RXDV) {
236 /*
237 * Clear hold bit that was set for FIFO control if
238 * RX data left is less than FIFO depth, unless
239 * repeated start is selected.
240 */
241 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
242 !id->bus_hold_flag)
243 cdns_i2c_clear_bus_hold(id);
244
245 *(id->p_recv_buf)++ =
246 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
247 id->recv_count--;
248 id->curr_recv_count--;
249
250 if (cdns_is_holdquirk(id, updatetx))
251 break;
252 }
253
254 /*
255 * The controller sends NACK to the slave when transfer size
256 * register reaches zero without considering the HOLD bit.
257 * This workaround is implemented for large data transfers to
258 * maintain transfer size non-zero while performing a large
259 * receive operation.
260 */
261 if (cdns_is_holdquirk(id, updatetx)) {
262 /* wait while fifo is full */
263 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
264 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
265 ;
266
267 /*
268 * Check number of bytes to be received against maximum
269 * transfer size and update register accordingly.
270 */
271 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
272 CDNS_I2C_TRANSFER_SIZE) {
273 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
274 CDNS_I2C_XFER_SIZE_OFFSET);
275 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
276 CDNS_I2C_FIFO_DEPTH;
277 } else {
278 cdns_i2c_writereg(id->recv_count -
279 CDNS_I2C_FIFO_DEPTH,
280 CDNS_I2C_XFER_SIZE_OFFSET);
281 id->curr_recv_count = id->recv_count;
282 }
283 }
284
285 /* Clear hold (if not repeated start) and signal completion */
286 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
287 if (!id->bus_hold_flag)
288 cdns_i2c_clear_bus_hold(id);
289 done_flag = 1;
290 }
291
292 status = IRQ_HANDLED;
293 }
294
295 /* When sending, handle transfer complete interrupt */
296 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
297 /*
298 * If there is more data to be sent, calculate the
299 * space available in FIFO and fill with that many bytes.
300 */
301 if (id->send_count) {
302 avail_bytes = CDNS_I2C_FIFO_DEPTH -
303 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
304 if (id->send_count > avail_bytes)
305 bytes_to_send = avail_bytes;
306 else
307 bytes_to_send = id->send_count;
308
309 while (bytes_to_send--) {
310 cdns_i2c_writereg(
311 (*(id->p_send_buf)++),
312 CDNS_I2C_DATA_OFFSET);
313 id->send_count--;
314 }
315 } else {
316 /*
317 * Signal the completion of transaction and
318 * clear the hold bus bit if there are no
319 * further messages to be processed.
320 */
321 done_flag = 1;
322 }
323 if (!id->send_count && !id->bus_hold_flag)
324 cdns_i2c_clear_bus_hold(id);
325
326 status = IRQ_HANDLED;
327 }
328
329 /* Update the status for errors */
330 id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
331 if (id->err_status)
332 status = IRQ_HANDLED;
333
334 if (done_flag)
335 complete(&id->xfer_done);
336
337 return status;
338 }
339
340 /**
341 * cdns_i2c_mrecv - Prepare and start a master receive operation
342 * @id: pointer to the i2c device structure
343 */
cdns_i2c_mrecv(struct cdns_i2c * id)344 static void cdns_i2c_mrecv(struct cdns_i2c *id)
345 {
346 unsigned int ctrl_reg;
347 unsigned int isr_status;
348
349 id->p_recv_buf = id->p_msg->buf;
350 id->recv_count = id->p_msg->len;
351
352 /* Put the controller in master receive mode and clear the FIFO */
353 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
354 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
355
356 /*
357 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
358 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
359 * PEC is enabled, otherwise 1.
360 */
361 if (id->p_msg->flags & I2C_M_RECV_LEN)
362 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
363
364 id->curr_recv_count = id->recv_count;
365
366 /*
367 * Check for the message size against FIFO depth and set the
368 * 'hold bus' bit if it is greater than FIFO depth.
369 */
370 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
371 ctrl_reg |= CDNS_I2C_CR_HOLD;
372
373 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
374
375 /* Clear the interrupts in interrupt status register */
376 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
377 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
378
379 /*
380 * The no. of bytes to receive is checked against the limit of
381 * max transfer size. Set transfer size register with no of bytes
382 * receive if it is less than transfer size and transfer size if
383 * it is more. Enable the interrupts.
384 */
385 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
386 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
387 CDNS_I2C_XFER_SIZE_OFFSET);
388 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
389 } else {
390 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
391 }
392
393 /* Set the slave address in address register - triggers operation */
394 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
395 CDNS_I2C_ADDR_OFFSET);
396 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
397 if (!id->bus_hold_flag &&
398 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
399 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
400 cdns_i2c_clear_bus_hold(id);
401 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
402 }
403
404 /**
405 * cdns_i2c_msend - Prepare and start a master send operation
406 * @id: pointer to the i2c device
407 */
cdns_i2c_msend(struct cdns_i2c * id)408 static void cdns_i2c_msend(struct cdns_i2c *id)
409 {
410 unsigned int avail_bytes;
411 unsigned int bytes_to_send;
412 unsigned int ctrl_reg;
413 unsigned int isr_status;
414
415 id->p_recv_buf = NULL;
416 id->p_send_buf = id->p_msg->buf;
417 id->send_count = id->p_msg->len;
418
419 /* Set the controller in Master transmit mode and clear the FIFO. */
420 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
421 ctrl_reg &= ~CDNS_I2C_CR_RW;
422 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
423
424 /*
425 * Check for the message size against FIFO depth and set the
426 * 'hold bus' bit if it is greater than FIFO depth.
427 */
428 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
429 ctrl_reg |= CDNS_I2C_CR_HOLD;
430 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
431
432 /* Clear the interrupts in interrupt status register. */
433 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
434 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
435
436 /*
437 * Calculate the space available in FIFO. Check the message length
438 * against the space available, and fill the FIFO accordingly.
439 * Enable the interrupts.
440 */
441 avail_bytes = CDNS_I2C_FIFO_DEPTH -
442 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
443
444 if (id->send_count > avail_bytes)
445 bytes_to_send = avail_bytes;
446 else
447 bytes_to_send = id->send_count;
448
449 while (bytes_to_send--) {
450 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
451 id->send_count--;
452 }
453
454 /*
455 * Clear the bus hold flag if there is no more data
456 * and if it is the last message.
457 */
458 if (!id->bus_hold_flag && !id->send_count)
459 cdns_i2c_clear_bus_hold(id);
460 /* Set the slave address in address register - triggers operation. */
461 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
462 CDNS_I2C_ADDR_OFFSET);
463
464 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
465 }
466
467 /**
468 * cdns_i2c_master_reset - Reset the interface
469 * @adap: pointer to the i2c adapter driver instance
470 *
471 * This function cleanup the fifos, clear the hold bit and status
472 * and disable the interrupts.
473 */
cdns_i2c_master_reset(struct i2c_adapter * adap)474 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
475 {
476 struct cdns_i2c *id = adap->algo_data;
477 u32 regval;
478
479 /* Disable the interrupts */
480 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
481 /* Clear the hold bit and fifos */
482 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
483 regval &= ~CDNS_I2C_CR_HOLD;
484 regval |= CDNS_I2C_CR_CLR_FIFO;
485 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
486 /* Update the transfercount register to zero */
487 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
488 /* Clear the interupt status register */
489 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
490 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
491 /* Clear the status register */
492 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
493 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
494 }
495
cdns_i2c_process_msg(struct cdns_i2c * id,struct i2c_msg * msg,struct i2c_adapter * adap)496 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
497 struct i2c_adapter *adap)
498 {
499 unsigned long time_left, msg_timeout;
500 u32 reg;
501
502 id->p_msg = msg;
503 id->err_status = 0;
504 reinit_completion(&id->xfer_done);
505
506 /* Check for the TEN Bit mode on each msg */
507 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
508 if (msg->flags & I2C_M_TEN) {
509 if (reg & CDNS_I2C_CR_NEA)
510 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
511 CDNS_I2C_CR_OFFSET);
512 } else {
513 if (!(reg & CDNS_I2C_CR_NEA))
514 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
515 CDNS_I2C_CR_OFFSET);
516 }
517
518 /* Check for the R/W flag on each msg */
519 if (msg->flags & I2C_M_RD)
520 cdns_i2c_mrecv(id);
521 else
522 cdns_i2c_msend(id);
523
524 /* Minimal time to execute this message */
525 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
526 /* Plus some wiggle room */
527 msg_timeout += msecs_to_jiffies(500);
528
529 if (msg_timeout < adap->timeout)
530 msg_timeout = adap->timeout;
531
532 /* Wait for the signal of completion */
533 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
534 if (time_left == 0) {
535 cdns_i2c_master_reset(adap);
536 dev_err(id->adap.dev.parent,
537 "timeout waiting on completion\n");
538 return -ETIMEDOUT;
539 }
540
541 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
542 CDNS_I2C_IDR_OFFSET);
543
544 /* If it is bus arbitration error, try again */
545 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
546 return -EAGAIN;
547
548 if (msg->flags & I2C_M_RECV_LEN)
549 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
550
551 return 0;
552 }
553
554 /**
555 * cdns_i2c_master_xfer - The main i2c transfer function
556 * @adap: pointer to the i2c adapter driver instance
557 * @msgs: pointer to the i2c message structure
558 * @num: the number of messages to transfer
559 *
560 * Initiates the send/recv activity based on the transfer message received.
561 *
562 * Return: number of msgs processed on success, negative error otherwise
563 */
cdns_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)564 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
565 int num)
566 {
567 int ret, count;
568 u32 reg;
569 struct cdns_i2c *id = adap->algo_data;
570 bool hold_quirk;
571
572 ret = pm_runtime_get_sync(id->dev);
573 if (ret < 0)
574 return ret;
575 /* Check if the bus is free */
576 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
577 ret = -EAGAIN;
578 goto out;
579 }
580
581 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
582 /*
583 * Set the flag to one when multiple messages are to be
584 * processed with a repeated start.
585 */
586 if (num > 1) {
587 /*
588 * This controller does not give completion interrupt after a
589 * master receive message if HOLD bit is set (repeated start),
590 * resulting in SW timeout. Hence, if a receive message is
591 * followed by any other message, an error is returned
592 * indicating that this sequence is not supported.
593 */
594 for (count = 0; (count < num - 1 && hold_quirk); count++) {
595 if (msgs[count].flags & I2C_M_RD) {
596 dev_warn(adap->dev.parent,
597 "Can't do repeated start after a receive message\n");
598 ret = -EOPNOTSUPP;
599 goto out;
600 }
601 }
602 id->bus_hold_flag = 1;
603 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
604 reg |= CDNS_I2C_CR_HOLD;
605 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
606 } else {
607 id->bus_hold_flag = 0;
608 }
609
610 /* Process the msg one by one */
611 for (count = 0; count < num; count++, msgs++) {
612 if (count == (num - 1))
613 id->bus_hold_flag = 0;
614
615 ret = cdns_i2c_process_msg(id, msgs, adap);
616 if (ret)
617 goto out;
618
619 /* Report the other error interrupts to application */
620 if (id->err_status) {
621 cdns_i2c_master_reset(adap);
622
623 if (id->err_status & CDNS_I2C_IXR_NACK) {
624 ret = -ENXIO;
625 goto out;
626 }
627 ret = -EIO;
628 goto out;
629 }
630 }
631
632 ret = num;
633 out:
634 pm_runtime_mark_last_busy(id->dev);
635 pm_runtime_put_autosuspend(id->dev);
636 return ret;
637 }
638
639 /**
640 * cdns_i2c_func - Returns the supported features of the I2C driver
641 * @adap: pointer to the i2c adapter structure
642 *
643 * Return: 32 bit value, each bit corresponding to a feature
644 */
cdns_i2c_func(struct i2c_adapter * adap)645 static u32 cdns_i2c_func(struct i2c_adapter *adap)
646 {
647 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
648 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
649 I2C_FUNC_SMBUS_BLOCK_DATA;
650 }
651
652 static const struct i2c_algorithm cdns_i2c_algo = {
653 .master_xfer = cdns_i2c_master_xfer,
654 .functionality = cdns_i2c_func,
655 };
656
657 /**
658 * cdns_i2c_calc_divs - Calculate clock dividers
659 * @f: I2C clock frequency
660 * @input_clk: Input clock frequency
661 * @a: First divider (return value)
662 * @b: Second divider (return value)
663 *
664 * f is used as input and output variable. As input it is used as target I2C
665 * frequency. On function exit f holds the actually resulting I2C frequency.
666 *
667 * Return: 0 on success, negative errno otherwise.
668 */
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)669 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
670 unsigned int *a, unsigned int *b)
671 {
672 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
673 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
674 unsigned int last_error, current_error;
675
676 /* calculate (divisor_a+1) x (divisor_b+1) */
677 temp = input_clk / (22 * fscl);
678
679 /*
680 * If the calculated value is negative or 0, the fscl input is out of
681 * range. Return error.
682 */
683 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
684 return -EINVAL;
685
686 last_error = -1;
687 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
688 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
689
690 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
691 continue;
692 div_b--;
693
694 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
695
696 if (actual_fscl > fscl)
697 continue;
698
699 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
700 (fscl - actual_fscl));
701
702 if (last_error > current_error) {
703 calc_div_a = div_a;
704 calc_div_b = div_b;
705 best_fscl = actual_fscl;
706 last_error = current_error;
707 }
708 }
709
710 *a = calc_div_a;
711 *b = calc_div_b;
712 *f = best_fscl;
713
714 return 0;
715 }
716
717 /**
718 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
719 * @clk_in: I2C clock input frequency in Hz
720 * @id: Pointer to the I2C device structure
721 *
722 * The device must be idle rather than busy transferring data before setting
723 * these device options.
724 * The data rate is set by values in the control register.
725 * The formula for determining the correct register values is
726 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
727 * See the hardware data sheet for a full explanation of setting the serial
728 * clock rate. The clock can not be faster than the input clock divide by 22.
729 * The two most common clock rates are 100KHz and 400KHz.
730 *
731 * Return: 0 on success, negative error otherwise
732 */
cdns_i2c_setclk(unsigned long clk_in,struct cdns_i2c * id)733 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
734 {
735 unsigned int div_a, div_b;
736 unsigned int ctrl_reg;
737 int ret = 0;
738 unsigned long fscl = id->i2c_clk;
739
740 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
741 if (ret)
742 return ret;
743
744 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
745 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
746 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
747 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
748 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
749
750 return 0;
751 }
752
753 /**
754 * cdns_i2c_clk_notifier_cb - Clock rate change callback
755 * @nb: Pointer to notifier block
756 * @event: Notification reason
757 * @data: Pointer to notification data object
758 *
759 * This function is called when the cdns_i2c input clock frequency changes.
760 * The callback checks whether a valid bus frequency can be generated after the
761 * change. If so, the change is acknowledged, otherwise the change is aborted.
762 * New dividers are written to the HW in the pre- or post change notification
763 * depending on the scaling direction.
764 *
765 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
766 * to acknowledge the change, NOTIFY_DONE if the notification is
767 * considered irrelevant.
768 */
cdns_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)769 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
770 event, void *data)
771 {
772 struct clk_notifier_data *ndata = data;
773 struct cdns_i2c *id = to_cdns_i2c(nb);
774
775 if (pm_runtime_suspended(id->dev))
776 return NOTIFY_OK;
777
778 switch (event) {
779 case PRE_RATE_CHANGE:
780 {
781 unsigned long input_clk = ndata->new_rate;
782 unsigned long fscl = id->i2c_clk;
783 unsigned int div_a, div_b;
784 int ret;
785
786 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
787 if (ret) {
788 dev_warn(id->adap.dev.parent,
789 "clock rate change rejected\n");
790 return NOTIFY_STOP;
791 }
792
793 /* scale up */
794 if (ndata->new_rate > ndata->old_rate)
795 cdns_i2c_setclk(ndata->new_rate, id);
796
797 return NOTIFY_OK;
798 }
799 case POST_RATE_CHANGE:
800 id->input_clk = ndata->new_rate;
801 /* scale down */
802 if (ndata->new_rate < ndata->old_rate)
803 cdns_i2c_setclk(ndata->new_rate, id);
804 return NOTIFY_OK;
805 case ABORT_RATE_CHANGE:
806 /* scale up */
807 if (ndata->new_rate > ndata->old_rate)
808 cdns_i2c_setclk(ndata->old_rate, id);
809 return NOTIFY_OK;
810 default:
811 return NOTIFY_DONE;
812 }
813 }
814
815 /**
816 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
817 * @dev: Address of the platform_device structure
818 *
819 * Put the driver into low power mode.
820 *
821 * Return: 0 always
822 */
cdns_i2c_runtime_suspend(struct device * dev)823 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
824 {
825 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
826
827 clk_disable(xi2c->clk);
828
829 return 0;
830 }
831
832 /**
833 * cdns_i2c_runtime_resume - Runtime resume
834 * @dev: Address of the platform_device structure
835 *
836 * Runtime resume callback.
837 *
838 * Return: 0 on success and error value on error
839 */
cdns_i2c_runtime_resume(struct device * dev)840 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
841 {
842 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
843 int ret;
844
845 ret = clk_enable(xi2c->clk);
846 if (ret) {
847 dev_err(dev, "Cannot enable clock.\n");
848 return ret;
849 }
850
851 return 0;
852 }
853
854 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
855 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
856 cdns_i2c_runtime_resume, NULL)
857 };
858
859 static const struct cdns_platform_data r1p10_i2c_def = {
860 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
861 };
862
863 static const struct of_device_id cdns_i2c_of_match[] = {
864 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
865 { .compatible = "cdns,i2c-r1p14",},
866 { /* end of table */ }
867 };
868 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
869
870 /**
871 * cdns_i2c_probe - Platform registration call
872 * @pdev: Handle to the platform device structure
873 *
874 * This function does all the memory allocation and registration for the i2c
875 * device. User can modify the address mode to 10 bit address mode using the
876 * ioctl call with option I2C_TENBIT.
877 *
878 * Return: 0 on success, negative error otherwise
879 */
cdns_i2c_probe(struct platform_device * pdev)880 static int cdns_i2c_probe(struct platform_device *pdev)
881 {
882 struct resource *r_mem;
883 struct cdns_i2c *id;
884 int ret;
885 const struct of_device_id *match;
886
887 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
888 if (!id)
889 return -ENOMEM;
890
891 id->dev = &pdev->dev;
892 platform_set_drvdata(pdev, id);
893
894 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
895 if (match && match->data) {
896 const struct cdns_platform_data *data = match->data;
897 id->quirks = data->quirks;
898 }
899
900 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
902 if (IS_ERR(id->membase))
903 return PTR_ERR(id->membase);
904
905 ret = platform_get_irq(pdev, 0);
906 if (ret < 0)
907 return ret;
908 id->irq = ret;
909
910 id->adap.owner = THIS_MODULE;
911 id->adap.dev.of_node = pdev->dev.of_node;
912 id->adap.algo = &cdns_i2c_algo;
913 id->adap.timeout = CDNS_I2C_TIMEOUT;
914 id->adap.retries = 3; /* Default retry value. */
915 id->adap.algo_data = id;
916 id->adap.dev.parent = &pdev->dev;
917 init_completion(&id->xfer_done);
918 snprintf(id->adap.name, sizeof(id->adap.name),
919 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
920
921 id->clk = devm_clk_get(&pdev->dev, NULL);
922 if (IS_ERR(id->clk)) {
923 dev_err(&pdev->dev, "input clock not found.\n");
924 return PTR_ERR(id->clk);
925 }
926 ret = clk_prepare_enable(id->clk);
927 if (ret)
928 dev_err(&pdev->dev, "Unable to enable clock.\n");
929
930 pm_runtime_enable(id->dev);
931 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
932 pm_runtime_use_autosuspend(id->dev);
933 pm_runtime_set_active(id->dev);
934
935 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
936 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
937 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
938 id->input_clk = clk_get_rate(id->clk);
939
940 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
941 &id->i2c_clk);
942 if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
943 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
944
945 cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
946 CDNS_I2C_CR_OFFSET);
947
948 ret = cdns_i2c_setclk(id->input_clk, id);
949 if (ret) {
950 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
951 ret = -EINVAL;
952 goto err_clk_dis;
953 }
954
955 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
956 DRIVER_NAME, id);
957 if (ret) {
958 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
959 goto err_clk_dis;
960 }
961
962 /*
963 * Cadence I2C controller has a bug wherein it generates
964 * invalid read transaction after HW timeout in master receiver mode.
965 * HW timeout is not used by this driver and the interrupt is disabled.
966 * But the feature itself cannot be disabled. Hence maximum value
967 * is written to this register to reduce the chances of error.
968 */
969 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
970
971 ret = i2c_add_adapter(&id->adap);
972 if (ret < 0)
973 goto err_clk_dis;
974
975 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
976 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
977
978 return 0;
979
980 err_clk_dis:
981 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
982 clk_disable_unprepare(id->clk);
983 pm_runtime_set_suspended(&pdev->dev);
984 pm_runtime_disable(&pdev->dev);
985 return ret;
986 }
987
988 /**
989 * cdns_i2c_remove - Unregister the device after releasing the resources
990 * @pdev: Handle to the platform device structure
991 *
992 * This function frees all the resources allocated to the device.
993 *
994 * Return: 0 always
995 */
cdns_i2c_remove(struct platform_device * pdev)996 static int cdns_i2c_remove(struct platform_device *pdev)
997 {
998 struct cdns_i2c *id = platform_get_drvdata(pdev);
999
1000 i2c_del_adapter(&id->adap);
1001 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1002 clk_disable_unprepare(id->clk);
1003 pm_runtime_disable(&pdev->dev);
1004
1005 return 0;
1006 }
1007
1008 static struct platform_driver cdns_i2c_drv = {
1009 .driver = {
1010 .name = DRIVER_NAME,
1011 .of_match_table = cdns_i2c_of_match,
1012 .pm = &cdns_i2c_dev_pm_ops,
1013 },
1014 .probe = cdns_i2c_probe,
1015 .remove = cdns_i2c_remove,
1016 };
1017
1018 module_platform_driver(cdns_i2c_drv);
1019
1020 MODULE_AUTHOR("Xilinx Inc.");
1021 MODULE_DESCRIPTION("Cadence I2C bus driver");
1022 MODULE_LICENSE("GPL");
1023