1 /*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * SMBus host driver for PA Semi PWRficient
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/kernel.h>
19 #include <linux/stddef.h>
20 #include <linux/sched.h>
21 #include <linux/i2c.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/io.h>
25
26 static struct pci_driver pasemi_smb_driver;
27
28 struct pasemi_smbus {
29 struct pci_dev *dev;
30 struct i2c_adapter adapter;
31 unsigned long base;
32 int size;
33 };
34
35 /* Register offsets */
36 #define REG_MTXFIFO 0x00
37 #define REG_MRXFIFO 0x04
38 #define REG_SMSTA 0x14
39 #define REG_CTL 0x1c
40
41 /* Register defs */
42 #define MTXFIFO_READ 0x00000400
43 #define MTXFIFO_STOP 0x00000200
44 #define MTXFIFO_START 0x00000100
45 #define MTXFIFO_DATA_M 0x000000ff
46
47 #define MRXFIFO_EMPTY 0x00000100
48 #define MRXFIFO_DATA_M 0x000000ff
49
50 #define SMSTA_XEN 0x08000000
51 #define SMSTA_MTN 0x00200000
52
53 #define CTL_MRR 0x00000400
54 #define CTL_MTR 0x00000200
55 #define CTL_CLK_M 0x000000ff
56
57 #define CLK_100K_DIV 84
58 #define CLK_400K_DIV 21
59
reg_write(struct pasemi_smbus * smbus,int reg,int val)60 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
61 {
62 dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
63 smbus->base + reg, val);
64 outl(val, smbus->base + reg);
65 }
66
reg_read(struct pasemi_smbus * smbus,int reg)67 static inline int reg_read(struct pasemi_smbus *smbus, int reg)
68 {
69 int ret;
70 ret = inl(smbus->base + reg);
71 dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
72 smbus->base + reg, ret);
73 return ret;
74 }
75
76 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
77 #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
78
pasemi_smb_clear(struct pasemi_smbus * smbus)79 static void pasemi_smb_clear(struct pasemi_smbus *smbus)
80 {
81 unsigned int status;
82
83 status = reg_read(smbus, REG_SMSTA);
84 reg_write(smbus, REG_SMSTA, status);
85 }
86
pasemi_smb_waitready(struct pasemi_smbus * smbus)87 static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
88 {
89 int timeout = 10;
90 unsigned int status;
91
92 status = reg_read(smbus, REG_SMSTA);
93
94 while (!(status & SMSTA_XEN) && timeout--) {
95 msleep(1);
96 status = reg_read(smbus, REG_SMSTA);
97 }
98
99 /* Got NACK? */
100 if (status & SMSTA_MTN)
101 return -ENXIO;
102
103 if (timeout < 0) {
104 dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
105 reg_write(smbus, REG_SMSTA, status);
106 return -ETIME;
107 }
108
109 /* Clear XEN */
110 reg_write(smbus, REG_SMSTA, SMSTA_XEN);
111
112 return 0;
113 }
114
pasemi_i2c_xfer_msg(struct i2c_adapter * adapter,struct i2c_msg * msg,int stop)115 static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
116 struct i2c_msg *msg, int stop)
117 {
118 struct pasemi_smbus *smbus = adapter->algo_data;
119 int read, i, err;
120 u32 rd;
121
122 read = msg->flags & I2C_M_RD ? 1 : 0;
123
124 TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg));
125
126 if (read) {
127 TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
128 (stop ? MTXFIFO_STOP : 0));
129
130 err = pasemi_smb_waitready(smbus);
131 if (err)
132 goto reset_out;
133
134 for (i = 0; i < msg->len; i++) {
135 rd = RXFIFO_RD(smbus);
136 if (rd & MRXFIFO_EMPTY) {
137 err = -ENODATA;
138 goto reset_out;
139 }
140 msg->buf[i] = rd & MRXFIFO_DATA_M;
141 }
142 } else {
143 for (i = 0; i < msg->len - 1; i++)
144 TXFIFO_WR(smbus, msg->buf[i]);
145
146 TXFIFO_WR(smbus, msg->buf[msg->len-1] |
147 (stop ? MTXFIFO_STOP : 0));
148
149 if (stop) {
150 err = pasemi_smb_waitready(smbus);
151 if (err)
152 goto reset_out;
153 }
154 }
155
156 return 0;
157
158 reset_out:
159 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
160 (CLK_100K_DIV & CTL_CLK_M)));
161 return err;
162 }
163
pasemi_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)164 static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
165 struct i2c_msg *msgs, int num)
166 {
167 struct pasemi_smbus *smbus = adapter->algo_data;
168 int ret, i;
169
170 pasemi_smb_clear(smbus);
171
172 ret = 0;
173
174 for (i = 0; i < num && !ret; i++)
175 ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
176
177 return ret ? ret : num;
178 }
179
pasemi_smb_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)180 static int pasemi_smb_xfer(struct i2c_adapter *adapter,
181 u16 addr, unsigned short flags, char read_write, u8 command,
182 int size, union i2c_smbus_data *data)
183 {
184 struct pasemi_smbus *smbus = adapter->algo_data;
185 unsigned int rd;
186 int read_flag, err;
187 int len = 0, i;
188
189 /* All our ops take 8-bit shifted addresses */
190 addr <<= 1;
191 read_flag = read_write == I2C_SMBUS_READ;
192
193 pasemi_smb_clear(smbus);
194
195 switch (size) {
196 case I2C_SMBUS_QUICK:
197 TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
198 MTXFIFO_STOP);
199 break;
200 case I2C_SMBUS_BYTE:
201 TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
202 if (read_write)
203 TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
204 else
205 TXFIFO_WR(smbus, MTXFIFO_STOP | command);
206 break;
207 case I2C_SMBUS_BYTE_DATA:
208 TXFIFO_WR(smbus, addr | MTXFIFO_START);
209 TXFIFO_WR(smbus, command);
210 if (read_write) {
211 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
212 TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
213 } else {
214 TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
215 }
216 break;
217 case I2C_SMBUS_WORD_DATA:
218 TXFIFO_WR(smbus, addr | MTXFIFO_START);
219 TXFIFO_WR(smbus, command);
220 if (read_write) {
221 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
222 TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
223 } else {
224 TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
225 TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
226 }
227 break;
228 case I2C_SMBUS_BLOCK_DATA:
229 TXFIFO_WR(smbus, addr | MTXFIFO_START);
230 TXFIFO_WR(smbus, command);
231 if (read_write) {
232 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
233 TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
234 rd = RXFIFO_RD(smbus);
235 len = min_t(u8, (rd & MRXFIFO_DATA_M),
236 I2C_SMBUS_BLOCK_MAX);
237 TXFIFO_WR(smbus, len | MTXFIFO_READ |
238 MTXFIFO_STOP);
239 } else {
240 len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
241 TXFIFO_WR(smbus, len);
242 for (i = 1; i < len; i++)
243 TXFIFO_WR(smbus, data->block[i]);
244 TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
245 }
246 break;
247 case I2C_SMBUS_PROC_CALL:
248 read_write = I2C_SMBUS_READ;
249 TXFIFO_WR(smbus, addr | MTXFIFO_START);
250 TXFIFO_WR(smbus, command);
251 TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
252 TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
253 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
254 TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
255 break;
256 case I2C_SMBUS_BLOCK_PROC_CALL:
257 len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
258 read_write = I2C_SMBUS_READ;
259 TXFIFO_WR(smbus, addr | MTXFIFO_START);
260 TXFIFO_WR(smbus, command);
261 TXFIFO_WR(smbus, len);
262 for (i = 1; i <= len; i++)
263 TXFIFO_WR(smbus, data->block[i]);
264 TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
265 TXFIFO_WR(smbus, MTXFIFO_READ | 1);
266 rd = RXFIFO_RD(smbus);
267 len = min_t(u8, (rd & MRXFIFO_DATA_M),
268 I2C_SMBUS_BLOCK_MAX - len);
269 TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
270 break;
271
272 default:
273 dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
274 return -EINVAL;
275 }
276
277 err = pasemi_smb_waitready(smbus);
278 if (err)
279 goto reset_out;
280
281 if (read_write == I2C_SMBUS_WRITE)
282 return 0;
283
284 switch (size) {
285 case I2C_SMBUS_BYTE:
286 case I2C_SMBUS_BYTE_DATA:
287 rd = RXFIFO_RD(smbus);
288 if (rd & MRXFIFO_EMPTY) {
289 err = -ENODATA;
290 goto reset_out;
291 }
292 data->byte = rd & MRXFIFO_DATA_M;
293 break;
294 case I2C_SMBUS_WORD_DATA:
295 case I2C_SMBUS_PROC_CALL:
296 rd = RXFIFO_RD(smbus);
297 if (rd & MRXFIFO_EMPTY) {
298 err = -ENODATA;
299 goto reset_out;
300 }
301 data->word = rd & MRXFIFO_DATA_M;
302 rd = RXFIFO_RD(smbus);
303 if (rd & MRXFIFO_EMPTY) {
304 err = -ENODATA;
305 goto reset_out;
306 }
307 data->word |= (rd & MRXFIFO_DATA_M) << 8;
308 break;
309 case I2C_SMBUS_BLOCK_DATA:
310 case I2C_SMBUS_BLOCK_PROC_CALL:
311 data->block[0] = len;
312 for (i = 1; i <= len; i ++) {
313 rd = RXFIFO_RD(smbus);
314 if (rd & MRXFIFO_EMPTY) {
315 err = -ENODATA;
316 goto reset_out;
317 }
318 data->block[i] = rd & MRXFIFO_DATA_M;
319 }
320 break;
321 }
322
323 return 0;
324
325 reset_out:
326 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
327 (CLK_100K_DIV & CTL_CLK_M)));
328 return err;
329 }
330
pasemi_smb_func(struct i2c_adapter * adapter)331 static u32 pasemi_smb_func(struct i2c_adapter *adapter)
332 {
333 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
334 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
335 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
336 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
337 }
338
339 static const struct i2c_algorithm smbus_algorithm = {
340 .master_xfer = pasemi_i2c_xfer,
341 .smbus_xfer = pasemi_smb_xfer,
342 .functionality = pasemi_smb_func,
343 };
344
pasemi_smb_probe(struct pci_dev * dev,const struct pci_device_id * id)345 static int pasemi_smb_probe(struct pci_dev *dev,
346 const struct pci_device_id *id)
347 {
348 struct pasemi_smbus *smbus;
349 int error;
350
351 if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
352 return -ENODEV;
353
354 smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
355 if (!smbus)
356 return -ENOMEM;
357
358 smbus->dev = dev;
359 smbus->base = pci_resource_start(dev, 0);
360 smbus->size = pci_resource_len(dev, 0);
361
362 if (!request_region(smbus->base, smbus->size,
363 pasemi_smb_driver.name)) {
364 error = -EBUSY;
365 goto out_kfree;
366 }
367
368 smbus->adapter.owner = THIS_MODULE;
369 snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
370 "PA Semi SMBus adapter at 0x%lx", smbus->base);
371 smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
372 smbus->adapter.algo = &smbus_algorithm;
373 smbus->adapter.algo_data = smbus;
374
375 /* set up the sysfs linkage to our parent device */
376 smbus->adapter.dev.parent = &dev->dev;
377
378 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
379 (CLK_100K_DIV & CTL_CLK_M)));
380
381 error = i2c_add_adapter(&smbus->adapter);
382 if (error)
383 goto out_release_region;
384
385 pci_set_drvdata(dev, smbus);
386
387 return 0;
388
389 out_release_region:
390 release_region(smbus->base, smbus->size);
391 out_kfree:
392 kfree(smbus);
393 return error;
394 }
395
pasemi_smb_remove(struct pci_dev * dev)396 static void pasemi_smb_remove(struct pci_dev *dev)
397 {
398 struct pasemi_smbus *smbus = pci_get_drvdata(dev);
399
400 i2c_del_adapter(&smbus->adapter);
401 release_region(smbus->base, smbus->size);
402 kfree(smbus);
403 }
404
405 static const struct pci_device_id pasemi_smb_ids[] = {
406 { PCI_DEVICE(0x1959, 0xa003) },
407 { 0, }
408 };
409
410 MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
411
412 static struct pci_driver pasemi_smb_driver = {
413 .name = "i2c-pasemi",
414 .id_table = pasemi_smb_ids,
415 .probe = pasemi_smb_probe,
416 .remove = pasemi_smb_remove,
417 };
418
419 module_pci_driver(pasemi_smb_driver);
420
421 MODULE_LICENSE("GPL");
422 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
423 MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
424