1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_5332_RX_H_ 19 #define _HAL_5332_RX_H_ 20 #include "qdf_util.h" 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_nbuf.h" 25 #include "tcl_data_cmd.h" 26 #include "phyrx_rssi_legacy.h" 27 #include "rx_msdu_start.h" 28 #include "tlv_tag_def.h" 29 #include "hal_hw_headers.h" 30 #include "hal_internal.h" 31 #include "cdp_txrx_mon_struct.h" 32 #include "qdf_trace.h" 33 #include "hal_rx.h" 34 #include "hal_tx.h" 35 #include "dp_types.h" 36 #include "hal_api_mon.h" 37 #include "phyrx_other_receive_info_ru_details.h" 38 39 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 40 (uint8_t *)(link_desc_va) + \ 41 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 42 43 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 44 (uint8_t *)(msdu0) + \ 45 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 46 47 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 48 (uint8_t *)(ent_ring_desc) + \ 49 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 50 51 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 52 (uint8_t *)(dst_ring_desc) + \ 53 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 54 55 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 56 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 57 58 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 59 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 60 61 /* 62 * In Beryllium chipset msdu_start was removed and merged in msdu_end. 63 * Due to this valid contents will be present only in last msdu. 64 * After setting the 5th bit of spare control field, REO will copy the contents 65 * from last buffer to all the other buffers of MSDU. 66 */ 67 #define HAL_REO_MSDU_END_COPY 0x20 68 #define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 69 70 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 71 do { \ 72 reg_val &= \ 73 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 74 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 75 reg_val |= \ 76 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 77 AGING_LIST_ENABLE, 1) | \ 78 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 79 AGING_FLUSH_ENABLE, 1); \ 80 HAL_REG_WRITE(soc, \ 81 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 82 REO_REG_REG_BASE), \ 83 reg_val); \ 84 reg_val = HAL_REG_READ(soc, \ 85 HWIO_REO_R0_MISC_CTL_ADDR( \ 86 REO_REG_REG_BASE)); \ 87 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 88 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 89 FRAGMENT_DEST_RING, \ 90 (reo_params)->frag_dst_ring); \ 91 reg_val |= ((HAL_REO_MSDU_END_COPY) << \ 92 HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \ 93 HAL_REG_WRITE(soc, \ 94 HWIO_REO_R0_MISC_CTL_ADDR(REO_REG_REG_BASE), \ 95 reg_val); \ 96 } while (0) 97 98 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 99 ((struct rx_msdu_desc_info *) \ 100 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 101 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 102 103 #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ 104 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy 105 106 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 107 ((struct rx_msdu_details *) \ 108 _OFFSET_TO_BYTE_PTR((link_desc),\ 109 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 110 111 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 112 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006 113 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1 114 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2 115 116 #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \ 117 ((HAL_RX_GET((rx_tlv), \ 118 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \ 119 RTT_CFR_STATUS) & \ 120 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \ 121 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB) 122 #endif 123 #endif 124