1 /*
2 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include "hal_hw_headers.h"
19 #include "hal_internal.h"
20 #include "cdp_txrx_mon_struct.h"
21 #include "qdf_trace.h"
22 #include "hal_rx.h"
23 #include "hal_tx.h"
24 #include "dp_types.h"
25 #include "hal_api_mon.h"
26
27 /**
28 * hal_tx_desc_set_dscp_tid_table_id_6122() - Sets DSCP to TID conversion
29 * table ID
30 * @desc: Handle to Tx Descriptor
31 * @id: DSCP to tid conversion table to be used for this frame
32 *
33 * Return: void
34 */
hal_tx_desc_set_dscp_tid_table_id_6122(void * desc,uint8_t id)35 static void hal_tx_desc_set_dscp_tid_table_id_6122(void *desc, uint8_t id)
36 {
37 HAL_SET_FLD(desc, TCL_DATA_CMD_5,
38 DSCP_TID_TABLE_NUM) |=
39 HAL_TX_SM(TCL_DATA_CMD_5, DSCP_TID_TABLE_NUM, id);
40 }
41
42 #define DSCP_TID_TABLE_SIZE 24
43 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
44 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
45
46 /**
47 * hal_tx_set_dscp_tid_map_6122() - Configure default DSCP to TID map table
48 * @soc: HAL SoC context
49 * @map: DSCP-TID mapping table
50 * @id: mapping table ID - 0,1
51 *
52 * DSCP are mapped to 8 TID values using TID values programmed
53 * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
54 * and DSCP_TID2_MAP_<0 to 6> (id = 1)
55 * Each mapping register has TID mapping for 10 DSCP values
56 *
57 * Return: none
58 */
hal_tx_set_dscp_tid_map_6122(struct hal_soc * soc,uint8_t * map,uint8_t id)59 static void hal_tx_set_dscp_tid_map_6122(struct hal_soc *soc,
60 uint8_t *map, uint8_t id)
61 {
62 int i;
63 uint32_t addr, cmn_reg_addr;
64 uint32_t value = 0, regval;
65 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
66
67 if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
68 return;
69
70 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
71 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
72
73 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
74 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
75 id * NUM_WORDS_PER_DSCP_TID_TABLE);
76
77 /* Enable read/write access */
78 regval = HAL_REG_READ(soc, cmn_reg_addr);
79 regval |=
80 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
81
82 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
83
84 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */
85 for (i = 0; i < 64; i += 8) {
86 value = (map[i] |
87 (map[i + 1] << 0x3) |
88 (map[i + 2] << 0x6) |
89 (map[i + 3] << 0x9) |
90 (map[i + 4] << 0xc) |
91 (map[i + 5] << 0xf) |
92 (map[i + 6] << 0x12) |
93 (map[i + 7] << 0x15));
94
95 qdf_mem_copy(&val[cnt], &value, 3);
96 cnt += 3;
97 }
98
99 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
100 regval = *(uint32_t *)(val + i);
101 HAL_REG_WRITE(soc, addr,
102 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
103 addr += 4;
104 }
105
106 /* Disable read/write access */
107 regval = HAL_REG_READ(soc, cmn_reg_addr);
108 regval &=
109 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
110
111 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
112 }
113
114 /**
115 * hal_tx_update_dscp_tid_6122() - Update the dscp tid map table as
116 * updated by user
117 * @soc: HAL SoC context
118 * @tid: TID
119 * @id: MAP ID
120 * @dscp: DSCP
121 *
122 * Return: void
123 */
hal_tx_update_dscp_tid_6122(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)124 static void hal_tx_update_dscp_tid_6122(struct hal_soc *soc, uint8_t tid,
125 uint8_t id, uint8_t dscp)
126 {
127 uint32_t addr, addr1, cmn_reg_addr;
128 uint32_t start_value = 0, end_value = 0;
129 uint32_t regval;
130 uint8_t end_bits = 0;
131 uint8_t start_bits = 0;
132 uint32_t start_index, end_index;
133
134 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
135 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
136
137 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
138 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
139 id * NUM_WORDS_PER_DSCP_TID_TABLE);
140
141 start_index = dscp * HAL_TX_BITS_PER_TID;
142 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
143 % HAL_TX_NUM_DSCP_REGISTER_SIZE;
144 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
145 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
146 HAL_TX_NUM_DSCP_REGISTER_SIZE));
147
148 if (end_index < start_index) {
149 end_bits = end_index + 1;
150 start_bits = HAL_TX_BITS_PER_TID - end_bits;
151 start_value = tid << start_index;
152 end_value = tid >> start_bits;
153 addr1 = addr + 4;
154 } else {
155 start_bits = HAL_TX_BITS_PER_TID - end_bits;
156 start_value = tid << start_index;
157 addr1 = 0;
158 }
159
160 /* Enable read/write access */
161 regval = HAL_REG_READ(soc, cmn_reg_addr);
162 regval |=
163 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
164
165 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
166
167 regval = HAL_REG_READ(soc, addr);
168
169 if (end_index < start_index)
170 regval &= (~0) >> start_bits;
171 else
172 regval &= ~(7 << start_index);
173
174 regval |= start_value;
175
176 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
177
178 if (addr1) {
179 regval = HAL_REG_READ(soc, addr1);
180 regval &= (~0) << end_bits;
181 regval |= end_value;
182
183 HAL_REG_WRITE(soc, addr1, (regval &
184 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
185 }
186
187 /* Disable read/write access */
188 regval = HAL_REG_READ(soc, cmn_reg_addr);
189 regval &=
190 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
191 HAL_REG_WRITE(soc, cmn_reg_addr, regval);
192 }
193
194 /**
195 * hal_tx_desc_set_lmac_id_6122 - Set the lmac_id value
196 * @desc: Handle to Tx Descriptor
197 * @lmac_id: mac Id to ast matching
198 * b00 – mac 0
199 * b01 – mac 1
200 * b10 – mac 2
201 * b11 – all macs (legacy HK way)
202 *
203 * Return: void
204 */
hal_tx_desc_set_lmac_id_6122(void * desc,uint8_t lmac_id)205 static void hal_tx_desc_set_lmac_id_6122(void *desc, uint8_t lmac_id)
206 {
207 HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
208 HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
209 }
210
211 /**
212 * hal_tx_init_cmd_credit_ring_6122() - Initialize TCL command/credit SRNG
213 * @hal_soc_hdl: Handle to HAL SoC structure
214 * @hal_ring_hdl: Handle to HAL SRNG structure
215 *
216 * Return: none
217 */
218 static inline void
hal_tx_init_cmd_credit_ring_6122(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)219 hal_tx_init_cmd_credit_ring_6122(hal_soc_handle_t hal_soc_hdl,
220 hal_ring_handle_t hal_ring_hdl)
221 {
222 uint8_t *desc_addr;
223 struct hal_srng_params srng_params;
224 uint32_t desc_size;
225 uint32_t num_desc;
226
227 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
228
229 desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
230 desc_size = sizeof(struct tcl_data_cmd);
231 num_desc = srng_params.num_entries;
232
233 while (num_desc) {
234 /* using CMD/CREDIT Ring to send DATA CMD tag */
235 HAL_TX_DESC_SET_TLV_HDR(desc_addr, WIFITCL_DATA_CMD_E,
236 desc_size);
237 desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
238 num_desc--;
239 }
240 }
241