1 /* 2 * Copyright (c) 2015-2016, 2018-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __IF_PCI_INTERNAL_H__ 20 #define __IF_PCI_INTERNAL_H__ 21 22 #ifdef DISABLE_L1SS_STATES 23 #define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) \ 24 { \ 25 uint32_t lcr_val; \ 26 pfrm_read_config_dword(pdev, addr, &lcr_val); \ 27 pfrm_write_config_dword(pdev, addr, (lcr_val & ~0x0000000f)); \ 28 } 29 #else 30 #define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) 31 #endif 32 33 #ifdef QCA_WIFI_3_0 34 #define PCI_CLR_CAUSE0_REGISTER(sc) \ 35 { \ 36 uint32_t tmp_cause0; \ 37 tmp_cause0 = hif_read32_mb(sc, sc->mem + PCIE_INTR_CAUSE_ADDRESS); \ 38 hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, \ 39 PCIE_INTR_FIRMWARE_MASK | tmp_cause0); \ 40 hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \ 41 hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \ 42 hif_read32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS); \ 43 } 44 #else 45 #define PCI_CLR_CAUSE0_REGISTER(sc) 46 #endif 47 #endif /* __IF_PCI_INTERNAL_H__ */ 48