1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21 #ifndef __DMAR_H__
22 #define __DMAR_H__
23
24 #include <linux/acpi.h>
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/irqreturn.h>
28 #include <linux/rwsem.h>
29 #include <linux/rculist.h>
30
31 struct acpi_dmar_header;
32
33 #ifdef CONFIG_X86
34 # define DMAR_UNITS_SUPPORTED MAX_IO_APICS
35 #else
36 # define DMAR_UNITS_SUPPORTED 64
37 #endif
38
39 /* DMAR Flags */
40 #define DMAR_INTR_REMAP 0x1
41 #define DMAR_X2APIC_OPT_OUT 0x2
42
43 struct intel_iommu;
44
45 struct dmar_dev_scope {
46 struct device __rcu *dev;
47 u8 bus;
48 u8 devfn;
49 };
50
51 #ifdef CONFIG_DMAR_TABLE
52 extern struct acpi_table_header *dmar_tbl;
53 struct dmar_drhd_unit {
54 struct list_head list; /* list of drhd units */
55 struct acpi_dmar_header *hdr; /* ACPI header */
56 u64 reg_base_addr; /* register base address*/
57 struct dmar_dev_scope *devices;/* target device array */
58 int devices_cnt; /* target device count */
59 u16 segment; /* PCI domain */
60 u8 ignored:1; /* ignore drhd */
61 u8 include_all:1;
62 struct intel_iommu *iommu;
63 };
64
65 struct dmar_pci_path {
66 u8 bus;
67 u8 device;
68 u8 function;
69 };
70
71 struct dmar_pci_notify_info {
72 struct pci_dev *dev;
73 unsigned long event;
74 int bus;
75 u16 seg;
76 u16 level;
77 struct dmar_pci_path path[];
78 } __attribute__((packed));
79
80 extern struct rw_semaphore dmar_global_lock;
81 extern struct list_head dmar_drhd_units;
82
83 #define for_each_drhd_unit(drhd) \
84 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list)
85
86 #define for_each_active_drhd_unit(drhd) \
87 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
88 if (drhd->ignored) {} else
89
90 #define for_each_active_iommu(i, drhd) \
91 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
92 if (i=drhd->iommu, drhd->ignored) {} else
93
94 #define for_each_iommu(i, drhd) \
95 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list) \
96 if (i=drhd->iommu, 0) {} else
97
dmar_rcu_check(void)98 static inline bool dmar_rcu_check(void)
99 {
100 return rwsem_is_locked(&dmar_global_lock) ||
101 system_state == SYSTEM_BOOTING;
102 }
103
104 #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
105
106 #define for_each_dev_scope(a, c, p, d) \
107 for ((p) = 0; ((d) = (p) < (c) ? dmar_rcu_dereference((a)[(p)].dev) : \
108 NULL, (p) < (c)); (p)++)
109
110 #define for_each_active_dev_scope(a, c, p, d) \
111 for_each_dev_scope((a), (c), (p), (d)) if (!(d)) { continue; } else
112
113 extern int dmar_table_init(void);
114 extern int dmar_dev_scope_init(void);
115 extern void dmar_register_bus_notifier(void);
116 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
117 struct dmar_dev_scope **devices, u16 segment);
118 extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
119 extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
120 extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
121 void *start, void*end, u16 segment,
122 struct dmar_dev_scope *devices,
123 int devices_cnt);
124 extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
125 u16 segment, struct dmar_dev_scope *devices,
126 int count);
127 /* Intel IOMMU detection */
128 extern int detect_intel_iommu(void);
129 extern int enable_drhd_fault_handling(void);
130 extern int dmar_device_add(acpi_handle handle);
131 extern int dmar_device_remove(acpi_handle handle);
132
dmar_res_noop(struct acpi_dmar_header * hdr,void * arg)133 static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
134 {
135 return 0;
136 }
137
138 #ifdef CONFIG_INTEL_IOMMU
139 extern int iommu_detected, no_iommu;
140 extern int intel_iommu_init(void);
141 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
142 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
143 extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
144 extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg);
145 extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
146 extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
147 #else /* !CONFIG_INTEL_IOMMU: */
intel_iommu_init(void)148 static inline int intel_iommu_init(void) { return -ENODEV; }
149
150 #define dmar_parse_one_rmrr dmar_res_noop
151 #define dmar_parse_one_atsr dmar_res_noop
152 #define dmar_check_one_atsr dmar_res_noop
153 #define dmar_release_one_atsr dmar_res_noop
154
dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info * info)155 static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
156 {
157 return 0;
158 }
159
dmar_iommu_hotplug(struct dmar_drhd_unit * dmaru,bool insert)160 static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
161 {
162 return 0;
163 }
164 #endif /* CONFIG_INTEL_IOMMU */
165
166 #ifdef CONFIG_IRQ_REMAP
167 extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
168 #else /* CONFIG_IRQ_REMAP */
dmar_ir_hotplug(struct dmar_drhd_unit * dmaru,bool insert)169 static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
170 { return 0; }
171 #endif /* CONFIG_IRQ_REMAP */
172
173 #else /* CONFIG_DMAR_TABLE */
174
dmar_device_add(void * handle)175 static inline int dmar_device_add(void *handle)
176 {
177 return 0;
178 }
179
dmar_device_remove(void * handle)180 static inline int dmar_device_remove(void *handle)
181 {
182 return 0;
183 }
184
185 #endif /* CONFIG_DMAR_TABLE */
186
187 struct irte {
188 union {
189 /* Shared between remapped and posted mode*/
190 struct {
191 __u64 present : 1, /* 0 */
192 fpd : 1, /* 1 */
193 __res0 : 6, /* 2 - 6 */
194 avail : 4, /* 8 - 11 */
195 __res1 : 3, /* 12 - 14 */
196 pst : 1, /* 15 */
197 vector : 8, /* 16 - 23 */
198 __res2 : 40; /* 24 - 63 */
199 };
200
201 /* Remapped mode */
202 struct {
203 __u64 r_present : 1, /* 0 */
204 r_fpd : 1, /* 1 */
205 dst_mode : 1, /* 2 */
206 redir_hint : 1, /* 3 */
207 trigger_mode : 1, /* 4 */
208 dlvry_mode : 3, /* 5 - 7 */
209 r_avail : 4, /* 8 - 11 */
210 r_res0 : 4, /* 12 - 15 */
211 r_vector : 8, /* 16 - 23 */
212 r_res1 : 8, /* 24 - 31 */
213 dest_id : 32; /* 32 - 63 */
214 };
215
216 /* Posted mode */
217 struct {
218 __u64 p_present : 1, /* 0 */
219 p_fpd : 1, /* 1 */
220 p_res0 : 6, /* 2 - 7 */
221 p_avail : 4, /* 8 - 11 */
222 p_res1 : 2, /* 12 - 13 */
223 p_urgent : 1, /* 14 */
224 p_pst : 1, /* 15 */
225 p_vector : 8, /* 16 - 23 */
226 p_res2 : 14, /* 24 - 37 */
227 pda_l : 26; /* 38 - 63 */
228 };
229 __u64 low;
230 };
231
232 union {
233 /* Shared between remapped and posted mode*/
234 struct {
235 __u64 sid : 16, /* 64 - 79 */
236 sq : 2, /* 80 - 81 */
237 svt : 2, /* 82 - 83 */
238 __res3 : 44; /* 84 - 127 */
239 };
240
241 /* Posted mode*/
242 struct {
243 __u64 p_sid : 16, /* 64 - 79 */
244 p_sq : 2, /* 80 - 81 */
245 p_svt : 2, /* 82 - 83 */
246 p_res3 : 12, /* 84 - 95 */
247 pda_h : 32; /* 96 - 127 */
248 };
249 __u64 high;
250 };
251 };
252
dmar_copy_shared_irte(struct irte * dst,struct irte * src)253 static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
254 {
255 dst->present = src->present;
256 dst->fpd = src->fpd;
257 dst->avail = src->avail;
258 dst->pst = src->pst;
259 dst->vector = src->vector;
260 dst->sid = src->sid;
261 dst->sq = src->sq;
262 dst->svt = src->svt;
263 }
264
265 #define PDA_LOW_BIT 26
266 #define PDA_HIGH_BIT 32
267
268 /* Can't use the common MSI interrupt functions
269 * since DMAR is not a pci device
270 */
271 struct irq_data;
272 extern void dmar_msi_unmask(struct irq_data *data);
273 extern void dmar_msi_mask(struct irq_data *data);
274 extern void dmar_msi_read(int irq, struct msi_msg *msg);
275 extern void dmar_msi_write(int irq, struct msi_msg *msg);
276 extern int dmar_set_interrupt(struct intel_iommu *iommu);
277 extern irqreturn_t dmar_fault(int irq, void *dev_id);
278 extern int dmar_alloc_hwirq(int id, int node, void *arg);
279 extern void dmar_free_hwirq(int irq);
280
281 #endif /* __DMAR_H__ */
282