1 /*
2 * TI AEMIF driver
3 *
4 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Authors:
7 * Murali Karicheri <m-karicheri2@ti.com>
8 * Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/ti-aemif.h>
24
25 #define TA_SHIFT 2
26 #define RHOLD_SHIFT 4
27 #define RSTROBE_SHIFT 7
28 #define RSETUP_SHIFT 13
29 #define WHOLD_SHIFT 17
30 #define WSTROBE_SHIFT 20
31 #define WSETUP_SHIFT 26
32 #define EW_SHIFT 30
33 #define SS_SHIFT 31
34
35 #define TA(x) ((x) << TA_SHIFT)
36 #define RHOLD(x) ((x) << RHOLD_SHIFT)
37 #define RSTROBE(x) ((x) << RSTROBE_SHIFT)
38 #define RSETUP(x) ((x) << RSETUP_SHIFT)
39 #define WHOLD(x) ((x) << WHOLD_SHIFT)
40 #define WSTROBE(x) ((x) << WSTROBE_SHIFT)
41 #define WSETUP(x) ((x) << WSETUP_SHIFT)
42 #define EW(x) ((x) << EW_SHIFT)
43 #define SS(x) ((x) << SS_SHIFT)
44
45 #define ASIZE_MAX 0x1
46 #define TA_MAX 0x3
47 #define RHOLD_MAX 0x7
48 #define RSTROBE_MAX 0x3f
49 #define RSETUP_MAX 0xf
50 #define WHOLD_MAX 0x7
51 #define WSTROBE_MAX 0x3f
52 #define WSETUP_MAX 0xf
53 #define EW_MAX 0x1
54 #define SS_MAX 0x1
55 #define NUM_CS 4
56
57 #define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
58 #define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
59 #define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
60 #define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
61 #define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
62 #define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
63 #define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
64 #define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
65 #define SS_VAL(x) (((x) & SS(SS_MAX)) >> SS_SHIFT)
66
67 #define NRCSR_OFFSET 0x00
68 #define AWCCR_OFFSET 0x04
69 #define A1CR_OFFSET 0x10
70
71 #define ACR_ASIZE_MASK 0x3
72 #define ACR_EW_MASK BIT(30)
73 #define ACR_SS_MASK BIT(31)
74 #define ASIZE_16BIT 1
75
76 #define CONFIG_MASK (TA(TA_MAX) | \
77 RHOLD(RHOLD_MAX) | \
78 RSTROBE(RSTROBE_MAX) | \
79 RSETUP(RSETUP_MAX) | \
80 WHOLD(WHOLD_MAX) | \
81 WSTROBE(WSTROBE_MAX) | \
82 WSETUP(WSETUP_MAX) | \
83 EW(EW_MAX) | SS(SS_MAX) | \
84 ASIZE_MAX)
85
86 /**
87 * struct aemif_cs_data: structure to hold cs parameters
88 * @cs: chip-select number
89 * @wstrobe: write strobe width, ns
90 * @rstrobe: read strobe width, ns
91 * @wsetup: write setup width, ns
92 * @whold: write hold width, ns
93 * @rsetup: read setup width, ns
94 * @rhold: read hold width, ns
95 * @ta: minimum turn around time, ns
96 * @enable_ss: enable/disable select strobe mode
97 * @enable_ew: enable/disable extended wait mode
98 * @asize: width of the asynchronous device's data bus
99 */
100 struct aemif_cs_data {
101 u8 cs;
102 u16 wstrobe;
103 u16 rstrobe;
104 u8 wsetup;
105 u8 whold;
106 u8 rsetup;
107 u8 rhold;
108 u8 ta;
109 u8 enable_ss;
110 u8 enable_ew;
111 u8 asize;
112 };
113
114 /**
115 * struct aemif_device: structure to hold device data
116 * @base: base address of AEMIF registers
117 * @clk: source clock
118 * @clk_rate: clock's rate in kHz
119 * @num_cs: number of assigned chip-selects
120 * @cs_offset: start number of cs nodes
121 * @cs_data: array of chip-select settings
122 */
123 struct aemif_device {
124 void __iomem *base;
125 struct clk *clk;
126 unsigned long clk_rate;
127 u8 num_cs;
128 int cs_offset;
129 struct aemif_cs_data cs_data[NUM_CS];
130 };
131
132 /**
133 * aemif_calc_rate - calculate timing data.
134 * @pdev: platform device to calculate for
135 * @wanted: The cycle time needed in nanoseconds.
136 * @clk: The input clock rate in kHz.
137 * @max: The maximum divider value that can be programmed.
138 *
139 * On success, returns the calculated timing value minus 1 for easy
140 * programming into AEMIF timing registers, else negative errno.
141 */
aemif_calc_rate(struct platform_device * pdev,int wanted,unsigned long clk,int max)142 static int aemif_calc_rate(struct platform_device *pdev, int wanted,
143 unsigned long clk, int max)
144 {
145 int result;
146
147 result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
148
149 dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
150 clk, wanted);
151
152 /* It is generally OK to have a more relaxed timing than requested... */
153 if (result < 0)
154 result = 0;
155
156 /* ... But configuring tighter timings is not an option. */
157 else if (result > max)
158 result = -EINVAL;
159
160 return result;
161 }
162
163 /**
164 * aemif_config_abus - configure async bus parameters
165 * @pdev: platform device to configure for
166 * @csnum: aemif chip select number
167 *
168 * This function programs the given timing values (in real clock) into the
169 * AEMIF registers taking the AEMIF clock into account.
170 *
171 * This function does not use any locking while programming the AEMIF
172 * because it is expected that there is only one user of a given
173 * chip-select.
174 *
175 * Returns 0 on success, else negative errno.
176 */
aemif_config_abus(struct platform_device * pdev,int csnum)177 static int aemif_config_abus(struct platform_device *pdev, int csnum)
178 {
179 struct aemif_device *aemif = platform_get_drvdata(pdev);
180 struct aemif_cs_data *data = &aemif->cs_data[csnum];
181 int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
182 unsigned long clk_rate = aemif->clk_rate;
183 unsigned offset;
184 u32 set, val;
185
186 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
187
188 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
189 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
190 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
191 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
192 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
193 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
194 wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
195
196 if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
197 whold < 0 || wstrobe < 0 || wsetup < 0) {
198 dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
199 __func__);
200 return -EINVAL;
201 }
202
203 set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
204 WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
205
206 set |= (data->asize & ACR_ASIZE_MASK);
207 if (data->enable_ew)
208 set |= ACR_EW_MASK;
209 if (data->enable_ss)
210 set |= ACR_SS_MASK;
211
212 val = readl(aemif->base + offset);
213 val &= ~CONFIG_MASK;
214 val |= set;
215 writel(val, aemif->base + offset);
216
217 return 0;
218 }
219
aemif_cycles_to_nsec(int val,unsigned long clk_rate)220 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
221 {
222 return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
223 }
224
225 /**
226 * aemif_get_hw_params - function to read hw register values
227 * @pdev: platform device to read for
228 * @csnum: aemif chip select number
229 *
230 * This function reads the defaults from the registers and update
231 * the timing values. Required for get/set commands and also for
232 * the case when driver needs to use defaults in hardware.
233 */
aemif_get_hw_params(struct platform_device * pdev,int csnum)234 static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
235 {
236 struct aemif_device *aemif = platform_get_drvdata(pdev);
237 struct aemif_cs_data *data = &aemif->cs_data[csnum];
238 unsigned long clk_rate = aemif->clk_rate;
239 u32 val, offset;
240
241 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
242 val = readl(aemif->base + offset);
243
244 data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
245 data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
246 data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
247 data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
248 data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
249 data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
250 data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
251 data->enable_ew = EW_VAL(val);
252 data->enable_ss = SS_VAL(val);
253 data->asize = val & ASIZE_MAX;
254 }
255
256 /**
257 * of_aemif_parse_abus_config - parse CS configuration from DT
258 * @pdev: platform device to parse for
259 * @np: device node ptr
260 *
261 * This function update the emif async bus configuration based on the values
262 * configured in a cs device binding node.
263 */
of_aemif_parse_abus_config(struct platform_device * pdev,struct device_node * np)264 static int of_aemif_parse_abus_config(struct platform_device *pdev,
265 struct device_node *np)
266 {
267 struct aemif_device *aemif = platform_get_drvdata(pdev);
268 struct aemif_cs_data *data;
269 u32 cs;
270 u32 val;
271
272 if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
273 dev_dbg(&pdev->dev, "cs property is required");
274 return -EINVAL;
275 }
276
277 if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
278 dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
279 return -EINVAL;
280 }
281
282 if (aemif->num_cs >= NUM_CS) {
283 dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
284 return -EINVAL;
285 }
286
287 data = &aemif->cs_data[aemif->num_cs];
288 data->cs = cs;
289
290 /* read the current value in the hw register */
291 aemif_get_hw_params(pdev, aemif->num_cs++);
292
293 /* override the values from device node */
294 if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
295 data->ta = val;
296
297 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
298 data->rhold = val;
299
300 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
301 data->rstrobe = val;
302
303 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
304 data->rsetup = val;
305
306 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
307 data->whold = val;
308
309 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
310 data->wstrobe = val;
311
312 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
313 data->wsetup = val;
314
315 if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
316 if (val == 16)
317 data->asize = 1;
318 data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
319 data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
320 return 0;
321 }
322
323 static const struct of_device_id aemif_of_match[] = {
324 { .compatible = "ti,davinci-aemif", },
325 { .compatible = "ti,da850-aemif", },
326 {},
327 };
328 MODULE_DEVICE_TABLE(of, aemif_of_match);
329
aemif_probe(struct platform_device * pdev)330 static int aemif_probe(struct platform_device *pdev)
331 {
332 int i;
333 int ret = -ENODEV;
334 struct resource *res;
335 struct device *dev = &pdev->dev;
336 struct device_node *np = dev->of_node;
337 struct device_node *child_np;
338 struct aemif_device *aemif;
339 struct aemif_platform_data *pdata;
340 struct of_dev_auxdata *dev_lookup;
341
342 aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
343 if (!aemif)
344 return -ENOMEM;
345
346 pdata = dev_get_platdata(&pdev->dev);
347 dev_lookup = pdata ? pdata->dev_lookup : NULL;
348
349 platform_set_drvdata(pdev, aemif);
350
351 aemif->clk = devm_clk_get(dev, NULL);
352 if (IS_ERR(aemif->clk)) {
353 dev_err(dev, "cannot get clock 'aemif'\n");
354 return PTR_ERR(aemif->clk);
355 }
356
357 ret = clk_prepare_enable(aemif->clk);
358 if (ret)
359 return ret;
360
361 aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
362
363 if (np && of_device_is_compatible(np, "ti,da850-aemif"))
364 aemif->cs_offset = 2;
365 else if (pdata)
366 aemif->cs_offset = pdata->cs_offset;
367
368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369 aemif->base = devm_ioremap_resource(dev, res);
370 if (IS_ERR(aemif->base)) {
371 ret = PTR_ERR(aemif->base);
372 goto error;
373 }
374
375 if (np) {
376 /*
377 * For every controller device node, there is a cs device node
378 * that describe the bus configuration parameters. This
379 * functions iterate over these nodes and update the cs data
380 * array.
381 */
382 for_each_available_child_of_node(np, child_np) {
383 ret = of_aemif_parse_abus_config(pdev, child_np);
384 if (ret < 0) {
385 of_node_put(child_np);
386 goto error;
387 }
388 }
389 } else if (pdata && pdata->num_abus_data > 0) {
390 for (i = 0; i < pdata->num_abus_data; i++, aemif->num_cs++) {
391 aemif->cs_data[i].cs = pdata->abus_data[i].cs;
392 aemif_get_hw_params(pdev, i);
393 }
394 }
395
396 for (i = 0; i < aemif->num_cs; i++) {
397 ret = aemif_config_abus(pdev, i);
398 if (ret < 0) {
399 dev_err(dev, "Error configuring chip select %d\n",
400 aemif->cs_data[i].cs);
401 goto error;
402 }
403 }
404
405 /*
406 * Create a child devices explicitly from here to guarantee that the
407 * child will be probed after the AEMIF timing parameters are set.
408 */
409 if (np) {
410 for_each_available_child_of_node(np, child_np) {
411 ret = of_platform_populate(child_np, NULL,
412 dev_lookup, dev);
413 if (ret < 0) {
414 of_node_put(child_np);
415 goto error;
416 }
417 }
418 } else if (pdata) {
419 for (i = 0; i < pdata->num_sub_devices; i++) {
420 pdata->sub_devices[i].dev.parent = dev;
421 ret = platform_device_register(&pdata->sub_devices[i]);
422 if (ret) {
423 dev_warn(dev, "Error register sub device %s\n",
424 pdata->sub_devices[i].name);
425 }
426 }
427 }
428
429 return 0;
430 error:
431 clk_disable_unprepare(aemif->clk);
432 return ret;
433 }
434
aemif_remove(struct platform_device * pdev)435 static int aemif_remove(struct platform_device *pdev)
436 {
437 struct aemif_device *aemif = platform_get_drvdata(pdev);
438
439 clk_disable_unprepare(aemif->clk);
440 return 0;
441 }
442
443 static struct platform_driver aemif_driver = {
444 .probe = aemif_probe,
445 .remove = aemif_remove,
446 .driver = {
447 .name = "ti-aemif",
448 .of_match_table = of_match_ptr(aemif_of_match),
449 },
450 };
451
452 module_platform_driver(aemif_driver);
453
454 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
455 MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
456 MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
457 MODULE_LICENSE("GPL v2");
458 MODULE_ALIAS("platform:" KBUILD_MODNAME);
459