1 /* 2 * drx3973d_map_firm.h 3 * 4 * Copyright (C) 2006-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #ifndef __DRX3973D_MAP__H__ 21 #define __DRX3973D_MAP__H__ 22 23 /* 24 * Note: originally, this file contained 12000+ lines of data 25 * Probably a few lines for every firwmare assembler instruction. However, 26 * only a few defines were actually used. So, removed all uneeded lines. 27 * If ever needed, the other lines can be easily obtained via git history. 28 */ 29 30 #define HI_COMM_EXEC__A 0x400000 31 #define HI_COMM_MB__A 0x400002 32 #define HI_CT_REG_COMM_STATE__A 0x410001 33 #define HI_RA_RAM_SRV_RES__A 0x420031 34 #define HI_RA_RAM_SRV_CMD__A 0x420032 35 #define HI_RA_RAM_SRV_CMD_RESET 0x2 36 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 37 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 38 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 39 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 40 #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 41 #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 42 #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 43 #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 44 #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 45 #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 46 #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 47 #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 48 #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 49 #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 50 #define HI_RA_RAM_USR_BEGIN__A 0x420040 51 #define HI_IF_RAM_TRP_BPT0__AX 0x430000 52 #define HI_IF_RAM_USR_BEGIN__A 0x430200 53 #define SC_COMM_EXEC__A 0x800000 54 #define SC_COMM_EXEC_CTL_STOP 0x0 55 #define SC_COMM_STATE__A 0x800001 56 #define SC_RA_RAM_PARAM0__A 0x820040 57 #define SC_RA_RAM_PARAM1__A 0x820041 58 #define SC_RA_RAM_CMD_ADDR__A 0x820042 59 #define SC_RA_RAM_CMD__A 0x820043 60 #define SC_RA_RAM_CMD_PROC_START 0x1 61 #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 62 #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 63 #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 64 #define SC_RA_RAM_LOCKTRACK_MIN 0x1 65 #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 66 #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 67 #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 68 #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 69 #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 70 #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC 71 #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 72 #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 73 #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 74 #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 75 #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 76 #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 77 #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 78 #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 79 #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 80 #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 81 #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 82 #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 83 #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 84 #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 85 #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 86 #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 87 #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 88 #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 89 #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 90 #define SC_RA_RAM_LOCK__A 0x82004B 91 #define SC_RA_RAM_LOCK_DEMOD__M 0x1 92 #define SC_RA_RAM_LOCK_FEC__M 0x2 93 #define SC_RA_RAM_LOCK_MPEG__M 0x4 94 #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C 95 #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 96 #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 97 #define SC_RA_RAM_CONFIG__A 0x820050 98 #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 99 #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 100 #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 101 #define SC_RA_RAM_IF_SAVE__AX 0x82008E 102 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 103 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 104 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 105 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 106 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 107 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 108 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 109 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 110 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 111 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 112 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 113 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 114 #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 115 #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 116 #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 117 #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 118 #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 119 #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 120 #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 121 #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 122 #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 123 #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 124 #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 125 #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 126 #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 127 #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 128 #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 129 #define SC_RA_RAM_BAND__A 0x8200EC 130 #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 131 #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F 132 #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 133 #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F 134 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 135 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 136 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB 137 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 138 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF 139 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 140 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E 141 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 142 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A 143 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 144 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB 145 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 146 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F 147 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 148 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 149 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 150 #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 151 #define SC_RA_RAM_PROC_LOCKTRACK 0x0 152 #define FE_COMM_EXEC__A 0xC00000 153 #define FE_AD_REG_COMM_EXEC__A 0xC10000 154 #define FE_AD_REG_FDB_IN__A 0xC10012 155 #define FE_AD_REG_PD__A 0xC10013 156 #define FE_AD_REG_INVEXT__A 0xC10014 157 #define FE_AD_REG_CLKNEG__A 0xC10015 158 #define FE_AG_REG_COMM_EXEC__A 0xC20000 159 #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 160 #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 161 #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 162 #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 163 #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 164 #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 165 #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 166 #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 167 #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 168 #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 169 #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 170 #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 171 #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 172 #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 173 #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 174 #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 175 #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 176 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 177 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 178 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 179 #define FE_AG_REG_AG_PWD__A 0xC20015 180 #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 181 #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 182 #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 183 #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 184 #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 185 #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 186 #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 187 #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 188 #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 189 #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 190 #define FE_AG_REG_EGC_SET_LVL__M 0x1FF 191 #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 192 #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 193 #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 194 #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 195 #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 196 #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B 197 #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 198 #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D 199 #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 200 #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 201 #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF 202 #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 203 #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 204 #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 205 #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 206 #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 207 #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF 208 #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 209 #define FE_AG_REG_IND_WIN__A 0xC2003C 210 #define FE_AG_REG_IND_THD_LOL__A 0xC2003D 211 #define FE_AG_REG_IND_THD_HIL__A 0xC2003E 212 #define FE_AG_REG_IND_DEL__A 0xC2003F 213 #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 214 #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 215 #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 216 #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 217 #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 218 #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 219 #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 220 #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 221 #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 222 #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 223 #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 224 #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 225 #define FE_AG_REG_PDC_MAX__A 0xC2004C 226 #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 227 #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 228 #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 229 #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 230 #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 231 #define FE_AG_REG_TGC_SET_LVL__M 0x3F 232 #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 233 #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 234 #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 235 #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 236 #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 237 #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 238 #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 239 #define FE_AG_REG_FGM_WRI__A 0xC20061 240 #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 241 #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 242 #define FE_FS_REG_COMM_EXEC__A 0xC30000 243 #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 244 #define FE_FD_REG_COMM_EXEC__A 0xC40000 245 #define FE_FD_REG_SCL__A 0xC40010 246 #define FE_FD_REG_MAX_LEV__A 0xC40011 247 #define FE_FD_REG_NR__A 0xC40012 248 #define FE_FD_REG_MEAS_VAL__A 0xC40014 249 #define FE_IF_REG_COMM_EXEC__A 0xC50000 250 #define FE_IF_REG_INCR0__A 0xC50010 251 #define FE_IF_REG_INCR0__W 16 252 #define FE_IF_REG_INCR0__M 0xFFFF 253 #define FE_IF_REG_INCR1__A 0xC50011 254 #define FE_IF_REG_INCR1__M 0xFF 255 #define FE_CF_REG_COMM_EXEC__A 0xC60000 256 #define FE_CF_REG_SCL__A 0xC60010 257 #define FE_CF_REG_MAX_LEV__A 0xC60011 258 #define FE_CF_REG_NR__A 0xC60012 259 #define FE_CF_REG_IMP_VAL__A 0xC60013 260 #define FE_CF_REG_MEAS_VAL__A 0xC60014 261 #define FE_CU_REG_COMM_EXEC__A 0xC70000 262 #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 263 #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 264 #define FT_COMM_EXEC__A 0x1000000 265 #define FT_REG_COMM_EXEC__A 0x1010000 266 #define CP_COMM_EXEC__A 0x1400000 267 #define CP_REG_COMM_EXEC__A 0x1410000 268 #define CP_REG_INTERVAL__A 0x1410011 269 #define CP_REG_BR_SPL_OFFSET__A 0x1410023 270 #define CP_REG_BR_STR_DEL__A 0x1410024 271 #define CP_REG_RT_ANG_INC0__A 0x1410030 272 #define CP_REG_RT_ANG_INC1__A 0x1410031 273 #define CP_REG_RT_DETECT_ENA__A 0x1410032 274 #define CP_REG_RT_DETECT_TRH__A 0x1410033 275 #define CP_REG_RT_EXP_MARG__A 0x141003E 276 #define CP_REG_AC_NEXP_OFFS__A 0x1410040 277 #define CP_REG_AC_AVER_POW__A 0x1410041 278 #define CP_REG_AC_MAX_POW__A 0x1410042 279 #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 280 #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 281 #define CP_REG_AC_AMP_MODE__A 0x1410047 282 #define CP_REG_AC_AMP_FIX__A 0x1410048 283 #define CP_REG_AC_ANG_MODE__A 0x141004A 284 #define CE_COMM_EXEC__A 0x1800000 285 #define CE_REG_COMM_EXEC__A 0x1810000 286 #define CE_REG_TAPSET__A 0x1810011 287 #define CE_REG_AVG_POW__A 0x1810012 288 #define CE_REG_MAX_POW__A 0x1810013 289 #define CE_REG_ATT__A 0x1810014 290 #define CE_REG_NRED__A 0x1810015 291 #define CE_REG_NE_ERR_SELECT__A 0x1810043 292 #define CE_REG_NE_TD_CAL__A 0x1810044 293 #define CE_REG_NE_MIXAVG__A 0x1810046 294 #define CE_REG_NE_NUPD_OFS__A 0x1810047 295 #define CE_REG_PE_NEXP_OFFS__A 0x1810050 296 #define CE_REG_PE_TIMESHIFT__A 0x1810051 297 #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 298 #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 299 #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 300 #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 301 #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 302 #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 303 #define CE_REG_TI_NEXP_OFFS__A 0x1810070 304 #define CE_REG_FI_SHT_INCR__A 0x1810090 305 #define CE_REG_FI_EXP_NORM__A 0x1810091 306 #define CE_REG_IR_INPUTSEL__A 0x18100A0 307 #define CE_REG_IR_STARTPOS__A 0x18100A1 308 #define CE_REG_IR_NEXP_THRES__A 0x18100A2 309 #define CE_REG_FR_TREAL00__A 0x1820010 310 #define CE_REG_FR_TIMAG00__A 0x1820011 311 #define CE_REG_FR_TREAL01__A 0x1820012 312 #define CE_REG_FR_TIMAG01__A 0x1820013 313 #define CE_REG_FR_TREAL02__A 0x1820014 314 #define CE_REG_FR_TIMAG02__A 0x1820015 315 #define CE_REG_FR_TREAL03__A 0x1820016 316 #define CE_REG_FR_TIMAG03__A 0x1820017 317 #define CE_REG_FR_TREAL04__A 0x1820018 318 #define CE_REG_FR_TIMAG04__A 0x1820019 319 #define CE_REG_FR_TREAL05__A 0x182001A 320 #define CE_REG_FR_TIMAG05__A 0x182001B 321 #define CE_REG_FR_TREAL06__A 0x182001C 322 #define CE_REG_FR_TIMAG06__A 0x182001D 323 #define CE_REG_FR_TREAL07__A 0x182001E 324 #define CE_REG_FR_TIMAG07__A 0x182001F 325 #define CE_REG_FR_TREAL08__A 0x1820020 326 #define CE_REG_FR_TIMAG08__A 0x1820021 327 #define CE_REG_FR_TREAL09__A 0x1820022 328 #define CE_REG_FR_TIMAG09__A 0x1820023 329 #define CE_REG_FR_TREAL10__A 0x1820024 330 #define CE_REG_FR_TIMAG10__A 0x1820025 331 #define CE_REG_FR_TREAL11__A 0x1820026 332 #define CE_REG_FR_TIMAG11__A 0x1820027 333 #define CE_REG_FR_MID_TAP__A 0x1820028 334 #define CE_REG_FR_SQS_G00__A 0x1820029 335 #define CE_REG_FR_SQS_G01__A 0x182002A 336 #define CE_REG_FR_SQS_G02__A 0x182002B 337 #define CE_REG_FR_SQS_G03__A 0x182002C 338 #define CE_REG_FR_SQS_G04__A 0x182002D 339 #define CE_REG_FR_SQS_G05__A 0x182002E 340 #define CE_REG_FR_SQS_G06__A 0x182002F 341 #define CE_REG_FR_SQS_G07__A 0x1820030 342 #define CE_REG_FR_SQS_G08__A 0x1820031 343 #define CE_REG_FR_SQS_G09__A 0x1820032 344 #define CE_REG_FR_SQS_G10__A 0x1820033 345 #define CE_REG_FR_SQS_G11__A 0x1820034 346 #define CE_REG_FR_SQS_G12__A 0x1820035 347 #define CE_REG_FR_RIO_G00__A 0x1820036 348 #define CE_REG_FR_RIO_G01__A 0x1820037 349 #define CE_REG_FR_RIO_G02__A 0x1820038 350 #define CE_REG_FR_RIO_G03__A 0x1820039 351 #define CE_REG_FR_RIO_G04__A 0x182003A 352 #define CE_REG_FR_RIO_G05__A 0x182003B 353 #define CE_REG_FR_RIO_G06__A 0x182003C 354 #define CE_REG_FR_RIO_G07__A 0x182003D 355 #define CE_REG_FR_RIO_G08__A 0x182003E 356 #define CE_REG_FR_RIO_G09__A 0x182003F 357 #define CE_REG_FR_RIO_G10__A 0x1820040 358 #define CE_REG_FR_MODE__A 0x1820041 359 #define CE_REG_FR_SQS_TRH__A 0x1820042 360 #define CE_REG_FR_RIO_GAIN__A 0x1820043 361 #define CE_REG_FR_BYPASS__A 0x1820044 362 #define CE_REG_FR_PM_SET__A 0x1820045 363 #define CE_REG_FR_ERR_SH__A 0x1820046 364 #define CE_REG_FR_MAN_SH__A 0x1820047 365 #define CE_REG_FR_TAP_SH__A 0x1820048 366 #define EQ_COMM_EXEC__A 0x1C00000 367 #define EQ_REG_COMM_EXEC__A 0x1C10000 368 #define EQ_REG_COMM_MB__A 0x1C10002 369 #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 370 #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 371 #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 372 #define EQ_REG_SN_CEGAIN__A 0x1C1002A 373 #define EQ_REG_SN_OFFSET__A 0x1C1002B 374 #define EQ_REG_RC_SEL_CAR__A 0x1C10032 375 #define EQ_REG_RC_SEL_CAR_INIT 0x0 376 #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 377 #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 378 #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 379 #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 380 #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 381 #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 382 #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 383 #define EQ_REG_OT_CONST__A 0x1C10046 384 #define EQ_REG_OT_ALPHA__A 0x1C10047 385 #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 386 #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 387 #define EQ_REG_OT_CSI_STEP__A 0x1C1004A 388 #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 389 #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 390 #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 391 #define EC_SB_REG_COMM_EXEC__A 0x2010000 392 #define EC_SB_REG_TR_MODE__A 0x2010010 393 #define EC_SB_REG_TR_MODE_8K 0x0 394 #define EC_SB_REG_TR_MODE_2K 0x1 395 #define EC_SB_REG_CONST__A 0x2010011 396 #define EC_SB_REG_CONST_QPSK 0x0 397 #define EC_SB_REG_CONST_16QAM 0x1 398 #define EC_SB_REG_CONST_64QAM 0x2 399 #define EC_SB_REG_ALPHA__A 0x2010012 400 #define EC_SB_REG_PRIOR__A 0x2010013 401 #define EC_SB_REG_PRIOR_HI 0x0 402 #define EC_SB_REG_PRIOR_LO 0x1 403 #define EC_SB_REG_CSI_HI__A 0x2010014 404 #define EC_SB_REG_CSI_LO__A 0x2010015 405 #define EC_SB_REG_SMB_TGL__A 0x2010016 406 #define EC_SB_REG_SNR_HI__A 0x2010017 407 #define EC_SB_REG_SNR_MID__A 0x2010018 408 #define EC_SB_REG_SNR_LO__A 0x2010019 409 #define EC_SB_REG_SCALE_MSB__A 0x201001A 410 #define EC_SB_REG_SCALE_BIT2__A 0x201001B 411 #define EC_SB_REG_SCALE_LSB__A 0x201001C 412 #define EC_SB_REG_CSI_OFS__A 0x201001D 413 #define EC_VD_REG_COMM_EXEC__A 0x2090000 414 #define EC_VD_REG_FORCE__A 0x2090010 415 #define EC_VD_REG_SET_CODERATE__A 0x2090011 416 #define EC_VD_REG_SET_CODERATE_C1_2 0x0 417 #define EC_VD_REG_SET_CODERATE_C2_3 0x1 418 #define EC_VD_REG_SET_CODERATE_C3_4 0x2 419 #define EC_VD_REG_SET_CODERATE_C5_6 0x3 420 #define EC_VD_REG_SET_CODERATE_C7_8 0x4 421 #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 422 #define EC_VD_REG_RLK_ENA__A 0x2090014 423 #define EC_OD_REG_COMM_EXEC__A 0x2110000 424 #define EC_OD_REG_SYNC__A 0x2110010 425 #define EC_OD_DEINT_RAM__A 0x2120000 426 #define EC_RS_REG_COMM_EXEC__A 0x2130000 427 #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 428 #define EC_RS_REG_VAL__A 0x2130011 429 #define EC_RS_REG_VAL_PCK 0x1 430 #define EC_RS_EC_RAM__A 0x2140000 431 #define EC_OC_REG_COMM_EXEC__A 0x2150000 432 #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 433 #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 434 #define EC_OC_REG_COMM_INT_STA__A 0x2150007 435 #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 436 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 437 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 438 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 439 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 440 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 441 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 442 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 443 #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 444 #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 445 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 446 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 447 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 448 #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 449 #define EC_OC_REG_OC_MPG_SIO__M 0xFFF 450 #define EC_OC_REG_OC_MON_SIO__A 0x2150013 451 #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 452 #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 453 #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 454 #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 455 #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D 456 #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E 457 #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F 458 #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 459 #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 460 #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 461 #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 462 #define EC_OC_REG_RCN_MODE__A 0x2150027 463 #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 464 #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 465 #define EC_OC_REG_RCN_CST_LOP__A 0x215002A 466 #define EC_OC_REG_RCN_CST_HIP__A 0x215002B 467 #define EC_OC_REG_RCN_SET_LVL__A 0x215002C 468 #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D 469 #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 470 #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 471 #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 472 #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 473 #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 474 #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF 475 #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 476 #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 477 #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 478 #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 479 #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 480 #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 481 #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 482 #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 483 #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 484 #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 485 #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 486 #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 487 #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 488 #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 489 #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 490 #define EC_OC_REG_OCR_MON_WRI__A 0x215003A 491 #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 492 #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 493 #define CC_REG_OSC_MODE__A 0x2410010 494 #define CC_REG_OSC_MODE_M20 0x1 495 #define CC_REG_PLL_MODE__A 0x2410011 496 #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 497 #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 498 #define CC_REG_REF_DIVIDE__A 0x2410012 499 #define CC_REG_PWD_MODE__A 0x2410015 500 #define CC_REG_PWD_MODE_DOWN_PLL 0x2 501 #define CC_REG_UPDATE__A 0x2410017 502 #define CC_REG_UPDATE_KEY 0x3973 503 #define CC_REG_JTAGID_L__A 0x2410019 504 #define LC_COMM_EXEC__A 0x2800000 505 #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 506 #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 507 #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 508 #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 509 #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 510 #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 511 #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 512 #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 513 #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 514 #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 515 #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 516 #define B_HI_COMM_EXEC__A 0x400000 517 #define B_HI_COMM_MB__A 0x400002 518 #define B_HI_CT_REG_COMM_STATE__A 0x410001 519 #define B_HI_RA_RAM_SRV_RES__A 0x420031 520 #define B_HI_RA_RAM_SRV_CMD__A 0x420032 521 #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 522 #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 523 #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 524 #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 525 #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 526 #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 527 #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 528 #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 529 #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 530 #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 531 #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 532 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 533 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 534 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 535 #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 536 #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 537 #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 538 #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 539 #define B_SC_COMM_EXEC__A 0x800000 540 #define B_SC_COMM_EXEC_CTL_STOP 0x0 541 #define B_SC_COMM_STATE__A 0x800001 542 #define B_SC_RA_RAM_PARAM0__A 0x820040 543 #define B_SC_RA_RAM_PARAM1__A 0x820041 544 #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 545 #define B_SC_RA_RAM_CMD__A 0x820043 546 #define B_SC_RA_RAM_CMD_PROC_START 0x1 547 #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 548 #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 549 #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 550 #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 551 #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 552 #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 553 #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 554 #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 555 #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 556 #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 557 #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 558 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 559 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 560 #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 561 #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 562 #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 563 #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 564 #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 565 #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 566 #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 567 #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 568 #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 569 #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 570 #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 571 #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 572 #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 573 #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 574 #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 575 #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 576 #define B_SC_RA_RAM_LOCK__A 0x82004B 577 #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 578 #define B_SC_RA_RAM_LOCK_FEC__M 0x2 579 #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 580 #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C 581 #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 582 #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D 583 #define B_SC_RA_RAM_CONFIG__A 0x820050 584 #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 585 #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 586 #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 587 #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 588 #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 589 #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D 590 #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E 591 #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E 592 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 593 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 594 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A 595 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B 596 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C 597 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D 598 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E 599 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F 600 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 601 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 602 #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 603 #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 604 #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 605 #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 606 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 607 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 608 #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 609 #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 610 #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 611 #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 612 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 613 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 614 #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 615 #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 616 #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 617 #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 618 #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA 619 #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB 620 #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB 621 #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 622 #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC 623 #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 624 #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD 625 #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 626 #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 627 #define B_SC_RA_RAM_BAND__A 0x8200EC 628 #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 629 #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F 630 #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 631 #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F 632 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 633 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 634 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 635 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 636 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D 637 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 638 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D 639 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 640 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 641 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 642 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 643 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 644 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A 645 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 646 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB 647 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 648 #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE 649 #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 650 #define B_FE_COMM_EXEC__A 0xC00000 651 #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 652 #define B_FE_AD_REG_FDB_IN__A 0xC10012 653 #define B_FE_AD_REG_PD__A 0xC10013 654 #define B_FE_AD_REG_INVEXT__A 0xC10014 655 #define B_FE_AD_REG_CLKNEG__A 0xC10015 656 #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 657 #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 658 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 659 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 660 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 661 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 662 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 663 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 664 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 665 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 666 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 667 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 668 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 669 #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 670 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 671 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 672 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 673 #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 674 #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 675 #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 676 #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 677 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 678 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 679 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 680 #define B_FE_AG_REG_AG_PWD__A 0xC20015 681 #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 682 #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 683 #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 684 #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 685 #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 686 #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A 687 #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B 688 #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 689 #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 690 #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 691 #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF 692 #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 693 #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 694 #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 695 #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 696 #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A 697 #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B 698 #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C 699 #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D 700 #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E 701 #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 702 #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF 703 #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 704 #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 705 #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 706 #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 707 #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 708 #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF 709 #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 710 #define B_FE_AG_REG_IND_WIN__A 0xC2003C 711 #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D 712 #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E 713 #define B_FE_AG_REG_IND_DEL__A 0xC2003F 714 #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 715 #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 716 #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 717 #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 718 #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 719 #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 720 #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 721 #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 722 #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 723 #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 724 #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A 725 #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B 726 #define B_FE_AG_REG_PDC_MAX__A 0xC2004C 727 #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D 728 #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E 729 #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F 730 #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 731 #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 732 #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F 733 #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 734 #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 735 #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 736 #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 737 #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 738 #define B_FE_AG_REG_FGM_WRI__A 0xC20061 739 #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 740 #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 741 #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 742 #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 743 #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 744 #define B_FE_FD_REG_SCL__A 0xC40010 745 #define B_FE_FD_REG_MAX_LEV__A 0xC40011 746 #define B_FE_FD_REG_NR__A 0xC40012 747 #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 748 #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 749 #define B_FE_IF_REG_INCR0__A 0xC50010 750 #define B_FE_IF_REG_INCR0__W 16 751 #define B_FE_IF_REG_INCR0__M 0xFFFF 752 #define B_FE_IF_REG_INCR1__A 0xC50011 753 #define B_FE_IF_REG_INCR1__M 0xFF 754 #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 755 #define B_FE_CF_REG_SCL__A 0xC60010 756 #define B_FE_CF_REG_MAX_LEV__A 0xC60011 757 #define B_FE_CF_REG_NR__A 0xC60012 758 #define B_FE_CF_REG_IMP_VAL__A 0xC60013 759 #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 760 #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 761 #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 762 #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 763 #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 764 #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 765 #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 766 #define B_FT_COMM_EXEC__A 0x1000000 767 #define B_FT_REG_COMM_EXEC__A 0x1010000 768 #define B_CP_COMM_EXEC__A 0x1400000 769 #define B_CP_REG_COMM_EXEC__A 0x1410000 770 #define B_CP_REG_INTERVAL__A 0x1410011 771 #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 772 #define B_CP_REG_BR_STR_DEL__A 0x1410024 773 #define B_CP_REG_RT_ANG_INC0__A 0x1410030 774 #define B_CP_REG_RT_ANG_INC1__A 0x1410031 775 #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 776 #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 777 #define B_CP_REG_AC_AVER_POW__A 0x1410041 778 #define B_CP_REG_AC_MAX_POW__A 0x1410042 779 #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 780 #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 781 #define B_CP_REG_AC_AMP_MODE__A 0x1410047 782 #define B_CP_REG_AC_AMP_FIX__A 0x1410048 783 #define B_CP_REG_AC_ANG_MODE__A 0x141004A 784 #define B_CE_COMM_EXEC__A 0x1800000 785 #define B_CE_REG_COMM_EXEC__A 0x1810000 786 #define B_CE_REG_TAPSET__A 0x1810011 787 #define B_CE_REG_AVG_POW__A 0x1810012 788 #define B_CE_REG_MAX_POW__A 0x1810013 789 #define B_CE_REG_ATT__A 0x1810014 790 #define B_CE_REG_NRED__A 0x1810015 791 #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 792 #define B_CE_REG_NE_TD_CAL__A 0x1810044 793 #define B_CE_REG_NE_MIXAVG__A 0x1810046 794 #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 795 #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 796 #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 797 #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 798 #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 799 #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 800 #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 801 #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 802 #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A 803 #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 804 #define B_CE_REG_FI_SHT_INCR__A 0x1810090 805 #define B_CE_REG_FI_EXP_NORM__A 0x1810091 806 #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 807 #define B_CE_REG_IR_STARTPOS__A 0x18100A1 808 #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 809 #define B_CE_REG_FR_TREAL00__A 0x1820010 810 #define B_CE_REG_FR_TIMAG00__A 0x1820011 811 #define B_CE_REG_FR_TREAL01__A 0x1820012 812 #define B_CE_REG_FR_TIMAG01__A 0x1820013 813 #define B_CE_REG_FR_TREAL02__A 0x1820014 814 #define B_CE_REG_FR_TIMAG02__A 0x1820015 815 #define B_CE_REG_FR_TREAL03__A 0x1820016 816 #define B_CE_REG_FR_TIMAG03__A 0x1820017 817 #define B_CE_REG_FR_TREAL04__A 0x1820018 818 #define B_CE_REG_FR_TIMAG04__A 0x1820019 819 #define B_CE_REG_FR_TREAL05__A 0x182001A 820 #define B_CE_REG_FR_TIMAG05__A 0x182001B 821 #define B_CE_REG_FR_TREAL06__A 0x182001C 822 #define B_CE_REG_FR_TIMAG06__A 0x182001D 823 #define B_CE_REG_FR_TREAL07__A 0x182001E 824 #define B_CE_REG_FR_TIMAG07__A 0x182001F 825 #define B_CE_REG_FR_TREAL08__A 0x1820020 826 #define B_CE_REG_FR_TIMAG08__A 0x1820021 827 #define B_CE_REG_FR_TREAL09__A 0x1820022 828 #define B_CE_REG_FR_TIMAG09__A 0x1820023 829 #define B_CE_REG_FR_TREAL10__A 0x1820024 830 #define B_CE_REG_FR_TIMAG10__A 0x1820025 831 #define B_CE_REG_FR_TREAL11__A 0x1820026 832 #define B_CE_REG_FR_TIMAG11__A 0x1820027 833 #define B_CE_REG_FR_MID_TAP__A 0x1820028 834 #define B_CE_REG_FR_SQS_G00__A 0x1820029 835 #define B_CE_REG_FR_SQS_G01__A 0x182002A 836 #define B_CE_REG_FR_SQS_G02__A 0x182002B 837 #define B_CE_REG_FR_SQS_G03__A 0x182002C 838 #define B_CE_REG_FR_SQS_G04__A 0x182002D 839 #define B_CE_REG_FR_SQS_G05__A 0x182002E 840 #define B_CE_REG_FR_SQS_G06__A 0x182002F 841 #define B_CE_REG_FR_SQS_G07__A 0x1820030 842 #define B_CE_REG_FR_SQS_G08__A 0x1820031 843 #define B_CE_REG_FR_SQS_G09__A 0x1820032 844 #define B_CE_REG_FR_SQS_G10__A 0x1820033 845 #define B_CE_REG_FR_SQS_G11__A 0x1820034 846 #define B_CE_REG_FR_SQS_G12__A 0x1820035 847 #define B_CE_REG_FR_RIO_G00__A 0x1820036 848 #define B_CE_REG_FR_RIO_G01__A 0x1820037 849 #define B_CE_REG_FR_RIO_G02__A 0x1820038 850 #define B_CE_REG_FR_RIO_G03__A 0x1820039 851 #define B_CE_REG_FR_RIO_G04__A 0x182003A 852 #define B_CE_REG_FR_RIO_G05__A 0x182003B 853 #define B_CE_REG_FR_RIO_G06__A 0x182003C 854 #define B_CE_REG_FR_RIO_G07__A 0x182003D 855 #define B_CE_REG_FR_RIO_G08__A 0x182003E 856 #define B_CE_REG_FR_RIO_G09__A 0x182003F 857 #define B_CE_REG_FR_RIO_G10__A 0x1820040 858 #define B_CE_REG_FR_MODE__A 0x1820041 859 #define B_CE_REG_FR_SQS_TRH__A 0x1820042 860 #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 861 #define B_CE_REG_FR_BYPASS__A 0x1820044 862 #define B_CE_REG_FR_PM_SET__A 0x1820045 863 #define B_CE_REG_FR_ERR_SH__A 0x1820046 864 #define B_CE_REG_FR_MAN_SH__A 0x1820047 865 #define B_CE_REG_FR_TAP_SH__A 0x1820048 866 #define B_EQ_COMM_EXEC__A 0x1C00000 867 #define B_EQ_REG_COMM_EXEC__A 0x1C10000 868 #define B_EQ_REG_COMM_MB__A 0x1C10002 869 #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 870 #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 871 #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 872 #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A 873 #define B_EQ_REG_SN_OFFSET__A 0x1C1002B 874 #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 875 #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 876 #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 877 #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 878 #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 879 #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 880 #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 881 #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 882 #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 883 #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 884 #define B_EQ_REG_OT_CONST__A 0x1C10046 885 #define B_EQ_REG_OT_ALPHA__A 0x1C10047 886 #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 887 #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 888 #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A 889 #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B 890 #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 891 #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 892 #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 893 #define B_EC_SB_REG_TR_MODE__A 0x2010010 894 #define B_EC_SB_REG_TR_MODE_8K 0x0 895 #define B_EC_SB_REG_TR_MODE_2K 0x1 896 #define B_EC_SB_REG_CONST__A 0x2010011 897 #define B_EC_SB_REG_CONST_QPSK 0x0 898 #define B_EC_SB_REG_CONST_16QAM 0x1 899 #define B_EC_SB_REG_CONST_64QAM 0x2 900 #define B_EC_SB_REG_ALPHA__A 0x2010012 901 #define B_EC_SB_REG_PRIOR__A 0x2010013 902 #define B_EC_SB_REG_PRIOR_HI 0x0 903 #define B_EC_SB_REG_PRIOR_LO 0x1 904 #define B_EC_SB_REG_CSI_HI__A 0x2010014 905 #define B_EC_SB_REG_CSI_LO__A 0x2010015 906 #define B_EC_SB_REG_SMB_TGL__A 0x2010016 907 #define B_EC_SB_REG_SNR_HI__A 0x2010017 908 #define B_EC_SB_REG_SNR_MID__A 0x2010018 909 #define B_EC_SB_REG_SNR_LO__A 0x2010019 910 #define B_EC_SB_REG_SCALE_MSB__A 0x201001A 911 #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B 912 #define B_EC_SB_REG_SCALE_LSB__A 0x201001C 913 #define B_EC_SB_REG_CSI_OFS0__A 0x201001D 914 #define B_EC_SB_REG_CSI_OFS1__A 0x201001E 915 #define B_EC_SB_REG_CSI_OFS2__A 0x201001F 916 #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 917 #define B_EC_VD_REG_FORCE__A 0x2090010 918 #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 919 #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 920 #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 921 #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 922 #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 923 #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 924 #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 925 #define B_EC_VD_REG_RLK_ENA__A 0x2090014 926 #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 927 #define B_EC_OD_REG_SYNC__A 0x2110664 928 #define B_EC_OD_DEINT_RAM__A 0x2120000 929 #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 930 #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 931 #define B_EC_RS_REG_VAL__A 0x2130011 932 #define B_EC_RS_REG_VAL_PCK 0x1 933 #define B_EC_RS_EC_RAM__A 0x2140000 934 #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 935 #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 936 #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 937 #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 938 #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 939 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 940 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 941 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 942 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 943 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 944 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 945 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 946 #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 947 #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 948 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 949 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 950 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 951 #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 952 #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF 953 #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 954 #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 955 #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 956 #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 957 #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D 958 #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E 959 #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F 960 #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 961 #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 962 #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 963 #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 964 #define B_EC_OC_REG_RCN_MODE__A 0x2150027 965 #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 966 #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 967 #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A 968 #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B 969 #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C 970 #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D 971 #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 972 #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 973 #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 974 #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 975 #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 976 #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF 977 #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 978 #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 979 #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 980 #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 981 #define B_EC_OC_REG_DTO_PER__A 0x2150048 982 #define B_EC_OC_REG_DTO_BUR__A 0x2150049 983 #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A 984 #define B_CC_REG_OSC_MODE__A 0x2410010 985 #define B_CC_REG_OSC_MODE_M20 0x1 986 #define B_CC_REG_PLL_MODE__A 0x2410011 987 #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 988 #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 989 #define B_CC_REG_REF_DIVIDE__A 0x2410012 990 #define B_CC_REG_PWD_MODE__A 0x2410015 991 #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 992 #define B_CC_REG_UPDATE__A 0x2410017 993 #define B_CC_REG_UPDATE_KEY 0x3973 994 #define B_CC_REG_JTAGID_L__A 0x2410019 995 #define B_CC_REG_DIVERSITY__A 0x241001B 996 #define B_LC_COMM_EXEC__A 0x2800000 997 #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C 998 #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A 999 #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 1000 #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 1001 #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 1002 #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 1003 #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 1004 #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 1005 #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 1006 #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 1007 #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 1008 1009 #endif 1010