1 /*
2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3  * 	Author: Tomasz Figa <t.figa@samsung.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * Device Tree binding constants for Samsung Exynos3250 clock controllers.
10  */
11 
12 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
13 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
14 
15 /*
16  * Let each exported clock get a unique index, which is used on DT-enabled
17  * platforms to lookup the clock from a clock specifier. These indices are
18  * therefore considered an ABI and so must not be changed. This implies
19  * that new clocks should be added either in free spaces between clock groups
20  * or at the end.
21  */
22 
23 
24 /*
25  * Main CMU
26  */
27 
28 #define CLK_OSCSEL			1
29 #define CLK_FIN_PLL			2
30 #define CLK_FOUT_APLL			3
31 #define CLK_FOUT_VPLL			4
32 #define CLK_FOUT_UPLL			5
33 #define CLK_FOUT_MPLL			6
34 #define CLK_ARM_CLK			7
35 
36 /* Muxes */
37 #define CLK_MOUT_MPLL_USER_L		16
38 #define CLK_MOUT_GDL			17
39 #define CLK_MOUT_MPLL_USER_R		18
40 #define CLK_MOUT_GDR			19
41 #define CLK_MOUT_EBI			20
42 #define CLK_MOUT_ACLK_200		21
43 #define CLK_MOUT_ACLK_160		22
44 #define CLK_MOUT_ACLK_100		23
45 #define CLK_MOUT_ACLK_266_1		24
46 #define CLK_MOUT_ACLK_266_0		25
47 #define CLK_MOUT_ACLK_266		26
48 #define CLK_MOUT_VPLL			27
49 #define CLK_MOUT_EPLL_USER		28
50 #define CLK_MOUT_EBI_1			29
51 #define CLK_MOUT_UPLL			30
52 #define CLK_MOUT_ACLK_400_MCUISP_SUB	31
53 #define CLK_MOUT_MPLL			32
54 #define CLK_MOUT_ACLK_400_MCUISP	33
55 #define CLK_MOUT_VPLLSRC		34
56 #define CLK_MOUT_CAM1			35
57 #define CLK_MOUT_CAM_BLK		36
58 #define CLK_MOUT_MFC			37
59 #define CLK_MOUT_MFC_1			38
60 #define CLK_MOUT_MFC_0			39
61 #define CLK_MOUT_G3D			40
62 #define CLK_MOUT_G3D_1			41
63 #define CLK_MOUT_G3D_0			42
64 #define CLK_MOUT_MIPI0			43
65 #define CLK_MOUT_FIMD0			44
66 #define CLK_MOUT_UART_ISP		45
67 #define CLK_MOUT_SPI1_ISP		46
68 #define CLK_MOUT_SPI0_ISP		47
69 #define CLK_MOUT_TSADC			48
70 #define CLK_MOUT_MMC1			49
71 #define CLK_MOUT_MMC0			50
72 #define CLK_MOUT_UART1			51
73 #define CLK_MOUT_UART0			52
74 #define CLK_MOUT_SPI1			53
75 #define CLK_MOUT_SPI0			54
76 #define CLK_MOUT_AUDIO			55
77 #define CLK_MOUT_MPLL_USER_C		56
78 #define CLK_MOUT_HPM			57
79 #define CLK_MOUT_CORE			58
80 #define CLK_MOUT_APLL			59
81 #define CLK_MOUT_ACLK_266_SUB		60
82 #define CLK_MOUT_UART2			61
83 #define CLK_MOUT_MMC2			62
84 
85 /* Dividers */
86 #define CLK_DIV_GPL			64
87 #define CLK_DIV_GDL			65
88 #define CLK_DIV_GPR			66
89 #define CLK_DIV_GDR			67
90 #define CLK_DIV_MPLL_PRE		68
91 #define CLK_DIV_ACLK_400_MCUISP		69
92 #define CLK_DIV_EBI			70
93 #define CLK_DIV_ACLK_200		71
94 #define CLK_DIV_ACLK_160		72
95 #define CLK_DIV_ACLK_100		73
96 #define CLK_DIV_ACLK_266		74
97 #define CLK_DIV_CAM1			75
98 #define CLK_DIV_CAM_BLK			76
99 #define CLK_DIV_MFC			77
100 #define CLK_DIV_G3D			78
101 #define CLK_DIV_MIPI0_PRE		79
102 #define CLK_DIV_MIPI0			80
103 #define CLK_DIV_FIMD0			81
104 #define CLK_DIV_UART_ISP		82
105 #define CLK_DIV_SPI1_ISP_PRE		83
106 #define CLK_DIV_SPI1_ISP		84
107 #define CLK_DIV_SPI0_ISP_PRE		85
108 #define CLK_DIV_SPI0_ISP		86
109 #define CLK_DIV_TSADC_PRE		87
110 #define CLK_DIV_TSADC			88
111 #define CLK_DIV_MMC1_PRE		89
112 #define CLK_DIV_MMC1			90
113 #define CLK_DIV_MMC0_PRE		91
114 #define CLK_DIV_MMC0			92
115 #define CLK_DIV_UART1			93
116 #define CLK_DIV_UART0			94
117 #define CLK_DIV_SPI1_PRE		95
118 #define CLK_DIV_SPI1			96
119 #define CLK_DIV_SPI0_PRE		97
120 #define CLK_DIV_SPI0			98
121 #define CLK_DIV_PCM			99
122 #define CLK_DIV_AUDIO			100
123 #define CLK_DIV_I2S			101
124 #define CLK_DIV_CORE2			102
125 #define CLK_DIV_APLL			103
126 #define CLK_DIV_PCLK_DBG		104
127 #define CLK_DIV_ATB			105
128 #define CLK_DIV_COREM			106
129 #define CLK_DIV_CORE			107
130 #define CLK_DIV_HPM			108
131 #define CLK_DIV_COPY			109
132 #define CLK_DIV_UART2			110
133 #define CLK_DIV_MMC2_PRE		111
134 #define CLK_DIV_MMC2			112
135 
136 /* Gates */
137 #define CLK_ASYNC_G3D			128
138 #define CLK_ASYNC_MFCL			129
139 #define CLK_PPMULEFT			130
140 #define CLK_GPIO_LEFT			131
141 #define CLK_ASYNC_ISPMX			132
142 #define CLK_ASYNC_FSYSD			133
143 #define CLK_ASYNC_LCD0X			134
144 #define CLK_ASYNC_CAMX			135
145 #define CLK_PPMURIGHT			136
146 #define CLK_GPIO_RIGHT			137
147 #define CLK_MONOCNT			138
148 #define CLK_TZPC6			139
149 #define CLK_PROVISIONKEY1		140
150 #define CLK_PROVISIONKEY0		141
151 #define CLK_CMU_ISPPART			142
152 #define CLK_TMU_APBIF			143
153 #define CLK_KEYIF			144
154 #define CLK_RTC				145
155 #define CLK_WDT				146
156 #define CLK_MCT				147
157 #define CLK_SECKEY			148
158 #define CLK_TZPC5			149
159 #define CLK_TZPC4			150
160 #define CLK_TZPC3			151
161 #define CLK_TZPC2			152
162 #define CLK_TZPC1			153
163 #define CLK_TZPC0			154
164 #define CLK_CMU_COREPART		155
165 #define CLK_CMU_TOPPART			156
166 #define CLK_PMU_APBIF			157
167 #define CLK_SYSREG			158
168 #define CLK_CHIP_ID			159
169 #define CLK_QEJPEG			160
170 #define CLK_PIXELASYNCM1		161
171 #define CLK_PIXELASYNCM0		162
172 #define CLK_PPMUCAMIF			163
173 #define CLK_QEM2MSCALER			164
174 #define CLK_QEGSCALER1			165
175 #define CLK_QEGSCALER0			166
176 #define CLK_SMMUJPEG			167
177 #define CLK_SMMUM2M2SCALER		168
178 #define CLK_SMMUGSCALER1		169
179 #define CLK_SMMUGSCALER0		170
180 #define CLK_JPEG			171
181 #define CLK_M2MSCALER			172
182 #define CLK_GSCALER1			173
183 #define CLK_GSCALER0			174
184 #define CLK_QEMFC			175
185 #define CLK_PPMUMFC_L			176
186 #define CLK_SMMUMFC_L			177
187 #define CLK_MFC				178
188 #define CLK_SMMUG3D			179
189 #define CLK_QEG3D			180
190 #define CLK_PPMUG3D			181
191 #define CLK_G3D				182
192 #define CLK_QE_CH1_LCD			183
193 #define CLK_QE_CH0_LCD			184
194 #define CLK_PPMULCD0			185
195 #define CLK_SMMUFIMD0			186
196 #define CLK_DSIM0			187
197 #define CLK_FIMD0			188
198 #define CLK_CAM1			189
199 #define CLK_UART_ISP_TOP		190
200 #define CLK_SPI1_ISP_TOP		191
201 #define CLK_SPI0_ISP_TOP		192
202 #define CLK_TSADC			193
203 #define CLK_PPMUFILE			194
204 #define CLK_USBOTG			195
205 #define CLK_USBHOST			196
206 #define CLK_SROMC			197
207 #define CLK_SDMMC1			198
208 #define CLK_SDMMC0			199
209 #define CLK_PDMA1			200
210 #define CLK_PDMA0			201
211 #define CLK_PWM				202
212 #define CLK_PCM				203
213 #define CLK_I2S				204
214 #define CLK_SPI1			205
215 #define CLK_SPI0			206
216 #define CLK_I2C7			207
217 #define CLK_I2C6			208
218 #define CLK_I2C5			209
219 #define CLK_I2C4			210
220 #define CLK_I2C3			211
221 #define CLK_I2C2			212
222 #define CLK_I2C1			213
223 #define CLK_I2C0			214
224 #define CLK_UART1			215
225 #define CLK_UART0			216
226 #define CLK_BLOCK_LCD			217
227 #define CLK_BLOCK_G3D			218
228 #define CLK_BLOCK_MFC			219
229 #define CLK_BLOCK_CAM			220
230 #define CLK_SMIES			221
231 #define CLK_UART2			222
232 #define CLK_SDMMC2			223
233 
234 /* Special clocks */
235 #define CLK_SCLK_JPEG			224
236 #define CLK_SCLK_M2MSCALER		225
237 #define CLK_SCLK_GSCALER1		226
238 #define CLK_SCLK_GSCALER0		227
239 #define CLK_SCLK_MFC			228
240 #define CLK_SCLK_G3D			229
241 #define CLK_SCLK_MIPIDPHY2L		230
242 #define CLK_SCLK_MIPI0			231
243 #define CLK_SCLK_FIMD0			232
244 #define CLK_SCLK_CAM1			233
245 #define CLK_SCLK_UART_ISP		234
246 #define CLK_SCLK_SPI1_ISP		235
247 #define CLK_SCLK_SPI0_ISP		236
248 #define CLK_SCLK_UPLL			237
249 #define CLK_SCLK_TSADC			238
250 #define CLK_SCLK_EBI			239
251 #define CLK_SCLK_MMC1			240
252 #define CLK_SCLK_MMC0			241
253 #define CLK_SCLK_I2S			242
254 #define CLK_SCLK_PCM			243
255 #define CLK_SCLK_SPI1			244
256 #define CLK_SCLK_SPI0			245
257 #define CLK_SCLK_UART1			246
258 #define CLK_SCLK_UART0			247
259 #define CLK_SCLK_UART2			248
260 #define CLK_SCLK_MMC2			249
261 
262 /*
263  * Total number of clocks of main CMU.
264  * NOTE: Must be equal to last clock ID increased by one.
265  */
266 #define CLK_NR_CLKS			250
267 
268 /*
269  * CMU DMC
270  */
271 
272 #define CLK_FOUT_BPLL			1
273 #define CLK_FOUT_EPLL			2
274 
275 /* Muxes */
276 #define CLK_MOUT_MPLL_MIF		8
277 #define CLK_MOUT_BPLL			9
278 #define CLK_MOUT_DPHY			10
279 #define CLK_MOUT_DMC_BUS		11
280 #define CLK_MOUT_EPLL			12
281 
282 /* Dividers */
283 #define CLK_DIV_DMC			16
284 #define CLK_DIV_DPHY			17
285 #define CLK_DIV_DMC_PRE			18
286 #define CLK_DIV_DMCP			19
287 #define CLK_DIV_DMCD			20
288 
289 /*
290  * Total number of clocks of main CMU.
291  * NOTE: Must be equal to last clock ID increased by one.
292  */
293 #define NR_CLKS_DMC			21
294 
295 /*
296  * CMU ISP
297  */
298 
299 /* Dividers */
300 
301 #define CLK_DIV_ISP1			1
302 #define CLK_DIV_ISP0			2
303 #define CLK_DIV_MCUISP1			3
304 #define CLK_DIV_MCUISP0			4
305 #define CLK_DIV_MPWM			5
306 
307 /* Gates */
308 
309 #define CLK_UART_ISP			8
310 #define CLK_WDT_ISP			9
311 #define CLK_PWM_ISP			10
312 #define CLK_I2C1_ISP			11
313 #define CLK_I2C0_ISP			12
314 #define CLK_MPWM_ISP			13
315 #define CLK_MCUCTL_ISP			14
316 #define CLK_PPMUISPX			15
317 #define CLK_PPMUISPMX			16
318 #define CLK_QE_LITE1			17
319 #define CLK_QE_LITE0			18
320 #define CLK_QE_FD			19
321 #define CLK_QE_DRC			20
322 #define CLK_QE_ISP			21
323 #define CLK_CSIS1			22
324 #define CLK_SMMU_LITE1			23
325 #define CLK_SMMU_LITE0			24
326 #define CLK_SMMU_FD			25
327 #define CLK_SMMU_DRC			26
328 #define CLK_SMMU_ISP			27
329 #define CLK_GICISP			28
330 #define CLK_CSIS0			29
331 #define CLK_MCUISP			30
332 #define CLK_LITE1			31
333 #define CLK_LITE0			32
334 #define CLK_FD				33
335 #define CLK_DRC				34
336 #define CLK_ISP				35
337 #define CLK_QE_ISPCX			36
338 #define CLK_QE_SCALERP			37
339 #define CLK_QE_SCALERC			38
340 #define CLK_SMMU_SCALERP		39
341 #define CLK_SMMU_SCALERC		40
342 #define CLK_SCALERP			41
343 #define CLK_SCALERC			42
344 #define CLK_SPI1_ISP			43
345 #define CLK_SPI0_ISP			44
346 #define CLK_SMMU_ISPCX			45
347 #define CLK_ASYNCAXIM			46
348 #define CLK_SCLK_MPWM_ISP		47
349 
350 /*
351  * Total number of clocks of CMU_ISP.
352  * NOTE: Must be equal to last clock ID increased by one.
353  */
354 #define NR_CLKS_ISP			48
355 
356 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
357