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Searched refs:CLK_MM_DISP_PWM0_MM (Results 1 – 2 of 2) sorted by relevance

/linux-4.19.296/drivers/clk/mediatek/
Dclk-mt2712-mm.c101 GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
/linux-4.19.296/include/dt-bindings/clock/
Dmt2712-clk.h338 #define CLK_MM_DISP_PWM0_MM 30 macro