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Searched refs:CLK_TOP_APLL_DIV_PDN1 (Results 1 – 2 of 2) sorted by relevance

/linux-4.19.296/include/dt-bindings/clock/
Dmt2712-clk.h218 #define CLK_TOP_APLL_DIV_PDN1 179 macro
/linux-4.19.296/drivers/clk/mediatek/
Dclk-mt2712.c985 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),