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Searched refs:CLK_TOP_CCI400_SEL (Results 1 – 4 of 4) sorted by relevance

/linux-4.19.296/include/dt-bindings/clock/
Dmt8173-clk.h126 #define CLK_TOP_CCI400_SEL 108 macro
Dmt2712-clk.h163 #define CLK_TOP_CCI400_SEL 124 macro
/linux-4.19.296/drivers/clk/mediatek/
Dclk-mt8173.c586 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
928 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]); in mtk_clk_enable_critical()
Dclk-mt2712.c798 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",