Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 8 of 8) sorted by relevance
| /linux-4.19.296/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
|
| D | mt7622-clk.h | 78 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
|
| D | mt8173-clk.h | 102 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
|
| D | mt2701-clk.h | 96 #define CLK_TOP_DDRPHYCFG_SEL 77 macro
|
| /linux-4.19.296/drivers/clk/mediatek/ |
| D | clk-mt7622.c | 527 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
650 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
|
| D | clk-mt8173.c | 552 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
927 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_clk_enable_critical()
|
| D | clk-mt8135.c | 389 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
|
| D | clk-mt2701.c | 505 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
|