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Searched refs:CLK_TOP_MSDC30_0_SEL (Results 1 – 6 of 6) sorted by relevance

/linux-4.19.296/include/dt-bindings/clock/
Dmt8135-clk.h105 #define CLK_TOP_MSDC30_0_SEL 86 macro
Dmt7622-clk.h88 #define CLK_TOP_MSDC30_0_SEL 68 macro
Dmt2701-clk.h103 #define CLK_TOP_MSDC30_0_SEL 84 macro
/linux-4.19.296/drivers/clk/mediatek/
Dclk-mt8135.c394 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
Dclk-mt7622.c553 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
Dclk-mt2701.c525 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,