Searched refs:CLK_TYPE_DIV6P1 (Results 1 – 2 of 2) sorted by relevance
39 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ enumerator56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
290 case CLK_TYPE_DIV6P1: in cpg_mssr_register_core_clk()305 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()