Searched refs:CLK_UART2 (Results 1 – 19 of 19) sorted by relevance
/linux-4.19.296/include/dt-bindings/clock/ |
D | exynos5410.h | 41 #define CLK_UART2 259 macro
|
D | actions,s700-cmu.h | 60 #define CLK_UART2 38 macro
|
D | actions,s900-cmu.h | 87 #define CLK_UART2 69 macro
|
D | exynos5250.h | 97 #define CLK_UART2 291 macro
|
D | s5pv210.h | 162 #define CLK_UART2 141 macro
|
D | exynos5420.h | 70 #define CLK_UART2 259 macro
|
D | exynos4.h | 155 #define CLK_UART2 314 macro
|
D | exynos3250.h | 231 #define CLK_UART2 222 macro
|
D | sprd,sc9860-clk.h | 87 #define CLK_UART2 4 macro
|
/linux-4.19.296/drivers/clk/samsung/ |
D | clk-exynos5410.c | 202 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
|
D | clk-s5pv210.c | 615 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
|
D | clk-exynos5250.c | 616 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
|
D | clk-exynos3250.c | 666 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
|
D | clk-exynos4.c | 997 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
|
D | clk-exynos5420.c | 1101 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
|
/linux-4.19.296/drivers/clk/actions/ |
D | owl-s700.c | 526 [CLK_UART2] = &clk_uart2.common.hw,
|
D | owl-s900.c | 676 [CLK_UART2] = &uart2_clk.common.hw,
|
/linux-4.19.296/drivers/clk/renesas/ |
D | r9a06g032-clocks.c | 295 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
|
/linux-4.19.296/drivers/clk/sprd/ |
D | sc9860-clk.c | 469 [CLK_UART2] = &uart2_clk.common.hw,
|