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Searched refs:CON0_PCW_CHG (Results 1 – 1 of 1) sorted by relevance

/linux-4.19.296/drivers/clk/mediatek/
Dclk-pll.c30 #define CON0_PCW_CHG BIT(31) macro
148 con1 |= CON0_PCW_CHG; in mtk_pll_set_rate_regs()