1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
8
9 #include <linux/device.h>
10 #include <linux/perf_event.h>
11 #include <linux/sched.h>
12
13 /* Peripheral id registers (0xFD0-0xFEC) */
14 #define CORESIGHT_PERIPHIDR4 0xfd0
15 #define CORESIGHT_PERIPHIDR5 0xfd4
16 #define CORESIGHT_PERIPHIDR6 0xfd8
17 #define CORESIGHT_PERIPHIDR7 0xfdC
18 #define CORESIGHT_PERIPHIDR0 0xfe0
19 #define CORESIGHT_PERIPHIDR1 0xfe4
20 #define CORESIGHT_PERIPHIDR2 0xfe8
21 #define CORESIGHT_PERIPHIDR3 0xfeC
22 /* Component id registers (0xFF0-0xFFC) */
23 #define CORESIGHT_COMPIDR0 0xff0
24 #define CORESIGHT_COMPIDR1 0xff4
25 #define CORESIGHT_COMPIDR2 0xff8
26 #define CORESIGHT_COMPIDR3 0xffC
27
28 #define ETM_ARCH_V3_3 0x23
29 #define ETM_ARCH_V3_5 0x25
30 #define PFT_ARCH_V1_0 0x30
31 #define PFT_ARCH_V1_1 0x31
32
33 #define CORESIGHT_UNLOCK 0xc5acce55
34
35 extern struct bus_type coresight_bustype;
36
37 enum coresight_dev_type {
38 CORESIGHT_DEV_TYPE_NONE,
39 CORESIGHT_DEV_TYPE_SINK,
40 CORESIGHT_DEV_TYPE_LINK,
41 CORESIGHT_DEV_TYPE_LINKSINK,
42 CORESIGHT_DEV_TYPE_SOURCE,
43 CORESIGHT_DEV_TYPE_HELPER,
44 };
45
46 enum coresight_dev_subtype_sink {
47 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
48 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
49 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
50 };
51
52 enum coresight_dev_subtype_link {
53 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
54 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
55 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
56 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
57 };
58
59 enum coresight_dev_subtype_source {
60 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
61 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
62 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
63 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
64 };
65
66 enum coresight_dev_subtype_helper {
67 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
68 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
69 };
70
71 /**
72 * union coresight_dev_subtype - further characterisation of a type
73 * @sink_subtype: type of sink this component is, as defined
74 * by @coresight_dev_subtype_sink.
75 * @link_subtype: type of link this component is, as defined
76 * by @coresight_dev_subtype_link.
77 * @source_subtype: type of source this component is, as defined
78 * by @coresight_dev_subtype_source.
79 * @helper_subtype: type of helper this component is, as defined
80 * by @coresight_dev_subtype_helper.
81 */
82 union coresight_dev_subtype {
83 /* We have some devices which acts as LINK and SINK */
84 struct {
85 enum coresight_dev_subtype_sink sink_subtype;
86 enum coresight_dev_subtype_link link_subtype;
87 };
88 enum coresight_dev_subtype_source source_subtype;
89 enum coresight_dev_subtype_helper helper_subtype;
90 };
91
92 /**
93 * struct coresight_platform_data - data harvested from the DT specification
94 * @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs.
95 * @name: name of the component as shown under sysfs.
96 * @nr_inport: number of input ports for this component.
97 * @outports: list of remote endpoint port number.
98 * @child_names:name of all child components connected to this device.
99 * @child_ports:child component port number the current component is
100 connected to.
101 * @nr_outport: number of output ports for this component.
102 */
103 struct coresight_platform_data {
104 int cpu;
105 const char *name;
106 int nr_inport;
107 int *outports;
108 const char **child_names;
109 int *child_ports;
110 int nr_outport;
111 };
112
113 /**
114 * struct coresight_desc - description of a component required from drivers
115 * @type: as defined by @coresight_dev_type.
116 * @subtype: as defined by @coresight_dev_subtype.
117 * @ops: generic operations for this component, as defined
118 by @coresight_ops.
119 * @pdata: platform data collected from DT.
120 * @dev: The device entity associated to this component.
121 * @groups: operations specific to this component. These will end up
122 in the component's sysfs sub-directory.
123 */
124 struct coresight_desc {
125 enum coresight_dev_type type;
126 union coresight_dev_subtype subtype;
127 const struct coresight_ops *ops;
128 struct coresight_platform_data *pdata;
129 struct device *dev;
130 const struct attribute_group **groups;
131 };
132
133 /**
134 * struct coresight_connection - representation of a single connection
135 * @outport: a connection's output port number.
136 * @chid_name: remote component's name.
137 * @child_port: remote component's port number @output is connected to.
138 * @child_dev: a @coresight_device representation of the component
139 connected to @outport.
140 */
141 struct coresight_connection {
142 int outport;
143 const char *child_name;
144 int child_port;
145 struct coresight_device *child_dev;
146 };
147
148 /**
149 * struct coresight_device - representation of a device as used by the framework
150 * @conns: array of coresight_connections associated to this component.
151 * @nr_inport: number of input port associated to this component.
152 * @nr_outport: number of output port associated to this component.
153 * @type: as defined by @coresight_dev_type.
154 * @subtype: as defined by @coresight_dev_subtype.
155 * @ops: generic operations for this component, as defined
156 by @coresight_ops.
157 * @dev: The device entity associated to this component.
158 * @refcnt: keep track of what is in use.
159 * @orphan: true if the component has connections that haven't been linked.
160 * @enable: 'true' if component is currently part of an active path.
161 * @activated: 'true' only if a _sink_ has been activated. A sink can be
162 activated but not yet enabled. Enabling for a _sink_
163 happens when a source has been selected for that it.
164 */
165 struct coresight_device {
166 struct coresight_connection *conns;
167 int nr_inport;
168 int nr_outport;
169 enum coresight_dev_type type;
170 union coresight_dev_subtype subtype;
171 const struct coresight_ops *ops;
172 struct device dev;
173 atomic_t *refcnt;
174 bool orphan;
175 bool enable; /* true only if configured as part of a path */
176 bool activated; /* true only if a sink is part of a path */
177 };
178
179 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
180
181 #define source_ops(csdev) csdev->ops->source_ops
182 #define sink_ops(csdev) csdev->ops->sink_ops
183 #define link_ops(csdev) csdev->ops->link_ops
184 #define helper_ops(csdev) csdev->ops->helper_ops
185
186 /**
187 * struct coresight_ops_sink - basic operations for a sink
188 * Operations available for sinks
189 * @enable: enables the sink.
190 * @disable: disables the sink.
191 * @alloc_buffer: initialises perf's ring buffer for trace collection.
192 * @free_buffer: release memory allocated in @get_config.
193 * @set_buffer: initialises buffer mechanic before a trace session.
194 * @reset_buffer: finalises buffer mechanic after a trace session.
195 * @update_buffer: update buffer pointers after a trace session.
196 */
197 struct coresight_ops_sink {
198 int (*enable)(struct coresight_device *csdev, u32 mode);
199 void (*disable)(struct coresight_device *csdev);
200 void *(*alloc_buffer)(struct coresight_device *csdev, int cpu,
201 void **pages, int nr_pages, bool overwrite);
202 void (*free_buffer)(void *config);
203 int (*set_buffer)(struct coresight_device *csdev,
204 struct perf_output_handle *handle,
205 void *sink_config);
206 unsigned long (*reset_buffer)(struct coresight_device *csdev,
207 struct perf_output_handle *handle,
208 void *sink_config);
209 void (*update_buffer)(struct coresight_device *csdev,
210 struct perf_output_handle *handle,
211 void *sink_config);
212 };
213
214 /**
215 * struct coresight_ops_link - basic operations for a link
216 * Operations available for links.
217 * @enable: enables flow between iport and oport.
218 * @disable: disables flow between iport and oport.
219 */
220 struct coresight_ops_link {
221 int (*enable)(struct coresight_device *csdev, int iport, int oport);
222 void (*disable)(struct coresight_device *csdev, int iport, int oport);
223 };
224
225 /**
226 * struct coresight_ops_source - basic operations for a source
227 * Operations available for sources.
228 * @cpu_id: returns the value of the CPU number this component
229 * is associated to.
230 * @trace_id: returns the value of the component's trace ID as known
231 * to the HW.
232 * @enable: enables tracing for a source.
233 * @disable: disables tracing for a source.
234 */
235 struct coresight_ops_source {
236 int (*cpu_id)(struct coresight_device *csdev);
237 int (*trace_id)(struct coresight_device *csdev);
238 int (*enable)(struct coresight_device *csdev,
239 struct perf_event *event, u32 mode);
240 void (*disable)(struct coresight_device *csdev,
241 struct perf_event *event);
242 };
243
244 /**
245 * struct coresight_ops_helper - Operations for a helper device.
246 *
247 * All operations could pass in a device specific data, which could
248 * help the helper device to determine what to do.
249 *
250 * @enable : Enable the device
251 * @disable : Disable the device
252 */
253 struct coresight_ops_helper {
254 int (*enable)(struct coresight_device *csdev, void *data);
255 int (*disable)(struct coresight_device *csdev, void *data);
256 };
257
258 struct coresight_ops {
259 const struct coresight_ops_sink *sink_ops;
260 const struct coresight_ops_link *link_ops;
261 const struct coresight_ops_source *source_ops;
262 const struct coresight_ops_helper *helper_ops;
263 };
264
265 #ifdef CONFIG_CORESIGHT
266 extern struct coresight_device *
267 coresight_register(struct coresight_desc *desc);
268 extern void coresight_unregister(struct coresight_device *csdev);
269 extern int coresight_enable(struct coresight_device *csdev);
270 extern void coresight_disable(struct coresight_device *csdev);
271 extern int coresight_timeout(void __iomem *addr, u32 offset,
272 int position, int value);
273 #else
274 static inline struct coresight_device *
coresight_register(struct coresight_desc * desc)275 coresight_register(struct coresight_desc *desc) { return NULL; }
coresight_unregister(struct coresight_device * csdev)276 static inline void coresight_unregister(struct coresight_device *csdev) {}
277 static inline int
coresight_enable(struct coresight_device * csdev)278 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
coresight_disable(struct coresight_device * csdev)279 static inline void coresight_disable(struct coresight_device *csdev) {}
coresight_timeout(void __iomem * addr,u32 offset,int position,int value)280 static inline int coresight_timeout(void __iomem *addr, u32 offset,
281 int position, int value) { return 1; }
282 #endif
283
284 #ifdef CONFIG_OF
285 extern int of_coresight_get_cpu(const struct device_node *node);
286 extern struct coresight_platform_data *
287 of_get_coresight_platform_data(struct device *dev,
288 const struct device_node *node);
289 #else
of_coresight_get_cpu(const struct device_node * node)290 static inline int of_coresight_get_cpu(const struct device_node *node)
291 { return 0; }
of_get_coresight_platform_data(struct device * dev,const struct device_node * node)292 static inline struct coresight_platform_data *of_get_coresight_platform_data(
293 struct device *dev, const struct device_node *node) { return NULL; }
294 #endif
295
296 #endif
297