1 /*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched/signal.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/slab.h>
23
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/iopoll.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/i2c.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31
32 #include <asm/mpc52xx.h>
33 #include <asm/mpc85xx.h>
34 #include <sysdev/fsl_soc.h>
35
36 #define DRV_NAME "mpc-i2c"
37
38 #define MPC_I2C_CLOCK_LEGACY 0
39 #define MPC_I2C_CLOCK_PRESERVE (~0U)
40
41 #define MPC_I2C_FDR 0x04
42 #define MPC_I2C_CR 0x08
43 #define MPC_I2C_SR 0x0c
44 #define MPC_I2C_DR 0x10
45 #define MPC_I2C_DFSRR 0x14
46
47 #define CCR_MEN 0x80
48 #define CCR_MIEN 0x40
49 #define CCR_MSTA 0x20
50 #define CCR_MTX 0x10
51 #define CCR_TXAK 0x08
52 #define CCR_RSTA 0x04
53 #define CCR_RSVD 0x02
54
55 #define CSR_MCF 0x80
56 #define CSR_MAAS 0x40
57 #define CSR_MBB 0x20
58 #define CSR_MAL 0x10
59 #define CSR_SRW 0x04
60 #define CSR_MIF 0x02
61 #define CSR_RXAK 0x01
62
63 struct mpc_i2c {
64 struct device *dev;
65 void __iomem *base;
66 u32 interrupt;
67 wait_queue_head_t queue;
68 struct i2c_adapter adap;
69 int irq;
70 u32 real_clk;
71 #ifdef CONFIG_PM_SLEEP
72 u8 fdr, dfsrr;
73 #endif
74 struct clk *clk_per;
75 bool has_errata_A004447;
76 };
77
78 struct mpc_i2c_divider {
79 u16 divider;
80 u16 fdr; /* including dfsrr */
81 };
82
83 struct mpc_i2c_data {
84 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
85 };
86
writeccr(struct mpc_i2c * i2c,u32 x)87 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
88 {
89 writeb(x, i2c->base + MPC_I2C_CR);
90 }
91
mpc_i2c_isr(int irq,void * dev_id)92 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
93 {
94 struct mpc_i2c *i2c = dev_id;
95 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
96 /* Read again to allow register to stabilise */
97 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
98 writeb(0, i2c->base + MPC_I2C_SR);
99 wake_up(&i2c->queue);
100 return IRQ_HANDLED;
101 }
102 return IRQ_NONE;
103 }
104
105 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
106 * the bus, because it wants to send ACK.
107 * Following sequence of enabling/disabling and sending start/stop generates
108 * the 9 pulses, each with a START then ending with STOP, so it's all OK.
109 */
mpc_i2c_fixup(struct mpc_i2c * i2c)110 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
111 {
112 int k;
113 unsigned long flags;
114
115 for (k = 9; k; k--) {
116 writeccr(i2c, 0);
117 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
118 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
119 readb(i2c->base + MPC_I2C_DR); /* init xfer */
120 udelay(15); /* let it hit the bus */
121 local_irq_save(flags); /* should not be delayed further */
122 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
123 readb(i2c->base + MPC_I2C_DR);
124 if (k != 1)
125 udelay(5);
126 local_irq_restore(flags);
127 }
128 writeccr(i2c, CCR_MEN); /* Initiate STOP */
129 readb(i2c->base + MPC_I2C_DR);
130 udelay(15); /* Let STOP propagate */
131 writeccr(i2c, 0);
132 }
133
i2c_wait(struct mpc_i2c * i2c,unsigned timeout,int writing)134 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
135 {
136 unsigned long orig_jiffies = jiffies;
137 u32 cmd_err;
138 int result = 0;
139
140 if (!i2c->irq) {
141 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
142 schedule();
143 if (time_after(jiffies, orig_jiffies + timeout)) {
144 dev_dbg(i2c->dev, "timeout\n");
145 writeccr(i2c, 0);
146 result = -ETIMEDOUT;
147 break;
148 }
149 }
150 cmd_err = readb(i2c->base + MPC_I2C_SR);
151 writeb(0, i2c->base + MPC_I2C_SR);
152 } else {
153 /* Interrupt mode */
154 result = wait_event_timeout(i2c->queue,
155 (i2c->interrupt & CSR_MIF), timeout);
156
157 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
158 dev_dbg(i2c->dev, "wait timeout\n");
159 writeccr(i2c, 0);
160 result = -ETIMEDOUT;
161 }
162
163 cmd_err = i2c->interrupt;
164 i2c->interrupt = 0;
165 }
166
167 if (result < 0)
168 return result;
169
170 if (!(cmd_err & CSR_MCF)) {
171 dev_dbg(i2c->dev, "unfinished\n");
172 return -EIO;
173 }
174
175 if (cmd_err & CSR_MAL) {
176 dev_dbg(i2c->dev, "MAL\n");
177 return -EAGAIN;
178 }
179
180 if (writing && (cmd_err & CSR_RXAK)) {
181 dev_dbg(i2c->dev, "No RXAK\n");
182 /* generate stop */
183 writeccr(i2c, CCR_MEN);
184 return -ENXIO;
185 }
186 return 0;
187 }
188
i2c_mpc_wait_sr(struct mpc_i2c * i2c,int mask)189 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
190 {
191 void __iomem *addr = i2c->base + MPC_I2C_SR;
192 u8 val;
193
194 return readb_poll_timeout(addr, val, val & mask, 0, 100);
195 }
196
197 /*
198 * Workaround for Erratum A004447. From the P2040CE Rev Q
199 *
200 * 1. Set up the frequency divider and sampling rate.
201 * 2. I2CCR - a0h
202 * 3. Poll for I2CSR[MBB] to get set.
203 * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
204 * step 5. If MAL is not set, then go to step 13.
205 * 5. I2CCR - 00h
206 * 6. I2CCR - 22h
207 * 7. I2CCR - a2h
208 * 8. Poll for I2CSR[MBB] to get set.
209 * 9. Issue read to I2CDR.
210 * 10. Poll for I2CSR[MIF] to be set.
211 * 11. I2CCR - 82h
212 * 12. Workaround complete. Skip the next steps.
213 * 13. Issue read to I2CDR.
214 * 14. Poll for I2CSR[MIF] to be set.
215 * 15. I2CCR - 80h
216 */
mpc_i2c_fixup_A004447(struct mpc_i2c * i2c)217 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
218 {
219 int ret;
220 u32 val;
221
222 writeccr(i2c, CCR_MEN | CCR_MSTA);
223 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
224 if (ret) {
225 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
226 return;
227 }
228
229 val = readb(i2c->base + MPC_I2C_SR);
230
231 if (val & CSR_MAL) {
232 writeccr(i2c, 0x00);
233 writeccr(i2c, CCR_MSTA | CCR_RSVD);
234 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
235 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
236 if (ret) {
237 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
238 return;
239 }
240 val = readb(i2c->base + MPC_I2C_DR);
241 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
242 if (ret) {
243 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
244 return;
245 }
246 writeccr(i2c, CCR_MEN | CCR_RSVD);
247 } else {
248 val = readb(i2c->base + MPC_I2C_DR);
249 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
250 if (ret) {
251 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
252 return;
253 }
254 writeccr(i2c, CCR_MEN);
255 }
256 }
257
258 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
259 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
260 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
261 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
262 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
263 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
264 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
265 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
266 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
267 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
268 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
269 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
270 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
271 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
272 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
273 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
274 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
275 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
276 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
277 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
278 };
279
mpc_i2c_get_fdr_52xx(struct device_node * node,u32 clock,u32 * real_clk)280 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
281 u32 *real_clk)
282 {
283 const struct mpc_i2c_divider *div = NULL;
284 unsigned int pvr = mfspr(SPRN_PVR);
285 u32 divider;
286 int i;
287
288 if (clock == MPC_I2C_CLOCK_LEGACY) {
289 /* see below - default fdr = 0x3f -> div = 2048 */
290 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
291 return -EINVAL;
292 }
293
294 /* Determine divider value */
295 divider = mpc5xxx_get_bus_frequency(node) / clock;
296
297 /*
298 * We want to choose an FDR/DFSR that generates an I2C bus speed that
299 * is equal to or lower than the requested speed.
300 */
301 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
302 div = &mpc_i2c_dividers_52xx[i];
303 /* Old MPC5200 rev A CPUs do not support the high bits */
304 if (div->fdr & 0xc0 && pvr == 0x80822011)
305 continue;
306 if (div->divider >= divider)
307 break;
308 }
309
310 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
311 return (int)div->fdr;
312 }
313
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)314 static void mpc_i2c_setup_52xx(struct device_node *node,
315 struct mpc_i2c *i2c,
316 u32 clock)
317 {
318 int ret, fdr;
319
320 if (clock == MPC_I2C_CLOCK_PRESERVE) {
321 dev_dbg(i2c->dev, "using fdr %d\n",
322 readb(i2c->base + MPC_I2C_FDR));
323 return;
324 }
325
326 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
327 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
328
329 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
330
331 if (ret >= 0)
332 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
333 fdr);
334 }
335 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)336 static void mpc_i2c_setup_52xx(struct device_node *node,
337 struct mpc_i2c *i2c,
338 u32 clock)
339 {
340 }
341 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
342
343 #ifdef CONFIG_PPC_MPC512x
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)344 static void mpc_i2c_setup_512x(struct device_node *node,
345 struct mpc_i2c *i2c,
346 u32 clock)
347 {
348 struct device_node *node_ctrl;
349 void __iomem *ctrl;
350 const u32 *pval;
351 u32 idx;
352
353 /* Enable I2C interrupts for mpc5121 */
354 node_ctrl = of_find_compatible_node(NULL, NULL,
355 "fsl,mpc5121-i2c-ctrl");
356 if (node_ctrl) {
357 ctrl = of_iomap(node_ctrl, 0);
358 if (ctrl) {
359 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
360 pval = of_get_property(node, "reg", NULL);
361 idx = (*pval & 0xff) / 0x20;
362 setbits32(ctrl, 1 << (24 + idx * 2));
363 iounmap(ctrl);
364 }
365 of_node_put(node_ctrl);
366 }
367
368 /* The clock setup for the 52xx works also fine for the 512x */
369 mpc_i2c_setup_52xx(node, i2c, clock);
370 }
371 #else /* CONFIG_PPC_MPC512x */
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)372 static void mpc_i2c_setup_512x(struct device_node *node,
373 struct mpc_i2c *i2c,
374 u32 clock)
375 {
376 }
377 #endif /* CONFIG_PPC_MPC512x */
378
379 #ifdef CONFIG_FSL_SOC
380 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
381 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
382 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
383 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
384 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
385 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
386 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
387 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
388 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
389 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
390 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
391 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
392 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
393 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
394 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
395 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
396 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
397 {49152, 0x011e}, {61440, 0x011f}
398 };
399
mpc_i2c_get_sec_cfg_8xxx(void)400 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
401 {
402 struct device_node *node;
403 u32 __iomem *reg;
404 u32 val = 0;
405
406 node = of_find_node_by_name(NULL, "global-utilities");
407 if (node) {
408 const u32 *prop = of_get_property(node, "reg", NULL);
409 if (prop) {
410 /*
411 * Map and check POR Device Status Register 2
412 * (PORDEVSR2) at 0xE0014. Note than while MPC8533
413 * and MPC8544 indicate SEC frequency ratio
414 * configuration as bit 26 in PORDEVSR2, other MPC8xxx
415 * parts may store it differently or may not have it
416 * at all.
417 */
418 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
419 if (!reg)
420 printk(KERN_ERR
421 "Error: couldn't map PORDEVSR2\n");
422 else
423 val = in_be32(reg) & 0x00000020; /* sec-cfg */
424 iounmap(reg);
425 }
426 }
427 of_node_put(node);
428
429 return val;
430 }
431
mpc_i2c_get_prescaler_8xxx(void)432 static u32 mpc_i2c_get_prescaler_8xxx(void)
433 {
434 /*
435 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
436 * may have prescaler 1, 2, or 3, depending on the power-on
437 * configuration.
438 */
439 u32 prescaler = 1;
440
441 /* mpc85xx */
442 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
443 || pvr_version_is(PVR_VER_E500MC)
444 || pvr_version_is(PVR_VER_E5500)
445 || pvr_version_is(PVR_VER_E6500)) {
446 unsigned int svr = mfspr(SPRN_SVR);
447
448 if ((SVR_SOC_VER(svr) == SVR_8540)
449 || (SVR_SOC_VER(svr) == SVR_8541)
450 || (SVR_SOC_VER(svr) == SVR_8560)
451 || (SVR_SOC_VER(svr) == SVR_8555)
452 || (SVR_SOC_VER(svr) == SVR_8610))
453 /* the above 85xx SoCs have prescaler 1 */
454 prescaler = 1;
455 else if ((SVR_SOC_VER(svr) == SVR_8533)
456 || (SVR_SOC_VER(svr) == SVR_8544))
457 /* the above 85xx SoCs have prescaler 3 or 2 */
458 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
459 else
460 /* all the other 85xx have prescaler 2 */
461 prescaler = 2;
462 }
463
464 return prescaler;
465 }
466
mpc_i2c_get_fdr_8xxx(struct device_node * node,u32 clock,u32 * real_clk)467 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
468 u32 *real_clk)
469 {
470 const struct mpc_i2c_divider *div = NULL;
471 u32 prescaler = mpc_i2c_get_prescaler_8xxx();
472 u32 divider;
473 int i;
474
475 if (clock == MPC_I2C_CLOCK_LEGACY) {
476 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
477 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
478 return -EINVAL;
479 }
480
481 divider = fsl_get_sys_freq() / clock / prescaler;
482
483 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
484 fsl_get_sys_freq(), clock, divider);
485
486 /*
487 * We want to choose an FDR/DFSR that generates an I2C bus speed that
488 * is equal to or lower than the requested speed.
489 */
490 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
491 div = &mpc_i2c_dividers_8xxx[i];
492 if (div->divider >= divider)
493 break;
494 }
495
496 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
497 return div ? (int)div->fdr : -EINVAL;
498 }
499
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)500 static void mpc_i2c_setup_8xxx(struct device_node *node,
501 struct mpc_i2c *i2c,
502 u32 clock)
503 {
504 int ret, fdr;
505
506 if (clock == MPC_I2C_CLOCK_PRESERVE) {
507 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
508 readb(i2c->base + MPC_I2C_DFSRR),
509 readb(i2c->base + MPC_I2C_FDR));
510 return;
511 }
512
513 ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
514 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
515
516 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
517 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
518
519 if (ret >= 0)
520 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
521 i2c->real_clk, fdr >> 8, fdr & 0xff);
522 }
523
524 #else /* !CONFIG_FSL_SOC */
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)525 static void mpc_i2c_setup_8xxx(struct device_node *node,
526 struct mpc_i2c *i2c,
527 u32 clock)
528 {
529 }
530 #endif /* CONFIG_FSL_SOC */
531
mpc_i2c_start(struct mpc_i2c * i2c)532 static void mpc_i2c_start(struct mpc_i2c *i2c)
533 {
534 /* Clear arbitration */
535 writeb(0, i2c->base + MPC_I2C_SR);
536 /* Start with MEN */
537 writeccr(i2c, CCR_MEN);
538 }
539
mpc_i2c_stop(struct mpc_i2c * i2c)540 static void mpc_i2c_stop(struct mpc_i2c *i2c)
541 {
542 writeccr(i2c, CCR_MEN);
543 }
544
mpc_write(struct mpc_i2c * i2c,int target,const u8 * data,int length,int restart)545 static int mpc_write(struct mpc_i2c *i2c, int target,
546 const u8 *data, int length, int restart)
547 {
548 int i, result;
549 unsigned timeout = i2c->adap.timeout;
550 u32 flags = restart ? CCR_RSTA : 0;
551
552 /* Start as master */
553 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
554 /* Write target byte */
555 writeb((target << 1), i2c->base + MPC_I2C_DR);
556
557 result = i2c_wait(i2c, timeout, 1);
558 if (result < 0)
559 return result;
560
561 for (i = 0; i < length; i++) {
562 /* Write data byte */
563 writeb(data[i], i2c->base + MPC_I2C_DR);
564
565 result = i2c_wait(i2c, timeout, 1);
566 if (result < 0)
567 return result;
568 }
569
570 return 0;
571 }
572
mpc_read(struct mpc_i2c * i2c,int target,u8 * data,int length,int restart,bool recv_len)573 static int mpc_read(struct mpc_i2c *i2c, int target,
574 u8 *data, int length, int restart, bool recv_len)
575 {
576 unsigned timeout = i2c->adap.timeout;
577 int i, result;
578 u32 flags = restart ? CCR_RSTA : 0;
579
580 /* Switch to read - restart */
581 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
582 /* Write target address byte - this time with the read flag set */
583 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
584
585 result = i2c_wait(i2c, timeout, 1);
586 if (result < 0)
587 return result;
588
589 if (length) {
590 if (length == 1 && !recv_len)
591 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
592 else
593 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
594 /* Dummy read */
595 readb(i2c->base + MPC_I2C_DR);
596 }
597
598 for (i = 0; i < length; i++) {
599 u8 byte;
600
601 result = i2c_wait(i2c, timeout, 0);
602 if (result < 0)
603 return result;
604
605 /*
606 * For block reads, we have to know the total length (1st byte)
607 * before we can determine if we are done.
608 */
609 if (i || !recv_len) {
610 /* Generate txack on next to last byte */
611 if (i == length - 2)
612 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
613 | CCR_TXAK);
614 /* Do not generate stop on last byte */
615 if (i == length - 1)
616 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
617 | CCR_MTX);
618 }
619
620 byte = readb(i2c->base + MPC_I2C_DR);
621
622 /*
623 * Adjust length if first received byte is length.
624 * The length is 1 length byte plus actually data length
625 */
626 if (i == 0 && recv_len) {
627 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
628 return -EPROTO;
629 length += byte;
630 /*
631 * For block reads, generate txack here if data length
632 * is 1 byte (total length is 2 bytes).
633 */
634 if (length == 2)
635 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
636 | CCR_TXAK);
637 }
638 data[i] = byte;
639 }
640
641 return length;
642 }
643
mpc_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)644 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
645 {
646 struct i2c_msg *pmsg;
647 int i;
648 int ret = 0;
649 unsigned long orig_jiffies = jiffies;
650 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
651
652 mpc_i2c_start(i2c);
653
654 /* Allow bus up to 1s to become not busy */
655 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
656 if (signal_pending(current)) {
657 dev_dbg(i2c->dev, "Interrupted\n");
658 writeccr(i2c, 0);
659 return -EINTR;
660 }
661 if (time_after(jiffies, orig_jiffies + HZ)) {
662 u8 status = readb(i2c->base + MPC_I2C_SR);
663
664 dev_dbg(i2c->dev, "timeout\n");
665 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
666 writeb(status & ~CSR_MAL,
667 i2c->base + MPC_I2C_SR);
668 i2c_recover_bus(&i2c->adap);
669 }
670 return -EIO;
671 }
672 schedule();
673 }
674
675 for (i = 0; ret >= 0 && i < num; i++) {
676 pmsg = &msgs[i];
677 dev_dbg(i2c->dev,
678 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
679 pmsg->flags & I2C_M_RD ? "read" : "write",
680 pmsg->len, pmsg->addr, i + 1, num);
681 if (pmsg->flags & I2C_M_RD) {
682 bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
683
684 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
685 recv_len);
686 if (recv_len && ret > 0)
687 pmsg->len = ret;
688 } else {
689 ret =
690 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
691 }
692 }
693 mpc_i2c_stop(i2c); /* Initiate STOP */
694 orig_jiffies = jiffies;
695 /* Wait until STOP is seen, allow up to 1 s */
696 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
697 if (time_after(jiffies, orig_jiffies + HZ)) {
698 u8 status = readb(i2c->base + MPC_I2C_SR);
699
700 dev_dbg(i2c->dev, "timeout\n");
701 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
702 writeb(status & ~CSR_MAL,
703 i2c->base + MPC_I2C_SR);
704 i2c_recover_bus(&i2c->adap);
705 }
706 return -EIO;
707 }
708 cond_resched();
709 }
710 return (ret < 0) ? ret : num;
711 }
712
mpc_functionality(struct i2c_adapter * adap)713 static u32 mpc_functionality(struct i2c_adapter *adap)
714 {
715 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
716 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
717 }
718
fsl_i2c_bus_recovery(struct i2c_adapter * adap)719 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
720 {
721 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
722
723 if (i2c->has_errata_A004447)
724 mpc_i2c_fixup_A004447(i2c);
725 else
726 mpc_i2c_fixup(i2c);
727
728 return 0;
729 }
730
731 static const struct i2c_algorithm mpc_algo = {
732 .master_xfer = mpc_xfer,
733 .functionality = mpc_functionality,
734 };
735
736 static struct i2c_adapter mpc_ops = {
737 .owner = THIS_MODULE,
738 .algo = &mpc_algo,
739 .timeout = HZ,
740 };
741
742 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
743 .recover_bus = fsl_i2c_bus_recovery,
744 };
745
746 static const struct of_device_id mpc_i2c_of_match[];
fsl_i2c_probe(struct platform_device * op)747 static int fsl_i2c_probe(struct platform_device *op)
748 {
749 const struct of_device_id *match;
750 struct mpc_i2c *i2c;
751 const u32 *prop;
752 u32 clock = MPC_I2C_CLOCK_LEGACY;
753 int result = 0;
754 int plen;
755 struct resource res;
756 struct clk *clk;
757 int err;
758
759 match = of_match_device(mpc_i2c_of_match, &op->dev);
760 if (!match)
761 return -EINVAL;
762
763 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
764 if (!i2c)
765 return -ENOMEM;
766
767 i2c->dev = &op->dev; /* for debug and error output */
768
769 init_waitqueue_head(&i2c->queue);
770
771 i2c->base = of_iomap(op->dev.of_node, 0);
772 if (!i2c->base) {
773 dev_err(i2c->dev, "failed to map controller\n");
774 result = -ENOMEM;
775 goto fail_map;
776 }
777
778 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
779 if (i2c->irq) { /* no i2c->irq implies polling */
780 result = request_irq(i2c->irq, mpc_i2c_isr,
781 IRQF_SHARED, "i2c-mpc", i2c);
782 if (result < 0) {
783 dev_err(i2c->dev, "failed to attach interrupt\n");
784 goto fail_request;
785 }
786 }
787
788 /*
789 * enable clock for the I2C peripheral (non fatal),
790 * keep a reference upon successful allocation
791 */
792 clk = devm_clk_get(&op->dev, NULL);
793 if (!IS_ERR(clk)) {
794 err = clk_prepare_enable(clk);
795 if (err) {
796 dev_err(&op->dev, "failed to enable clock\n");
797 goto fail_request;
798 } else {
799 i2c->clk_per = clk;
800 }
801 }
802
803 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
804 clock = MPC_I2C_CLOCK_PRESERVE;
805 } else {
806 prop = of_get_property(op->dev.of_node, "clock-frequency",
807 &plen);
808 if (prop && plen == sizeof(u32))
809 clock = *prop;
810 }
811
812 if (match->data) {
813 const struct mpc_i2c_data *data = match->data;
814 data->setup(op->dev.of_node, i2c, clock);
815 } else {
816 /* Backwards compatibility */
817 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
818 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
819 }
820
821 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
822 if (prop && plen == sizeof(u32)) {
823 mpc_ops.timeout = *prop * HZ / 1000000;
824 if (mpc_ops.timeout < 5)
825 mpc_ops.timeout = 5;
826 }
827 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
828
829 platform_set_drvdata(op, i2c);
830 if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
831 i2c->has_errata_A004447 = true;
832
833 i2c->adap = mpc_ops;
834 of_address_to_resource(op->dev.of_node, 0, &res);
835 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
836 "MPC adapter at 0x%llx", (unsigned long long)res.start);
837 i2c_set_adapdata(&i2c->adap, i2c);
838 i2c->adap.dev.parent = &op->dev;
839 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
840 i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
841
842 result = i2c_add_adapter(&i2c->adap);
843 if (result < 0)
844 goto fail_add;
845
846 return result;
847
848 fail_add:
849 if (i2c->clk_per)
850 clk_disable_unprepare(i2c->clk_per);
851 free_irq(i2c->irq, i2c);
852 fail_request:
853 irq_dispose_mapping(i2c->irq);
854 iounmap(i2c->base);
855 fail_map:
856 kfree(i2c);
857 return result;
858 };
859
fsl_i2c_remove(struct platform_device * op)860 static int fsl_i2c_remove(struct platform_device *op)
861 {
862 struct mpc_i2c *i2c = platform_get_drvdata(op);
863
864 i2c_del_adapter(&i2c->adap);
865
866 if (i2c->clk_per)
867 clk_disable_unprepare(i2c->clk_per);
868
869 if (i2c->irq)
870 free_irq(i2c->irq, i2c);
871
872 irq_dispose_mapping(i2c->irq);
873 iounmap(i2c->base);
874 kfree(i2c);
875 return 0;
876 };
877
878 #ifdef CONFIG_PM_SLEEP
mpc_i2c_suspend(struct device * dev)879 static int mpc_i2c_suspend(struct device *dev)
880 {
881 struct mpc_i2c *i2c = dev_get_drvdata(dev);
882
883 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
884 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
885
886 return 0;
887 }
888
mpc_i2c_resume(struct device * dev)889 static int mpc_i2c_resume(struct device *dev)
890 {
891 struct mpc_i2c *i2c = dev_get_drvdata(dev);
892
893 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
894 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
895
896 return 0;
897 }
898
899 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
900 #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
901 #else
902 #define MPC_I2C_PM_OPS NULL
903 #endif
904
905 static const struct mpc_i2c_data mpc_i2c_data_512x = {
906 .setup = mpc_i2c_setup_512x,
907 };
908
909 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
910 .setup = mpc_i2c_setup_52xx,
911 };
912
913 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
914 .setup = mpc_i2c_setup_8xxx,
915 };
916
917 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
918 .setup = mpc_i2c_setup_8xxx,
919 };
920
921 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
922 .setup = mpc_i2c_setup_8xxx,
923 };
924
925 static const struct of_device_id mpc_i2c_of_match[] = {
926 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
927 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
928 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
929 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
930 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
931 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
932 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
933 /* Backward compatibility */
934 {.compatible = "fsl-i2c", },
935 {},
936 };
937 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
938
939 /* Structure for a device driver */
940 static struct platform_driver mpc_i2c_driver = {
941 .probe = fsl_i2c_probe,
942 .remove = fsl_i2c_remove,
943 .driver = {
944 .name = DRV_NAME,
945 .of_match_table = mpc_i2c_of_match,
946 .pm = MPC_I2C_PM_OPS,
947 },
948 };
949
950 module_platform_driver(mpc_i2c_driver);
951
952 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
953 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
954 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
955 MODULE_LICENSE("GPL");
956