1 /*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 */
10
11 #include <linux/module.h>
12 #include <linux/ctype.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/slab.h>
17 #include <linux/mmzone.h>
18 #include <linux/edac.h>
19 #include <asm/cpu_device_id.h>
20 #include <asm/msr.h>
21 #include "edac_module.h"
22 #include "mce_amd.h"
23
24 #define amd64_info(fmt, arg...) \
25 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
26
27 #define amd64_warn(fmt, arg...) \
28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
29
30 #define amd64_err(fmt, arg...) \
31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
32
33 #define amd64_mc_warn(mci, fmt, arg...) \
34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
35
36 #define amd64_mc_err(mci, fmt, arg...) \
37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
38
39 /*
40 * Throughout the comments in this code, the following terms are used:
41 *
42 * SysAddr, DramAddr, and InputAddr
43 *
44 * These terms come directly from the amd64 documentation
45 * (AMD publication #26094). They are defined as follows:
46 *
47 * SysAddr:
48 * This is a physical address generated by a CPU core or a device
49 * doing DMA. If generated by a CPU core, a SysAddr is the result of
50 * a virtual to physical address translation by the CPU core's address
51 * translation mechanism (MMU).
52 *
53 * DramAddr:
54 * A DramAddr is derived from a SysAddr by subtracting an offset that
55 * depends on which node the SysAddr maps to and whether the SysAddr
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
58 * determine which node a SysAddr maps to.
59 *
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
61 * is within the range of addresses specified by this register, then
62 * a value x from the DHAR is subtracted from the SysAddr to produce a
63 * DramAddr. Here, x represents the base address for the node that
64 * the SysAddr maps to plus an offset due to memory hoisting. See
65 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
66 * sys_addr_to_dram_addr() below for more information.
67 *
68 * If the SysAddr is not affected by the DHAR then a value y is
69 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
70 * base address for the node that the SysAddr maps to. See section
71 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
72 * information.
73 *
74 * InputAddr:
75 * A DramAddr is translated to an InputAddr before being passed to the
76 * memory controller for the node that the DramAddr is associated
77 * with. The memory controller then maps the InputAddr to a csrow.
78 * If node interleaving is not in use, then the InputAddr has the same
79 * value as the DramAddr. Otherwise, the InputAddr is produced by
80 * discarding the bits used for node interleaving from the DramAddr.
81 * See section 3.4.4 for more information.
82 *
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
85 * sections 3.5.4 and 3.5.5 for more information.
86 */
87
88 #define EDAC_AMD64_VERSION "3.5.0"
89 #define EDAC_MOD_STR "amd64_edac"
90
91 /* Extended Model from CPUID, for CPU Revision numbers */
92 #define K8_REV_D 1
93 #define K8_REV_E 2
94 #define K8_REV_F 4
95
96 /* Hardware limit on ChipSelect rows per MC and processors per system */
97 #define NUM_CHIPSELECTS 8
98 #define DRAM_RANGES 8
99
100 #define ON true
101 #define OFF false
102
103 /*
104 * PCI-defined configuration space registers
105 */
106 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
107 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
108 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
110 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
112 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
113 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
114 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
116 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
117 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
118 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
119 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
120 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
121 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
122
123 /*
124 * Function 1 - Address Map
125 */
126 #define DRAM_BASE_LO 0x40
127 #define DRAM_LIMIT_LO 0x44
128
129 /*
130 * F15 M30h D18F1x2[1C:00]
131 */
132 #define DRAM_CONT_BASE 0x200
133 #define DRAM_CONT_LIMIT 0x204
134
135 /*
136 * F15 M30h D18F1x2[4C:40]
137 */
138 #define DRAM_CONT_HIGH_OFF 0x240
139
140 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
141 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
142 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
143
144 #define DHAR 0xf0
145 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
146 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
147 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
148
149 /* NOTE: Extra mask bit vs K8 */
150 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
151
152 #define DCT_CFG_SEL 0x10C
153
154 #define DRAM_LOCAL_NODE_BASE 0x120
155 #define DRAM_LOCAL_NODE_LIM 0x124
156
157 #define DRAM_BASE_HI 0x140
158 #define DRAM_LIMIT_HI 0x144
159
160
161 /*
162 * Function 2 - DRAM controller
163 */
164 #define DCSB0 0x40
165 #define DCSB1 0x140
166 #define DCSB_CS_ENABLE BIT(0)
167
168 #define DCSM0 0x60
169 #define DCSM1 0x160
170
171 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
172
173 #define DRAM_CONTROL 0x78
174
175 #define DBAM0 0x80
176 #define DBAM1 0x180
177
178 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
179 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
180
181 #define DBAM_MAX_VALUE 11
182
183 #define DCLR0 0x90
184 #define DCLR1 0x190
185 #define REVE_WIDTH_128 BIT(16)
186 #define WIDTH_128 BIT(11)
187
188 #define DCHR0 0x94
189 #define DCHR1 0x194
190 #define DDR3_MODE BIT(8)
191
192 #define DCT_SEL_LO 0x110
193 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
194 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
195
196 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
197
198 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
199 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
200
201 #define SWAP_INTLV_REG 0x10c
202
203 #define DCT_SEL_HI 0x114
204
205 #define F15H_M60H_SCRCTRL 0x1C8
206 #define F17H_SCR_BASE_ADDR 0x48
207 #define F17H_SCR_LIMIT_ADDR 0x4C
208
209 /*
210 * Function 3 - Misc Control
211 */
212 #define NBCTL 0x40
213
214 #define NBCFG 0x44
215 #define NBCFG_CHIPKILL BIT(23)
216 #define NBCFG_ECC_ENABLE BIT(22)
217
218 /* F3x48: NBSL */
219 #define F10_NBSL_EXT_ERR_ECC 0x8
220 #define NBSL_PP_OBS 0x2
221
222 #define SCRCTRL 0x58
223
224 #define F10_ONLINE_SPARE 0xB0
225 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
226 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
227
228 #define F10_NB_ARRAY_ADDR 0xB8
229 #define F10_NB_ARRAY_DRAM BIT(31)
230
231 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
232 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
233
234 #define F10_NB_ARRAY_DATA 0xBC
235 #define F10_NB_ARR_ECC_WR_REQ BIT(17)
236 #define SET_NB_DRAM_INJECTION_WRITE(inj) \
237 (BIT(((inj.word) & 0xF) + 20) | \
238 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
239 #define SET_NB_DRAM_INJECTION_READ(inj) \
240 (BIT(((inj.word) & 0xF) + 20) | \
241 BIT(16) | inj.bit_map)
242
243
244 #define NBCAP 0xE8
245 #define NBCAP_CHIPKILL BIT(4)
246 #define NBCAP_SECDED BIT(3)
247 #define NBCAP_DCT_DUAL BIT(0)
248
249 #define EXT_NB_MCA_CFG 0x180
250
251 /* MSRs */
252 #define MSR_MCGCTL_NBE BIT(4)
253
254 /* F17h */
255
256 /* F0: */
257 #define DF_DHAR 0x104
258
259 /* UMC CH register offsets */
260 #define UMCCH_BASE_ADDR 0x0
261 #define UMCCH_ADDR_MASK 0x20
262 #define UMCCH_ADDR_CFG 0x30
263 #define UMCCH_DIMM_CFG 0x80
264 #define UMCCH_UMC_CFG 0x100
265 #define UMCCH_SDP_CTRL 0x104
266 #define UMCCH_ECC_CTRL 0x14C
267 #define UMCCH_ECC_BAD_SYMBOL 0xD90
268 #define UMCCH_UMC_CAP 0xDF0
269 #define UMCCH_UMC_CAP_HI 0xDF4
270
271 /* UMC CH bitfields */
272 #define UMC_ECC_CHIPKILL_CAP BIT(31)
273 #define UMC_ECC_ENABLED BIT(30)
274
275 #define UMC_SDP_INIT BIT(31)
276
277 #define NUM_UMCS 2
278
279 enum amd_families {
280 K8_CPUS = 0,
281 F10_CPUS,
282 F15_CPUS,
283 F15_M30H_CPUS,
284 F15_M60H_CPUS,
285 F16_CPUS,
286 F16_M30H_CPUS,
287 F17_CPUS,
288 F17_M10H_CPUS,
289 F17_M30H_CPUS,
290 NUM_FAMILIES,
291 };
292
293 /* Error injection control structure */
294 struct error_injection {
295 u32 section;
296 u32 word;
297 u32 bit_map;
298 };
299
300 /* low and high part of PCI config space regs */
301 struct reg_pair {
302 u32 lo, hi;
303 };
304
305 /*
306 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
307 */
308 struct dram_range {
309 struct reg_pair base;
310 struct reg_pair lim;
311 };
312
313 /* A DCT chip selects collection */
314 struct chip_select {
315 u32 csbases[NUM_CHIPSELECTS];
316 u8 b_cnt;
317
318 u32 csmasks[NUM_CHIPSELECTS];
319 u8 m_cnt;
320 };
321
322 struct amd64_umc {
323 u32 dimm_cfg; /* DIMM Configuration reg */
324 u32 umc_cfg; /* Configuration reg */
325 u32 sdp_ctrl; /* SDP Control reg */
326 u32 ecc_ctrl; /* DRAM ECC Control reg */
327 u32 umc_cap_hi; /* Capabilities High reg */
328 };
329
330 struct amd64_pvt {
331 struct low_ops *ops;
332
333 /* pci_device handles which we utilize */
334 struct pci_dev *F0, *F1, *F2, *F3, *F6;
335
336 u16 mc_node_id; /* MC index of this MC node */
337 u8 fam; /* CPU family */
338 u8 model; /* ... model */
339 u8 stepping; /* ... stepping */
340
341 int ext_model; /* extended model value of this node */
342 int channel_count;
343
344 /* Raw registers */
345 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
346 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
347 u32 dchr0; /* DRAM Configuration High DCT0 reg */
348 u32 dchr1; /* DRAM Configuration High DCT1 reg */
349 u32 nbcap; /* North Bridge Capabilities */
350 u32 nbcfg; /* F10 North Bridge Configuration */
351 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
352 u32 dhar; /* DRAM Hoist reg */
353 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
354 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
355
356 /* one for each DCT */
357 struct chip_select csels[2];
358
359 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
360 struct dram_range ranges[DRAM_RANGES];
361
362 u64 top_mem; /* top of memory below 4GB */
363 u64 top_mem2; /* top of memory above 4GB */
364
365 u32 dct_sel_lo; /* DRAM Controller Select Low */
366 u32 dct_sel_hi; /* DRAM Controller Select High */
367 u32 online_spare; /* On-Line spare Reg */
368
369 /* x4 or x8 syndromes in use */
370 u8 ecc_sym_sz;
371
372 /* place to store error injection parameters prior to issue */
373 struct error_injection injection;
374
375 /* cache the dram_type */
376 enum mem_type dram_type;
377
378 struct amd64_umc *umc; /* UMC registers */
379 };
380
381 enum err_codes {
382 DECODE_OK = 0,
383 ERR_NODE = -1,
384 ERR_CSROW = -2,
385 ERR_CHANNEL = -3,
386 ERR_SYND = -4,
387 ERR_NORM_ADDR = -5,
388 };
389
390 struct err_info {
391 int err_code;
392 struct mem_ctl_info *src_mci;
393 int csrow;
394 int channel;
395 u16 syndrome;
396 u32 page;
397 u32 offset;
398 };
399
get_umc_base(u8 channel)400 static inline u32 get_umc_base(u8 channel)
401 {
402 /* ch0: 0x50000, ch1: 0x150000 */
403 return 0x50000 + (!!channel << 20);
404 }
405
get_dram_base(struct amd64_pvt * pvt,u8 i)406 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
407 {
408 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
409
410 if (boot_cpu_data.x86 == 0xf)
411 return addr;
412
413 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
414 }
415
get_dram_limit(struct amd64_pvt * pvt,u8 i)416 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
417 {
418 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
419
420 if (boot_cpu_data.x86 == 0xf)
421 return lim;
422
423 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
424 }
425
extract_syndrome(u64 status)426 static inline u16 extract_syndrome(u64 status)
427 {
428 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
429 }
430
dct_sel_interleave_addr(struct amd64_pvt * pvt)431 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
432 {
433 if (pvt->fam == 0x15 && pvt->model >= 0x30)
434 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
435 ((pvt->dct_sel_lo >> 6) & 0x3);
436
437 return ((pvt)->dct_sel_lo >> 6) & 0x3;
438 }
439 /*
440 * per-node ECC settings descriptor
441 */
442 struct ecc_settings {
443 u32 old_nbctl;
444 bool nbctl_valid;
445
446 struct flags {
447 unsigned long nb_mce_enable:1;
448 unsigned long nb_ecc_prev:1;
449 } flags;
450 };
451
452 #ifdef CONFIG_EDAC_DEBUG
453 extern const struct attribute_group amd64_edac_dbg_group;
454 #endif
455
456 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
457 extern const struct attribute_group amd64_edac_inj_group;
458 #endif
459
460 /*
461 * Each of the PCI Device IDs types have their own set of hardware accessor
462 * functions and per device encoding/decoding logic.
463 */
464 struct low_ops {
465 int (*early_channel_count) (struct amd64_pvt *pvt);
466 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
467 struct err_info *);
468 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
469 unsigned cs_mode, int cs_mask_nr);
470 };
471
472 struct amd64_family_type {
473 const char *ctl_name;
474 u16 f0_id, f1_id, f2_id, f6_id;
475 struct low_ops ops;
476 };
477
478 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
479 u32 *val, const char *func);
480 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
481 u32 val, const char *func);
482
483 #define amd64_read_pci_cfg(pdev, offset, val) \
484 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
485
486 #define amd64_write_pci_cfg(pdev, offset, val) \
487 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
488
489 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
490 u64 *hole_offset, u64 *hole_size);
491
492 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
493
494 /* Injection helpers */
disable_caches(void * dummy)495 static inline void disable_caches(void *dummy)
496 {
497 write_cr0(read_cr0() | X86_CR0_CD);
498 wbinvd();
499 }
500
enable_caches(void * dummy)501 static inline void enable_caches(void *dummy)
502 {
503 write_cr0(read_cr0() & ~X86_CR0_CD);
504 }
505
dram_intlv_en(struct amd64_pvt * pvt,unsigned int i)506 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
507 {
508 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
509 u32 tmp;
510 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
511 return (u8) tmp & 0xF;
512 }
513 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
514 }
515
dhar_valid(struct amd64_pvt * pvt)516 static inline u8 dhar_valid(struct amd64_pvt *pvt)
517 {
518 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
519 u32 tmp;
520 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
521 return (tmp >> 1) & BIT(0);
522 }
523 return (pvt)->dhar & BIT(0);
524 }
525
dct_sel_baseaddr(struct amd64_pvt * pvt)526 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
527 {
528 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
529 u32 tmp;
530 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
531 return (tmp >> 11) & 0x1FFF;
532 }
533 return (pvt)->dct_sel_lo & 0xFFFFF800;
534 }
535