1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25
26 #include <linux/types.h>
27 #include <linux/i2c.h>
28 #include <linux/delay.h>
29
30 /*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
41 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
44
45 #define DP_AUX_MAX_PAYLOAD_BYTES 16
46
47 #define DP_AUX_I2C_WRITE 0x0
48 #define DP_AUX_I2C_READ 0x1
49 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
50 #define DP_AUX_I2C_MOT 0x4
51 #define DP_AUX_NATIVE_WRITE 0x8
52 #define DP_AUX_NATIVE_READ 0x9
53
54 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
58
59 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
63
64 /* AUX CH addresses */
65 /* DPCD */
66 #define DP_DPCD_REV 0x000
67 # define DP_DPCD_REV_10 0x10
68 # define DP_DPCD_REV_11 0x11
69 # define DP_DPCD_REV_12 0x12
70 # define DP_DPCD_REV_13 0x13
71 # define DP_DPCD_REV_14 0x14
72
73 #define DP_MAX_LINK_RATE 0x001
74
75 #define DP_MAX_LANE_COUNT 0x002
76 # define DP_MAX_LANE_COUNT_MASK 0x1f
77 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
78 # define DP_ENHANCED_FRAME_CAP (1 << 7)
79
80 #define DP_MAX_DOWNSPREAD 0x003
81 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
82 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
83 # define DP_TPS4_SUPPORTED (1 << 7)
84
85 #define DP_NORP 0x004
86
87 #define DP_DOWNSTREAMPORT_PRESENT 0x005
88 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
89 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
90 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
91 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
92 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
93 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
94 # define DP_FORMAT_CONVERSION (1 << 3)
95 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
96
97 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
98
99 #define DP_DOWN_STREAM_PORT_COUNT 0x007
100 # define DP_PORT_COUNT_MASK 0x0f
101 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
102 # define DP_OUI_SUPPORT (1 << 7)
103
104 #define DP_RECEIVE_PORT_0_CAP_0 0x008
105 # define DP_LOCAL_EDID_PRESENT (1 << 1)
106 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
107
108 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
109
110 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
111 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
112
113 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
114 # define DP_I2C_SPEED_1K 0x01
115 # define DP_I2C_SPEED_5K 0x02
116 # define DP_I2C_SPEED_10K 0x04
117 # define DP_I2C_SPEED_100K 0x08
118 # define DP_I2C_SPEED_400K 0x10
119 # define DP_I2C_SPEED_1M 0x20
120
121 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
122 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
123 # define DP_FRAMING_CHANGE_CAP (1 << 1)
124 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
125
126 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
127 # define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
128
129 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
130 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
131 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
132
133 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
134 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
135
136 /* Multiple stream transport */
137 #define DP_FAUX_CAP 0x020 /* 1.2 */
138 # define DP_FAUX_CAP_1 (1 << 0)
139
140 #define DP_MSTM_CAP 0x021 /* 1.2 */
141 # define DP_MST_CAP (1 << 0)
142
143 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
144
145 /* AV_SYNC_DATA_BLOCK 1.2 */
146 #define DP_AV_GRANULARITY 0x023
147 # define DP_AG_FACTOR_MASK (0xf << 0)
148 # define DP_AG_FACTOR_3MS (0 << 0)
149 # define DP_AG_FACTOR_2MS (1 << 0)
150 # define DP_AG_FACTOR_1MS (2 << 0)
151 # define DP_AG_FACTOR_500US (3 << 0)
152 # define DP_AG_FACTOR_200US (4 << 0)
153 # define DP_AG_FACTOR_100US (5 << 0)
154 # define DP_AG_FACTOR_10US (6 << 0)
155 # define DP_AG_FACTOR_1US (7 << 0)
156 # define DP_VG_FACTOR_MASK (0xf << 4)
157 # define DP_VG_FACTOR_3MS (0 << 4)
158 # define DP_VG_FACTOR_2MS (1 << 4)
159 # define DP_VG_FACTOR_1MS (2 << 4)
160 # define DP_VG_FACTOR_500US (3 << 4)
161 # define DP_VG_FACTOR_200US (4 << 4)
162 # define DP_VG_FACTOR_100US (5 << 4)
163
164 #define DP_AUD_DEC_LAT0 0x024
165 #define DP_AUD_DEC_LAT1 0x025
166
167 #define DP_AUD_PP_LAT0 0x026
168 #define DP_AUD_PP_LAT1 0x027
169
170 #define DP_VID_INTER_LAT 0x028
171
172 #define DP_VID_PROG_LAT 0x029
173
174 #define DP_REP_LAT 0x02a
175
176 #define DP_AUD_DEL_INS0 0x02b
177 #define DP_AUD_DEL_INS1 0x02c
178 #define DP_AUD_DEL_INS2 0x02d
179 /* End of AV_SYNC_DATA_BLOCK */
180
181 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
182 # define DP_ALPM_CAP (1 << 0)
183
184 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
185 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
186
187 #define DP_GUID 0x030 /* 1.2 */
188
189 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
190 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
191
192 #define DP_DSC_REV 0x061
193 # define DP_DSC_MAJOR_MASK (0xf << 0)
194 # define DP_DSC_MINOR_MASK (0xf << 4)
195 # define DP_DSC_MAJOR_SHIFT 0
196 # define DP_DSC_MINOR_SHIFT 4
197
198 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
199 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
200 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
201 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
202 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
203
204 #define DP_DSC_RC_BUF_SIZE 0x063
205
206 #define DP_DSC_SLICE_CAP_1 0x064
207 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
208 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
209 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
210 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
211 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
212 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
213 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
214
215 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
216 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
217 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
218 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
219 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
220 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
221 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
222 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
223 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
224 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
225 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
226
227 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
228 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
229
230 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
231
232 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
233
234 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
235 # define DP_DSC_RGB (1 << 0)
236 # define DP_DSC_YCbCr444 (1 << 1)
237 # define DP_DSC_YCbCr422_Simple (1 << 2)
238 # define DP_DSC_YCbCr422_Native (1 << 3)
239 # define DP_DSC_YCbCr420_Native (1 << 4)
240
241 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
242 # define DP_DSC_8_BPC (1 << 1)
243 # define DP_DSC_10_BPC (1 << 2)
244 # define DP_DSC_12_BPC (1 << 3)
245
246 #define DP_DSC_PEAK_THROUGHPUT 0x06B
247 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
248 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
249 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
250 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
251 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
252 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
253 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
254 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
255 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
256 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
257 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
258 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
259 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
260 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
261 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
262 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
263 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
264 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
265 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
266 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
267 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
268 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
269 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
270 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
271 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
272 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
273 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
274 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
275 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
276 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
277 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
278 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
279
280 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
281
282 #define DP_DSC_SLICE_CAP_2 0x06D
283 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
284 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
285 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
286
287 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
288 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
289 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
290 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
291 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
292 # define DP_DSC_BITS_PER_PIXEL_1 0x4
293
294 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
295 # define DP_PSR_IS_SUPPORTED 1
296 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
297 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
298
299 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
300 # define DP_PSR_NO_TRAIN_ON_EXIT 1
301 # define DP_PSR_SETUP_TIME_330 (0 << 1)
302 # define DP_PSR_SETUP_TIME_275 (1 << 1)
303 # define DP_PSR_SETUP_TIME_220 (2 << 1)
304 # define DP_PSR_SETUP_TIME_165 (3 << 1)
305 # define DP_PSR_SETUP_TIME_110 (4 << 1)
306 # define DP_PSR_SETUP_TIME_55 (5 << 1)
307 # define DP_PSR_SETUP_TIME_0 (6 << 1)
308 # define DP_PSR_SETUP_TIME_MASK (7 << 1)
309 # define DP_PSR_SETUP_TIME_SHIFT 1
310 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
311 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
312 /*
313 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
314 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
315 * each port's descriptor is one byte wide. If it was set, each port's is
316 * four bytes wide, starting with the one byte from the base info. As of
317 * DP interop v1.1a only VGA defines additional detail.
318 */
319
320 /* offset 0 */
321 #define DP_DOWNSTREAM_PORT_0 0x80
322 # define DP_DS_PORT_TYPE_MASK (7 << 0)
323 # define DP_DS_PORT_TYPE_DP 0
324 # define DP_DS_PORT_TYPE_VGA 1
325 # define DP_DS_PORT_TYPE_DVI 2
326 # define DP_DS_PORT_TYPE_HDMI 3
327 # define DP_DS_PORT_TYPE_NON_EDID 4
328 # define DP_DS_PORT_TYPE_DP_DUALMODE 5
329 # define DP_DS_PORT_TYPE_WIRELESS 6
330 # define DP_DS_PORT_HPD (1 << 3)
331 /* offset 1 for VGA is maximum megapixels per second / 8 */
332 /* offset 2 */
333 # define DP_DS_MAX_BPC_MASK (3 << 0)
334 # define DP_DS_8BPC 0
335 # define DP_DS_10BPC 1
336 # define DP_DS_12BPC 2
337 # define DP_DS_16BPC 3
338
339 /* DP Forward error Correction Registers */
340 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
341 # define DP_FEC_CAPABLE (1 << 0)
342 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
343 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
344 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
345
346 /* link configuration */
347 #define DP_LINK_BW_SET 0x100
348 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
349 # define DP_LINK_BW_1_62 0x06
350 # define DP_LINK_BW_2_7 0x0a
351 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
352 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
353
354 #define DP_LANE_COUNT_SET 0x101
355 # define DP_LANE_COUNT_MASK 0x0f
356 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
357
358 #define DP_TRAINING_PATTERN_SET 0x102
359 # define DP_TRAINING_PATTERN_DISABLE 0
360 # define DP_TRAINING_PATTERN_1 1
361 # define DP_TRAINING_PATTERN_2 2
362 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
363 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
364 # define DP_TRAINING_PATTERN_MASK 0x3
365 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
366
367 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
368 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
369 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
370 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
371 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
372 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
373
374 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
375 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
376
377 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
378 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
379 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
380 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
381
382 #define DP_TRAINING_LANE0_SET 0x103
383 #define DP_TRAINING_LANE1_SET 0x104
384 #define DP_TRAINING_LANE2_SET 0x105
385 #define DP_TRAINING_LANE3_SET 0x106
386
387 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
388 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
389 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
390 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
391 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
392 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
393 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
394
395 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
396 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
397 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
398 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
399 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
400
401 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
402 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
403
404 #define DP_DOWNSPREAD_CTRL 0x107
405 # define DP_SPREAD_AMP_0_5 (1 << 4)
406 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
407
408 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
409 # define DP_SET_ANSI_8B10B (1 << 0)
410
411 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
412 /* bitmask as for DP_I2C_SPEED_CAP */
413
414 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
415 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
416 # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
417 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
418
419 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
420 #define DP_LINK_QUAL_LANE1_SET 0x10c
421 #define DP_LINK_QUAL_LANE2_SET 0x10d
422 #define DP_LINK_QUAL_LANE3_SET 0x10e
423 # define DP_LINK_QUAL_PATTERN_DISABLE 0
424 # define DP_LINK_QUAL_PATTERN_D10_2 1
425 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
426 # define DP_LINK_QUAL_PATTERN_PRBS7 3
427 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
428 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
429 # define DP_LINK_QUAL_PATTERN_MASK 7
430
431 #define DP_TRAINING_LANE0_1_SET2 0x10f
432 #define DP_TRAINING_LANE2_3_SET2 0x110
433 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
434 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
435 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
436 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
437
438 #define DP_MSTM_CTRL 0x111 /* 1.2 */
439 # define DP_MST_EN (1 << 0)
440 # define DP_UP_REQ_EN (1 << 1)
441 # define DP_UPSTREAM_IS_SRC (1 << 2)
442
443 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
444 #define DP_AUDIO_DELAY1 0x113
445 #define DP_AUDIO_DELAY2 0x114
446
447 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
448 # define DP_LINK_RATE_SET_SHIFT 0
449 # define DP_LINK_RATE_SET_MASK (7 << 0)
450
451 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
452 # define DP_ALPM_ENABLE (1 << 0)
453 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
454
455 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
456 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
457 # define DP_IRQ_HPD_ENABLE (1 << 1)
458
459 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
460 # define DP_PWR_NOT_NEEDED (1 << 0)
461
462 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
463 # define DP_FEC_READY (1 << 0)
464 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
465 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
466 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
467 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
468 # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
469 # define DP_FEC_LANE_SELECT_MASK (3 << 4)
470 # define DP_FEC_LANE_0_SELECT (0 << 4)
471 # define DP_FEC_LANE_1_SELECT (1 << 4)
472 # define DP_FEC_LANE_2_SELECT (2 << 4)
473 # define DP_FEC_LANE_3_SELECT (3 << 4)
474
475 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
476 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
477
478 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
479
480 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
481 # define DP_PSR_ENABLE (1 << 0)
482 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
483 # define DP_PSR_CRC_VERIFICATION (1 << 2)
484 # define DP_PSR_FRAME_CAPTURE (1 << 3)
485 # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
486 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
487 # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
488
489 #define DP_ADAPTER_CTRL 0x1a0
490 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
491
492 #define DP_BRANCH_DEVICE_CTRL 0x1a1
493 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
494
495 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
496 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
497 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
498
499 #define DP_SINK_COUNT 0x200
500 /* prior to 1.2 bit 7 was reserved mbz */
501 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
502 # define DP_SINK_CP_READY (1 << 6)
503
504 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
505 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
506 # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
507 # define DP_CP_IRQ (1 << 2)
508 # define DP_MCCS_IRQ (1 << 3)
509 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
510 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
511 # define DP_SINK_SPECIFIC_IRQ (1 << 6)
512
513 #define DP_LANE0_1_STATUS 0x202
514 #define DP_LANE2_3_STATUS 0x203
515 # define DP_LANE_CR_DONE (1 << 0)
516 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
517 # define DP_LANE_SYMBOL_LOCKED (1 << 2)
518
519 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
520 DP_LANE_CHANNEL_EQ_DONE | \
521 DP_LANE_SYMBOL_LOCKED)
522
523 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
524
525 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
526 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
527 #define DP_LINK_STATUS_UPDATED (1 << 7)
528
529 #define DP_SINK_STATUS 0x205
530
531 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
532 #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
533
534 #define DP_ADJUST_REQUEST_LANE0_1 0x206
535 #define DP_ADJUST_REQUEST_LANE2_3 0x207
536 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
537 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
538 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
539 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
540 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
541 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
542 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
543 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
544
545 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
546
547 #define DP_TEST_REQUEST 0x218
548 # define DP_TEST_LINK_TRAINING (1 << 0)
549 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
550 # define DP_TEST_LINK_EDID_READ (1 << 2)
551 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
552 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
553
554 #define DP_TEST_LINK_RATE 0x219
555 # define DP_LINK_RATE_162 (0x6)
556 # define DP_LINK_RATE_27 (0xa)
557
558 #define DP_TEST_LANE_COUNT 0x220
559
560 #define DP_TEST_PATTERN 0x221
561 # define DP_NO_TEST_PATTERN 0x0
562 # define DP_COLOR_RAMP 0x1
563 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
564 # define DP_COLOR_SQUARE 0x3
565
566 #define DP_TEST_H_TOTAL_HI 0x222
567 #define DP_TEST_H_TOTAL_LO 0x223
568
569 #define DP_TEST_V_TOTAL_HI 0x224
570 #define DP_TEST_V_TOTAL_LO 0x225
571
572 #define DP_TEST_H_START_HI 0x226
573 #define DP_TEST_H_START_LO 0x227
574
575 #define DP_TEST_V_START_HI 0x228
576 #define DP_TEST_V_START_LO 0x229
577
578 #define DP_TEST_HSYNC_HI 0x22A
579 # define DP_TEST_HSYNC_POLARITY (1 << 7)
580 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
581 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
582
583 #define DP_TEST_VSYNC_HI 0x22C
584 # define DP_TEST_VSYNC_POLARITY (1 << 7)
585 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
586 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
587
588 #define DP_TEST_H_WIDTH_HI 0x22E
589 #define DP_TEST_H_WIDTH_LO 0x22F
590
591 #define DP_TEST_V_HEIGHT_HI 0x230
592 #define DP_TEST_V_HEIGHT_LO 0x231
593
594 #define DP_TEST_MISC0 0x232
595 # define DP_TEST_SYNC_CLOCK (1 << 0)
596 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
597 # define DP_TEST_COLOR_FORMAT_SHIFT 1
598 # define DP_COLOR_FORMAT_RGB (0 << 1)
599 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
600 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
601 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
602 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
603 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
604 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
605 # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
606 # define DP_TEST_BIT_DEPTH_SHIFT 5
607 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
608 # define DP_TEST_BIT_DEPTH_8 (1 << 5)
609 # define DP_TEST_BIT_DEPTH_10 (2 << 5)
610 # define DP_TEST_BIT_DEPTH_12 (3 << 5)
611 # define DP_TEST_BIT_DEPTH_16 (4 << 5)
612
613 #define DP_TEST_MISC1 0x233
614 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
615 # define DP_TEST_INTERLACED (1 << 1)
616
617 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
618
619 #define DP_TEST_MISC0 0x232
620
621 #define DP_TEST_CRC_R_CR 0x240
622 #define DP_TEST_CRC_G_Y 0x242
623 #define DP_TEST_CRC_B_CB 0x244
624
625 #define DP_TEST_SINK_MISC 0x246
626 # define DP_TEST_CRC_SUPPORTED (1 << 5)
627 # define DP_TEST_COUNT_MASK 0xf
628
629 #define DP_TEST_PHY_PATTERN 0x248
630 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
631 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
632 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
633 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
634 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
635 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
636 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
637 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
638 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
639 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
640
641 #define DP_TEST_RESPONSE 0x260
642 # define DP_TEST_ACK (1 << 0)
643 # define DP_TEST_NAK (1 << 1)
644 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
645
646 #define DP_TEST_EDID_CHECKSUM 0x261
647
648 #define DP_TEST_SINK 0x270
649 # define DP_TEST_SINK_START (1 << 0)
650
651 #define DP_FEC_STATUS 0x280 /* 1.4 */
652 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
653 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
654
655 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
656
657 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
658 # define DP_FEC_ERROR_COUNT_MASK 0x7F
659 # define DP_FEC_ERR_COUNT_VALID (1 << 7)
660
661 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
662 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
663 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
664
665 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
666 /* up to ID_SLOT_63 at 0x2ff */
667
668 #define DP_SOURCE_OUI 0x300
669 #define DP_SINK_OUI 0x400
670 #define DP_BRANCH_OUI 0x500
671 #define DP_BRANCH_ID 0x503
672 #define DP_BRANCH_REVISION_START 0x509
673 #define DP_BRANCH_HW_REV 0x509
674 #define DP_BRANCH_SW_REV 0x50A
675
676 #define DP_SET_POWER 0x600
677 # define DP_SET_POWER_D0 0x1
678 # define DP_SET_POWER_D3 0x2
679 # define DP_SET_POWER_MASK 0x3
680 # define DP_SET_POWER_D3_AUX_ON 0x5
681
682 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
683 # define DP_EDP_11 0x00
684 # define DP_EDP_12 0x01
685 # define DP_EDP_13 0x02
686 # define DP_EDP_14 0x03
687
688 #define DP_EDP_GENERAL_CAP_1 0x701
689 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
690 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
691 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
692 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
693 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
694 # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
695 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
696 # define DP_EDP_SET_POWER_CAP (1 << 7)
697
698 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
699 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
700 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
701 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
702 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
703 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
704 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
705 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
706 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
707
708 #define DP_EDP_GENERAL_CAP_2 0x703
709 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
710
711 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
712 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
713 # define DP_EDP_X_REGION_CAP_SHIFT 0
714 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
715 # define DP_EDP_Y_REGION_CAP_SHIFT 4
716
717 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
718 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
719 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
720 # define DP_EDP_FRC_ENABLE (1 << 2)
721 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
722 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
723
724 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
725 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
726 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
727 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
728 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
729 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
730 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
731 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
732 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
733 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
734 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
735
736 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
737 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
738
739 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
740 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
741 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
742 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
743
744 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
745
746 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
747 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
748
749 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
750 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
751 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
752
753 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
754 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
755 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
756
757 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
758 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
759
760 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
761 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
762
763 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
764 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
765 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
766 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
767
768 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
769 /* 0-5 sink count */
770 # define DP_SINK_COUNT_CP_READY (1 << 6)
771
772 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
773
774 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
775 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
776 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
777 # define DP_CEC_IRQ (1 << 2)
778
779 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
780
781 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
782 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
783 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
784 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
785
786 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
787 # define DP_PSR_CAPS_CHANGE (1 << 0)
788
789 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
790 # define DP_PSR_SINK_INACTIVE 0
791 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
792 # define DP_PSR_SINK_ACTIVE_RFB 2
793 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
794 # define DP_PSR_SINK_ACTIVE_RESYNC 4
795 # define DP_PSR_SINK_INTERNAL_ERROR 7
796 # define DP_PSR_SINK_STATE_MASK 0x07
797
798 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
799 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
800 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
801 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
802 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
803
804 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
805 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
806 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
807 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
808 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
809 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
810 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
811 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
812
813 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
814 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
815
816 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
817 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
818 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
819 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
820
821 #define DP_DP13_DPCD_REV 0x2200
822 #define DP_DP13_MAX_LINK_RATE 0x2201
823
824 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
825 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
826 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
827 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
828 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
829 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
830 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
831 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
832 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
833
834 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
835 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
836 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
837 # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
838 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
839
840 #define DP_CEC_TUNNELING_CONTROL 0x3001
841 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
842 # define DP_CEC_SNOOPING_ENABLE (1 << 1)
843
844 #define DP_CEC_RX_MESSAGE_INFO 0x3002
845 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
846 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
847 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
848 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
849 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
850 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
851
852 #define DP_CEC_TX_MESSAGE_INFO 0x3003
853 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
854 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
855 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
856 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
857 # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
858
859 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
860 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
861 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
862 # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
863 # define DP_CEC_TX_LINE_ERROR (1 << 5)
864 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
865 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
866
867 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
868 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
869 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
870 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
871 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
872 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
873 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
874 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
875 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
876 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
877 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
878 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
879 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
880 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
881 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
882 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
883 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
884 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
885
886 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
887 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
888 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
889
890 #define DP_AUX_HDCP_BKSV 0x68000
891 #define DP_AUX_HDCP_RI_PRIME 0x68005
892 #define DP_AUX_HDCP_AKSV 0x68007
893 #define DP_AUX_HDCP_AN 0x6800C
894 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
895 #define DP_AUX_HDCP_BCAPS 0x68028
896 # define DP_BCAPS_REPEATER_PRESENT BIT(1)
897 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
898 #define DP_AUX_HDCP_BSTATUS 0x68029
899 # define DP_BSTATUS_REAUTH_REQ BIT(3)
900 # define DP_BSTATUS_LINK_FAILURE BIT(2)
901 # define DP_BSTATUS_R0_PRIME_READY BIT(1)
902 # define DP_BSTATUS_READY BIT(0)
903 #define DP_AUX_HDCP_BINFO 0x6802A
904 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
905 #define DP_AUX_HDCP_AINFO 0x6803B
906
907 /* DP 1.2 Sideband message defines */
908 /* peer device type - DP 1.2a Table 2-92 */
909 #define DP_PEER_DEVICE_NONE 0x0
910 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
911 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
912 #define DP_PEER_DEVICE_SST_SINK 0x3
913 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
914
915 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
916 #define DP_LINK_ADDRESS 0x01
917 #define DP_CONNECTION_STATUS_NOTIFY 0x02
918 #define DP_ENUM_PATH_RESOURCES 0x10
919 #define DP_ALLOCATE_PAYLOAD 0x11
920 #define DP_QUERY_PAYLOAD 0x12
921 #define DP_RESOURCE_STATUS_NOTIFY 0x13
922 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
923 #define DP_REMOTE_DPCD_READ 0x20
924 #define DP_REMOTE_DPCD_WRITE 0x21
925 #define DP_REMOTE_I2C_READ 0x22
926 #define DP_REMOTE_I2C_WRITE 0x23
927 #define DP_POWER_UP_PHY 0x24
928 #define DP_POWER_DOWN_PHY 0x25
929 #define DP_SINK_EVENT_NOTIFY 0x30
930 #define DP_QUERY_STREAM_ENC_STATUS 0x38
931
932 /* DP 1.2 MST sideband nak reasons - table 2.84 */
933 #define DP_NAK_WRITE_FAILURE 0x01
934 #define DP_NAK_INVALID_READ 0x02
935 #define DP_NAK_CRC_FAILURE 0x03
936 #define DP_NAK_BAD_PARAM 0x04
937 #define DP_NAK_DEFER 0x05
938 #define DP_NAK_LINK_FAILURE 0x06
939 #define DP_NAK_NO_RESOURCES 0x07
940 #define DP_NAK_DPCD_FAIL 0x08
941 #define DP_NAK_I2C_NAK 0x09
942 #define DP_NAK_ALLOCATE_FAIL 0x0a
943
944 #define MODE_I2C_START 1
945 #define MODE_I2C_WRITE 2
946 #define MODE_I2C_READ 4
947 #define MODE_I2C_STOP 8
948
949 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
950 #define DP_MST_PHYSICAL_PORT_0 0
951 #define DP_MST_LOGICAL_PORT_0 8
952
953 #define DP_LINK_STATUS_SIZE 6
954 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
955 int lane_count);
956 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
957 int lane_count);
958 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
959 int lane);
960 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
961 int lane);
962
963 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
964 #define DP_RECEIVER_CAP_SIZE 0xf
965 #define EDP_PSR_RECEIVER_CAP_SIZE 2
966 #define EDP_DISPLAY_CTL_CAP_SIZE 3
967
968 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
969 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
970
971 u8 drm_dp_link_rate_to_bw_code(int link_rate);
972 int drm_dp_bw_code_to_link_rate(u8 link_bw);
973
974 #define DP_SDP_AUDIO_TIMESTAMP 0x01
975 #define DP_SDP_AUDIO_STREAM 0x02
976 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
977 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
978 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
979 #define DP_SDP_VSC 0x07 /* DP 1.2 */
980 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
981 #define DP_SDP_PPS 0x10 /* DP 1.4 */
982 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
983 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
984 /* 0x80+ CEA-861 infoframe types */
985
986 struct dp_sdp_header {
987 u8 HB0; /* Secondary Data Packet ID */
988 u8 HB1; /* Secondary Data Packet Type */
989 u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */
990 u8 HB3; /* Secondary Data packet Specific header, Byte 1 */
991 } __packed;
992
993 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
994 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
995
996 struct edp_vsc_psr {
997 struct dp_sdp_header sdp_header;
998 u8 DB0; /* Stereo Interface */
999 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
1000 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
1001 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
1002 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
1003 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
1004 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
1005 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
1006 u8 DB8_31[24]; /* Reserved */
1007 } __packed;
1008
1009 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1010 #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1011 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1012
1013 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1014
1015 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1016 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1017 {
1018 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1019 }
1020
1021 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1022 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1023 {
1024 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1025 }
1026
1027 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1028 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1029 {
1030 return dpcd[DP_DPCD_REV] >= 0x11 &&
1031 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1032 }
1033
1034 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1035 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1036 {
1037 return dpcd[DP_DPCD_REV] >= 0x12 &&
1038 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1039 }
1040
1041 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1042 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1043 {
1044 return dpcd[DP_DPCD_REV] >= 0x14 &&
1045 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1046 }
1047
1048 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1049 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1050 {
1051 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1052 DP_TRAINING_PATTERN_MASK;
1053 }
1054
1055 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1056 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1057 {
1058 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1059 }
1060
1061 /*
1062 * DisplayPort AUX channel
1063 */
1064
1065 /**
1066 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1067 * @address: address of the (first) register to access
1068 * @request: contains the type of transaction (see DP_AUX_* macros)
1069 * @reply: upon completion, contains the reply type of the transaction
1070 * @buffer: pointer to a transmission or reception buffer
1071 * @size: size of @buffer
1072 */
1073 struct drm_dp_aux_msg {
1074 unsigned int address;
1075 u8 request;
1076 u8 reply;
1077 void *buffer;
1078 size_t size;
1079 };
1080
1081 struct cec_adapter;
1082 struct edid;
1083
1084 /**
1085 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1086 * @lock: mutex protecting this struct
1087 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1088 * @name: name of the CEC adapter
1089 * @parent: parent device of the CEC adapter
1090 * @unregister_work: unregister the CEC adapter
1091 */
1092 struct drm_dp_aux_cec {
1093 struct mutex lock;
1094 struct cec_adapter *adap;
1095 const char *name;
1096 struct device *parent;
1097 struct delayed_work unregister_work;
1098 };
1099
1100 /**
1101 * struct drm_dp_aux - DisplayPort AUX channel
1102 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1103 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1104 * @dev: pointer to struct device that is the parent for this AUX channel
1105 * @crtc: backpointer to the crtc that is currently using this AUX channel
1106 * @hw_mutex: internal mutex used for locking transfers
1107 * @crc_work: worker that captures CRCs for each frame
1108 * @crc_count: counter of captured frame CRCs
1109 * @transfer: transfers a message representing a single AUX transaction
1110 *
1111 * The .dev field should be set to a pointer to the device that implements
1112 * the AUX channel.
1113 *
1114 * The .name field may be used to specify the name of the I2C adapter. If set to
1115 * NULL, dev_name() of .dev will be used.
1116 *
1117 * Drivers provide a hardware-specific implementation of how transactions
1118 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1119 * structure describing the transaction is passed into this function. Upon
1120 * success, the implementation should return the number of payload bytes
1121 * that were transferred, or a negative error-code on failure. Helpers
1122 * propagate errors from the .transfer() function, with the exception of
1123 * the -EBUSY error, which causes a transaction to be retried. On a short,
1124 * helpers will return -EPROTO to make it simpler to check for failure.
1125 *
1126 * An AUX channel can also be used to transport I2C messages to a sink. A
1127 * typical application of that is to access an EDID that's present in the
1128 * sink device. The .transfer() function can also be used to execute such
1129 * transactions. The drm_dp_aux_register() function registers an I2C
1130 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1131 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1132 * The I2C adapter uses long transfers by default; if a partial response is
1133 * received, the adapter will drop down to the size given by the partial
1134 * response for this transaction only.
1135 *
1136 * Note that the aux helper code assumes that the .transfer() function
1137 * only modifies the reply field of the drm_dp_aux_msg structure. The
1138 * retry logic and i2c helpers assume this is the case.
1139 */
1140 struct drm_dp_aux {
1141 const char *name;
1142 struct i2c_adapter ddc;
1143 struct device *dev;
1144 struct drm_crtc *crtc;
1145 struct mutex hw_mutex;
1146 struct work_struct crc_work;
1147 u8 crc_count;
1148 ssize_t (*transfer)(struct drm_dp_aux *aux,
1149 struct drm_dp_aux_msg *msg);
1150 /**
1151 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1152 */
1153 unsigned i2c_nack_count;
1154 /**
1155 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1156 */
1157 unsigned i2c_defer_count;
1158 /**
1159 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1160 */
1161 struct drm_dp_aux_cec cec;
1162 };
1163
1164 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1165 void *buffer, size_t size);
1166 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1167 void *buffer, size_t size);
1168
1169 /**
1170 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1171 * @aux: DisplayPort AUX channel
1172 * @offset: address of the register to read
1173 * @valuep: location where the value of the register will be stored
1174 *
1175 * Returns the number of bytes transferred (1) on success, or a negative
1176 * error code on failure.
1177 */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)1178 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1179 unsigned int offset, u8 *valuep)
1180 {
1181 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1182 }
1183
1184 /**
1185 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1186 * @aux: DisplayPort AUX channel
1187 * @offset: address of the register to write
1188 * @value: value to write to the register
1189 *
1190 * Returns the number of bytes transferred (1) on success, or a negative
1191 * error code on failure.
1192 */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)1193 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1194 unsigned int offset, u8 value)
1195 {
1196 return drm_dp_dpcd_write(aux, offset, &value, 1);
1197 }
1198
1199 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1200 u8 status[DP_LINK_STATUS_SIZE]);
1201
1202 /*
1203 * DisplayPort link
1204 */
1205 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1206
1207 struct drm_dp_link {
1208 unsigned char revision;
1209 unsigned int rate;
1210 unsigned int num_lanes;
1211 unsigned long capabilities;
1212 };
1213
1214 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1215 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1216 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1217 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1218 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1219 const u8 port_cap[4]);
1220 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1221 const u8 port_cap[4]);
1222 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1223 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1224 const u8 port_cap[4], struct drm_dp_aux *aux);
1225
1226 void drm_dp_aux_init(struct drm_dp_aux *aux);
1227 int drm_dp_aux_register(struct drm_dp_aux *aux);
1228 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1229
1230 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1231 int drm_dp_stop_crc(struct drm_dp_aux *aux);
1232
1233 struct drm_dp_dpcd_ident {
1234 u8 oui[3];
1235 u8 device_id[6];
1236 u8 hw_rev;
1237 u8 sw_major_rev;
1238 u8 sw_minor_rev;
1239 } __packed;
1240
1241 /**
1242 * struct drm_dp_desc - DP branch/sink device descriptor
1243 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1244 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1245 */
1246 struct drm_dp_desc {
1247 struct drm_dp_dpcd_ident ident;
1248 u32 quirks;
1249 };
1250
1251 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1252 bool is_branch);
1253
1254 /**
1255 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1256 *
1257 * Display Port sink and branch devices in the wild have a variety of bugs, try
1258 * to collect them here. The quirks are shared, but it's up to the drivers to
1259 * implement workarounds for them.
1260 */
1261 enum drm_dp_quirk {
1262 /**
1263 * @DP_DPCD_QUIRK_LIMITED_M_N:
1264 *
1265 * The device requires main link attributes Mvid and Nvid to be limited
1266 * to 16 bits.
1267 */
1268 DP_DPCD_QUIRK_LIMITED_M_N,
1269 };
1270
1271 /**
1272 * drm_dp_has_quirk() - does the DP device have a specific quirk
1273 * @desc: Device decriptor filled by drm_dp_read_desc()
1274 * @quirk: Quirk to query for
1275 *
1276 * Return true if DP device identified by @desc has @quirk.
1277 */
1278 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)1279 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1280 {
1281 return desc->quirks & BIT(quirk);
1282 }
1283
1284 #ifdef CONFIG_DRM_DP_CEC
1285 void drm_dp_cec_irq(struct drm_dp_aux *aux);
1286 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name,
1287 struct device *parent);
1288 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1289 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1290 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1291 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)1292 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1293 {
1294 }
1295
drm_dp_cec_register_connector(struct drm_dp_aux * aux,const char * name,struct device * parent)1296 static inline void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1297 const char *name,
1298 struct device *parent)
1299 {
1300 }
1301
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)1302 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1303 {
1304 }
1305
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)1306 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1307 const struct edid *edid)
1308 {
1309 }
1310
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)1311 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1312 {
1313 }
1314
1315 #endif
1316
1317 #endif /* _DRM_DP_HELPER_H_ */
1318