1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 #include "drm.h"
28 
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32 
33 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
34 				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
35 
36 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
37 
38 /* color index */
39 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
40 
41 /* 8 bpp Red */
42 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
43 
44 /* 16 bpp Red */
45 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
46 
47 /* 16 bpp RG */
48 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
49 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
50 
51 /* 32 bpp RG */
52 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
53 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
54 
55 /* 8 bpp RGB */
56 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
57 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
58 
59 /* 16 bpp RGB */
60 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
61 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
62 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
63 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
64 
65 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
66 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
67 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
68 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
69 
70 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
71 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
72 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
73 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
74 
75 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
76 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
77 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
78 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
79 
80 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
81 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
82 
83 /* 24 bpp RGB */
84 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
85 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
86 
87 /* 32 bpp RGB */
88 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
89 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
90 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
91 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
92 
93 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
94 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
95 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
96 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
97 
98 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
99 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
100 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
101 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
102 
103 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
104 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
105 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
106 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
107 
108 /* packed YCbCr */
109 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
110 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
111 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
112 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
113 
114 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
115 
116 /*
117  * 2 plane RGB + A
118  * index 0 = RGB plane, same format as the corresponding non _A8 format has
119  * index 1 = A plane, [7:0] A
120  */
121 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
122 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
123 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
124 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
125 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
126 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
127 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
128 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
129 
130 /*
131  * 2 plane YCbCr
132  * index 0 = Y plane, [7:0] Y
133  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
134  * or
135  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
136  */
137 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
138 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
139 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
140 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
141 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
142 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
143 
144 /*
145  * 3 plane YCbCr
146  * index 0: Y plane, [7:0] Y
147  * index 1: Cb plane, [7:0] Cb
148  * index 2: Cr plane, [7:0] Cr
149  * or
150  * index 1: Cr plane, [7:0] Cr
151  * index 2: Cb plane, [7:0] Cb
152  */
153 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
154 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
155 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
156 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
157 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
158 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
159 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
160 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
161 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
162 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
163 
164 
165 /*
166  * Format Modifiers:
167  *
168  * Format modifiers describe, typically, a re-ordering or modification
169  * of the data in a plane of an FB.  This can be used to express tiled/
170  * swizzled formats, or compression, or a combination of the two.
171  *
172  * The upper 8 bits of the format modifier are a vendor-id as assigned
173  * below.  The lower 56 bits are assigned as vendor sees fit.
174  */
175 
176 /* Vendor Ids: */
177 #define DRM_FORMAT_MOD_NONE           0
178 #define DRM_FORMAT_MOD_VENDOR_NONE    0
179 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
180 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
181 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
182 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
183 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
184 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
185 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
186 #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
187 /* add more to the end as needed */
188 
189 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
190 
191 #define fourcc_mod_code(vendor, val) \
192 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
193 
194 /*
195  * Format Modifier tokens:
196  *
197  * When adding a new token please document the layout with a code comment,
198  * similar to the fourcc codes above. drm_fourcc.h is considered the
199  * authoritative source for all of these.
200  */
201 
202 /*
203  * Invalid Modifier
204  *
205  * This modifier can be used as a sentinel to terminate the format modifiers
206  * list, or to initialize a variable with an invalid modifier. It might also be
207  * used to report an error back to userspace for certain APIs.
208  */
209 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
210 
211 /*
212  * Linear Layout
213  *
214  * Just plain linear layout. Note that this is different from no specifying any
215  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
216  * which tells the driver to also take driver-internal information into account
217  * and so might actually result in a tiled framebuffer.
218  */
219 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
220 
221 /* Intel framebuffer modifiers */
222 
223 /*
224  * Intel X-tiling layout
225  *
226  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
227  * in row-major layout. Within the tile bytes are laid out row-major, with
228  * a platform-dependent stride. On top of that the memory can apply
229  * platform-depending swizzling of some higher address bits into bit6.
230  *
231  * This format is highly platforms specific and not useful for cross-driver
232  * sharing. It exists since on a given platform it does uniquely identify the
233  * layout in a simple way for i915-specific userspace.
234  */
235 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
236 
237 /*
238  * Intel Y-tiling layout
239  *
240  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
241  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
242  * chunks column-major, with a platform-dependent height. On top of that the
243  * memory can apply platform-depending swizzling of some higher address bits
244  * into bit6.
245  *
246  * This format is highly platforms specific and not useful for cross-driver
247  * sharing. It exists since on a given platform it does uniquely identify the
248  * layout in a simple way for i915-specific userspace.
249  */
250 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
251 
252 /*
253  * Intel Yf-tiling layout
254  *
255  * This is a tiled layout using 4Kb tiles in row-major layout.
256  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
257  * are arranged in four groups (two wide, two high) with column-major layout.
258  * Each group therefore consits out of four 256 byte units, which are also laid
259  * out as 2x2 column-major.
260  * 256 byte units are made out of four 64 byte blocks of pixels, producing
261  * either a square block or a 2:1 unit.
262  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
263  * in pixel depends on the pixel depth.
264  */
265 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
266 
267 /*
268  * Intel color control surface (CCS) for render compression
269  *
270  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
271  * The main surface will be plane index 0 and must be Y/Yf-tiled,
272  * the CCS will be plane index 1.
273  *
274  * Each CCS tile matches a 1024x512 pixel area of the main surface.
275  * To match certain aspects of the 3D hardware the CCS is
276  * considered to be made up of normal 128Bx32 Y tiles, Thus
277  * the CCS pitch must be specified in multiples of 128 bytes.
278  *
279  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
280  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
281  * But that fact is not relevant unless the memory is accessed
282  * directly.
283  */
284 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
285 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
286 
287 /*
288  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
289  *
290  * Macroblocks are laid in a Z-shape, and each pixel data is following the
291  * standard NV12 style.
292  * As for NV12, an image is the result of two frame buffers: one for Y,
293  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
294  * Alignment requirements are (for each buffer):
295  * - multiple of 128 pixels for the width
296  * - multiple of  32 pixels for the height
297  *
298  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
299  */
300 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
301 
302 /*
303  * Qualcomm Compressed Format
304  *
305  * Refers to a compressed variant of the base format that is compressed.
306  * Implementation may be platform and base-format specific.
307  *
308  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
309  * Pixel data pitch/stride is aligned with macrotile width.
310  * Pixel data height is aligned with macrotile height.
311  * Entire pixel data buffer is aligned with 4k(bytes).
312  */
313 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
314 
315 /* Vivante framebuffer modifiers */
316 
317 /*
318  * Vivante 4x4 tiling layout
319  *
320  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
321  * layout.
322  */
323 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
324 
325 /*
326  * Vivante 64x64 super-tiling layout
327  *
328  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
329  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
330  * major layout.
331  *
332  * For more information: see
333  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
334  */
335 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
336 
337 /*
338  * Vivante 4x4 tiling layout for dual-pipe
339  *
340  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
341  * different base address. Offsets from the base addresses are therefore halved
342  * compared to the non-split tiled layout.
343  */
344 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
345 
346 /*
347  * Vivante 64x64 super-tiling layout for dual-pipe
348  *
349  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
350  * starts at a different base address. Offsets from the base addresses are
351  * therefore halved compared to the non-split super-tiled layout.
352  */
353 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
354 
355 /* NVIDIA frame buffer modifiers */
356 
357 /*
358  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
359  *
360  * Pixels are arranged in simple tiles of 16 x 16 bytes.
361  */
362 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
363 
364 /*
365  * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
366  *
367  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
368  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
369  *
370  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
371  *
372  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
373  * Valid values are:
374  *
375  * 0 == ONE_GOB
376  * 1 == TWO_GOBS
377  * 2 == FOUR_GOBS
378  * 3 == EIGHT_GOBS
379  * 4 == SIXTEEN_GOBS
380  * 5 == THIRTYTWO_GOBS
381  *
382  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
383  * in full detail.
384  */
385 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
386 	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
387 
388 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
389 	fourcc_mod_code(NVIDIA, 0x10)
390 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
391 	fourcc_mod_code(NVIDIA, 0x11)
392 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
393 	fourcc_mod_code(NVIDIA, 0x12)
394 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
395 	fourcc_mod_code(NVIDIA, 0x13)
396 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
397 	fourcc_mod_code(NVIDIA, 0x14)
398 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
399 	fourcc_mod_code(NVIDIA, 0x15)
400 
401 /*
402  * Some Broadcom modifiers take parameters, for example the number of
403  * vertical lines in the image. Reserve the lower 32 bits for modifier
404  * type, and the next 24 bits for parameters. Top 8 bits are the
405  * vendor code.
406  */
407 #define __fourcc_mod_broadcom_param_shift 8
408 #define __fourcc_mod_broadcom_param_bits 48
409 #define fourcc_mod_broadcom_code(val, params) \
410 	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
411 #define fourcc_mod_broadcom_param(m) \
412 	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
413 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
414 #define fourcc_mod_broadcom_mod(m) \
415 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
416 		 __fourcc_mod_broadcom_param_shift))
417 
418 /*
419  * Broadcom VC4 "T" format
420  *
421  * This is the primary layout that the V3D GPU can texture from (it
422  * can't do linear).  The T format has:
423  *
424  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
425  *   pixels at 32 bit depth.
426  *
427  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
428  *   16x16 pixels).
429  *
430  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
431  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
432  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
433  *
434  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
435  *   tiles) or right-to-left (odd rows of 4k tiles).
436  */
437 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
438 
439 /*
440  * Broadcom SAND format
441  *
442  * This is the native format that the H.264 codec block uses.  For VC4
443  * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
444  *
445  * The image can be considered to be split into columns, and the
446  * columns are placed consecutively into memory.  The width of those
447  * columns can be either 32, 64, 128, or 256 pixels, but in practice
448  * only 128 pixel columns are used.
449  *
450  * The pitch between the start of each column is set to optimally
451  * switch between SDRAM banks. This is passed as the number of lines
452  * of column width in the modifier (we can't use the stride value due
453  * to various core checks that look at it , so you should set the
454  * stride to width*cpp).
455  *
456  * Note that the column height for this format modifier is the same
457  * for all of the planes, assuming that each column contains both Y
458  * and UV.  Some SAND-using hardware stores UV in a separate tiled
459  * image from Y to reduce the column height, which is not supported
460  * with these modifiers.
461  */
462 
463 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
464 	fourcc_mod_broadcom_code(2, v)
465 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
466 	fourcc_mod_broadcom_code(3, v)
467 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
468 	fourcc_mod_broadcom_code(4, v)
469 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
470 	fourcc_mod_broadcom_code(5, v)
471 
472 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
473 	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
474 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
475 	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
476 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
477 	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
478 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
479 	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
480 
481 /* Broadcom UIF format
482  *
483  * This is the common format for the current Broadcom multimedia
484  * blocks, including V3D 3.x and newer, newer video codecs, and
485  * displays.
486  *
487  * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
488  * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
489  * stored in columns, with padding between the columns to ensure that
490  * moving from one column to the next doesn't hit the same SDRAM page
491  * bank.
492  *
493  * To calculate the padding, it is assumed that each hardware block
494  * and the software driving it knows the platform's SDRAM page size,
495  * number of banks, and XOR address, and that it's identical between
496  * all blocks using the format.  This tiling modifier will use XOR as
497  * necessary to reduce the padding.  If a hardware block can't do XOR,
498  * the assumption is that a no-XOR tiling modifier will be created.
499  */
500 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
501 
502 /*
503  * Arm Framebuffer Compression (AFBC) modifiers
504  *
505  * AFBC is a proprietary lossless image compression protocol and format.
506  * It provides fine-grained random access and minimizes the amount of data
507  * transferred between IP blocks.
508  *
509  * AFBC has several features which may be supported and/or used, which are
510  * represented using bits in the modifier. Not all combinations are valid,
511  * and different devices or use-cases may support different combinations.
512  */
513 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)	fourcc_mod_code(ARM, __afbc_mode)
514 
515 /*
516  * AFBC superblock size
517  *
518  * Indicates the superblock size(s) used for the AFBC buffer. The buffer
519  * size (in pixels) must be aligned to a multiple of the superblock size.
520  * Four lowest significant bits(LSBs) are reserved for block size.
521  */
522 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf
523 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)
524 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)
525 
526 /*
527  * AFBC lossless colorspace transform
528  *
529  * Indicates that the buffer makes use of the AFBC lossless colorspace
530  * transform.
531  */
532 #define AFBC_FORMAT_MOD_YTR     (1ULL <<  4)
533 
534 /*
535  * AFBC block-split
536  *
537  * Indicates that the payload of each superblock is split. The second
538  * half of the payload is positioned at a predefined offset from the start
539  * of the superblock payload.
540  */
541 #define AFBC_FORMAT_MOD_SPLIT   (1ULL <<  5)
542 
543 /*
544  * AFBC sparse layout
545  *
546  * This flag indicates that the payload of each superblock must be stored at a
547  * predefined position relative to the other superblocks in the same AFBC
548  * buffer. This order is the same order used by the header buffer. In this mode
549  * each superblock is given the same amount of space as an uncompressed
550  * superblock of the particular format would require, rounding up to the next
551  * multiple of 128 bytes in size.
552  */
553 #define AFBC_FORMAT_MOD_SPARSE  (1ULL <<  6)
554 
555 /*
556  * AFBC copy-block restrict
557  *
558  * Buffers with this flag must obey the copy-block restriction. The restriction
559  * is such that there are no copy-blocks referring across the border of 8x8
560  * blocks. For the subsampled data the 8x8 limitation is also subsampled.
561  */
562 #define AFBC_FORMAT_MOD_CBR     (1ULL <<  7)
563 
564 /*
565  * AFBC tiled layout
566  *
567  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
568  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
569  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
570  * larger bpp formats. The order between the tiles is scan line.
571  * When the tiled layout is used, the buffer size (in pixels) must be aligned
572  * to the tile size.
573  */
574 #define AFBC_FORMAT_MOD_TILED   (1ULL <<  8)
575 
576 /*
577  * AFBC solid color blocks
578  *
579  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
580  * can be reduced if a whole superblock is a single color.
581  */
582 #define AFBC_FORMAT_MOD_SC      (1ULL <<  9)
583 
584 #if defined(__cplusplus)
585 }
586 #endif
587 
588 #endif /* DRM_FOURCC_H */
589