1 /*
2  * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
3  *
4  * Copyright (C) 2008 David Brownell
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/bcd.h>
14 #include <linux/slab.h>
15 #include <linux/rtc.h>
16 #include <linux/workqueue.h>
17 
18 #include <linux/spi/spi.h>
19 #include <linux/spi/ds1305.h>
20 #include <linux/module.h>
21 
22 
23 /*
24  * Registers ... mask DS1305_WRITE into register address to write,
25  * otherwise you're reading it.  All non-bitmask values are BCD.
26  */
27 #define DS1305_WRITE		0x80
28 
29 
30 /* RTC date/time ... the main special cases are that we:
31  *  - Need fancy "hours" encoding in 12hour mode
32  *  - Don't rely on the "day-of-week" field (or tm_wday)
33  *  - Are a 21st-century clock (2000 <= year < 2100)
34  */
35 #define DS1305_RTC_LEN		7		/* bytes for RTC regs */
36 
37 #define DS1305_SEC		0x00		/* register addresses */
38 #define DS1305_MIN		0x01
39 #define DS1305_HOUR		0x02
40 #	define DS1305_HR_12		0x40	/* set == 12 hr mode */
41 #	define DS1305_HR_PM		0x20	/* set == PM (12hr mode) */
42 #define DS1305_WDAY		0x03
43 #define DS1305_MDAY		0x04
44 #define DS1305_MON		0x05
45 #define DS1305_YEAR		0x06
46 
47 
48 /* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
49  * DS1305_ALM_DISABLE disables a match field (some combos are bad).
50  *
51  * NOTE that since we don't use WDAY, we limit ourselves to alarms
52  * only one day into the future (vs potentially up to a week).
53  *
54  * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
55  * don't currently support them.  We'd either need to do it only when
56  * no alarm is pending (not the standard model), or to use the second
57  * alarm (implying that this is a DS1305 not DS1306, *and* that either
58  * it's wired up a second IRQ we know, or that INTCN is set)
59  */
60 #define DS1305_ALM_LEN		4		/* bytes for ALM regs */
61 #define DS1305_ALM_DISABLE	0x80
62 
63 #define DS1305_ALM0(r)		(0x07 + (r))	/* register addresses */
64 #define DS1305_ALM1(r)		(0x0b + (r))
65 
66 
67 /* three control registers */
68 #define DS1305_CONTROL_LEN	3		/* bytes of control regs */
69 
70 #define DS1305_CONTROL		0x0f		/* register addresses */
71 #	define DS1305_nEOSC		0x80	/* low enables oscillator */
72 #	define DS1305_WP		0x40	/* write protect */
73 #	define DS1305_INTCN		0x04	/* clear == only int0 used */
74 #	define DS1306_1HZ		0x04	/* enable 1Hz output */
75 #	define DS1305_AEI1		0x02	/* enable ALM1 IRQ */
76 #	define DS1305_AEI0		0x01	/* enable ALM0 IRQ */
77 #define DS1305_STATUS		0x10
78 /* status has just AEIx bits, mirrored as IRQFx */
79 #define DS1305_TRICKLE		0x11
80 /* trickle bits are defined in <linux/spi/ds1305.h> */
81 
82 /* a bunch of NVRAM */
83 #define DS1305_NVRAM_LEN	96		/* bytes of NVRAM */
84 
85 #define DS1305_NVRAM		0x20		/* register addresses */
86 
87 
88 struct ds1305 {
89 	struct spi_device	*spi;
90 	struct rtc_device	*rtc;
91 
92 	struct work_struct	work;
93 
94 	unsigned long		flags;
95 #define FLAG_EXITING	0
96 
97 	bool			hr12;
98 	u8			ctrl[DS1305_CONTROL_LEN];
99 };
100 
101 
102 /*----------------------------------------------------------------------*/
103 
104 /*
105  * Utilities ...  tolerate 12-hour AM/PM notation in case of non-Linux
106  * software (like a bootloader) which may require it.
107  */
108 
bcd2hour(u8 bcd)109 static unsigned bcd2hour(u8 bcd)
110 {
111 	if (bcd & DS1305_HR_12) {
112 		unsigned	hour = 0;
113 
114 		bcd &= ~DS1305_HR_12;
115 		if (bcd & DS1305_HR_PM) {
116 			hour = 12;
117 			bcd &= ~DS1305_HR_PM;
118 		}
119 		hour += bcd2bin(bcd);
120 		return hour - 1;
121 	}
122 	return bcd2bin(bcd);
123 }
124 
hour2bcd(bool hr12,int hour)125 static u8 hour2bcd(bool hr12, int hour)
126 {
127 	if (hr12) {
128 		hour++;
129 		if (hour <= 12)
130 			return DS1305_HR_12 | bin2bcd(hour);
131 		hour -= 12;
132 		return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
133 	}
134 	return bin2bcd(hour);
135 }
136 
137 /*----------------------------------------------------------------------*/
138 
139 /*
140  * Interface to RTC framework
141  */
142 
ds1305_alarm_irq_enable(struct device * dev,unsigned int enabled)143 static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
144 {
145 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
146 	u8		buf[2];
147 	long		err = -EINVAL;
148 
149 	buf[0] = DS1305_WRITE | DS1305_CONTROL;
150 	buf[1] = ds1305->ctrl[0];
151 
152 	if (enabled) {
153 		if (ds1305->ctrl[0] & DS1305_AEI0)
154 			goto done;
155 		buf[1] |= DS1305_AEI0;
156 	} else {
157 		if (!(buf[1] & DS1305_AEI0))
158 			goto done;
159 		buf[1] &= ~DS1305_AEI0;
160 	}
161 	err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
162 	if (err >= 0)
163 		ds1305->ctrl[0] = buf[1];
164 done:
165 	return err;
166 
167 }
168 
169 
170 /*
171  * Get/set of date and time is pretty normal.
172  */
173 
ds1305_get_time(struct device * dev,struct rtc_time * time)174 static int ds1305_get_time(struct device *dev, struct rtc_time *time)
175 {
176 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
177 	u8		addr = DS1305_SEC;
178 	u8		buf[DS1305_RTC_LEN];
179 	int		status;
180 
181 	/* Use write-then-read to get all the date/time registers
182 	 * since dma from stack is nonportable
183 	 */
184 	status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
185 			buf, sizeof(buf));
186 	if (status < 0)
187 		return status;
188 
189 	dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
190 
191 	/* Decode the registers */
192 	time->tm_sec = bcd2bin(buf[DS1305_SEC]);
193 	time->tm_min = bcd2bin(buf[DS1305_MIN]);
194 	time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
195 	time->tm_wday = buf[DS1305_WDAY] - 1;
196 	time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
197 	time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
198 	time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
199 
200 	dev_vdbg(dev, "%s secs=%d, mins=%d, "
201 		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
202 		"read", time->tm_sec, time->tm_min,
203 		time->tm_hour, time->tm_mday,
204 		time->tm_mon, time->tm_year, time->tm_wday);
205 
206 	return 0;
207 }
208 
ds1305_set_time(struct device * dev,struct rtc_time * time)209 static int ds1305_set_time(struct device *dev, struct rtc_time *time)
210 {
211 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
212 	u8		buf[1 + DS1305_RTC_LEN];
213 	u8		*bp = buf;
214 
215 	dev_vdbg(dev, "%s secs=%d, mins=%d, "
216 		"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
217 		"write", time->tm_sec, time->tm_min,
218 		time->tm_hour, time->tm_mday,
219 		time->tm_mon, time->tm_year, time->tm_wday);
220 
221 	/* Write registers starting at the first time/date address. */
222 	*bp++ = DS1305_WRITE | DS1305_SEC;
223 
224 	*bp++ = bin2bcd(time->tm_sec);
225 	*bp++ = bin2bcd(time->tm_min);
226 	*bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
227 	*bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
228 	*bp++ = bin2bcd(time->tm_mday);
229 	*bp++ = bin2bcd(time->tm_mon + 1);
230 	*bp++ = bin2bcd(time->tm_year - 100);
231 
232 	dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
233 
234 	/* use write-then-read since dma from stack is nonportable */
235 	return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
236 			NULL, 0);
237 }
238 
239 /*
240  * Get/set of alarm is a bit funky:
241  *
242  * - First there's the inherent raciness of getting the (partitioned)
243  *   status of an alarm that could trigger while we're reading parts
244  *   of that status.
245  *
246  * - Second there's its limited range (we could increase it a bit by
247  *   relying on WDAY), which means it will easily roll over.
248  *
249  * - Third there's the choice of two alarms and alarm signals.
250  *   Here we use ALM0 and expect that nINT0 (open drain) is used;
251  *   that's the only real option for DS1306 runtime alarms, and is
252  *   natural on DS1305.
253  *
254  * - Fourth, there's also ALM1, and a second interrupt signal:
255  *     + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
256  *     + On DS1306 ALM1 only uses INT1 (an active high pulse)
257  *       and it won't work when VCC1 is active.
258  *
259  *   So to be most general, we should probably set both alarms to the
260  *   same value, letting ALM1 be the wakeup event source on DS1306
261  *   and handling several wiring options on DS1305.
262  *
263  * - Fifth, we support the polled mode (as well as possible; why not?)
264  *   even when no interrupt line is wired to an IRQ.
265  */
266 
267 /*
268  * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
269  */
ds1305_get_alarm(struct device * dev,struct rtc_wkalrm * alm)270 static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
271 {
272 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
273 	struct spi_device *spi = ds1305->spi;
274 	u8		addr;
275 	int		status;
276 	u8		buf[DS1305_ALM_LEN];
277 
278 	/* Refresh control register cache BEFORE reading ALM0 registers,
279 	 * since reading alarm registers acks any pending IRQ.  That
280 	 * makes returning "pending" status a bit of a lie, but that bit
281 	 * of EFI status is at best fragile anyway (given IRQ handlers).
282 	 */
283 	addr = DS1305_CONTROL;
284 	status = spi_write_then_read(spi, &addr, sizeof(addr),
285 			ds1305->ctrl, sizeof(ds1305->ctrl));
286 	if (status < 0)
287 		return status;
288 
289 	alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
290 	alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
291 
292 	/* get and check ALM0 registers */
293 	addr = DS1305_ALM0(DS1305_SEC);
294 	status = spi_write_then_read(spi, &addr, sizeof(addr),
295 			buf, sizeof(buf));
296 	if (status < 0)
297 		return status;
298 
299 	dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
300 		"alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
301 		buf[DS1305_HOUR], buf[DS1305_WDAY]);
302 
303 	if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
304 			|| (DS1305_ALM_DISABLE & buf[DS1305_MIN])
305 			|| (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
306 		return -EIO;
307 
308 	/* Stuff these values into alm->time and let RTC framework code
309 	 * fill in the rest ... and also handle rollover to tomorrow when
310 	 * that's needed.
311 	 */
312 	alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
313 	alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
314 	alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
315 
316 	return 0;
317 }
318 
319 /*
320  * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
321  */
ds1305_set_alarm(struct device * dev,struct rtc_wkalrm * alm)322 static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
323 {
324 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
325 	struct spi_device *spi = ds1305->spi;
326 	unsigned long	now, later;
327 	struct rtc_time	tm;
328 	int		status;
329 	u8		buf[1 + DS1305_ALM_LEN];
330 
331 	/* convert desired alarm to time_t */
332 	status = rtc_tm_to_time(&alm->time, &later);
333 	if (status < 0)
334 		return status;
335 
336 	/* Read current time as time_t */
337 	status = ds1305_get_time(dev, &tm);
338 	if (status < 0)
339 		return status;
340 	status = rtc_tm_to_time(&tm, &now);
341 	if (status < 0)
342 		return status;
343 
344 	/* make sure alarm fires within the next 24 hours */
345 	if (later <= now)
346 		return -EINVAL;
347 	if ((later - now) > 24 * 60 * 60)
348 		return -EDOM;
349 
350 	/* disable alarm if needed */
351 	if (ds1305->ctrl[0] & DS1305_AEI0) {
352 		ds1305->ctrl[0] &= ~DS1305_AEI0;
353 
354 		buf[0] = DS1305_WRITE | DS1305_CONTROL;
355 		buf[1] = ds1305->ctrl[0];
356 		status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
357 		if (status < 0)
358 			return status;
359 	}
360 
361 	/* write alarm */
362 	buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
363 	buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
364 	buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
365 	buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
366 	buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
367 
368 	dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
369 		"alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
370 		buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
371 
372 	status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
373 	if (status < 0)
374 		return status;
375 
376 	/* enable alarm if requested */
377 	if (alm->enabled) {
378 		ds1305->ctrl[0] |= DS1305_AEI0;
379 
380 		buf[0] = DS1305_WRITE | DS1305_CONTROL;
381 		buf[1] = ds1305->ctrl[0];
382 		status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
383 	}
384 
385 	return status;
386 }
387 
388 #ifdef CONFIG_PROC_FS
389 
ds1305_proc(struct device * dev,struct seq_file * seq)390 static int ds1305_proc(struct device *dev, struct seq_file *seq)
391 {
392 	struct ds1305	*ds1305 = dev_get_drvdata(dev);
393 	char		*diodes = "no";
394 	char		*resistors = "";
395 
396 	/* ctrl[2] is treated as read-only; no locking needed */
397 	if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
398 		switch (ds1305->ctrl[2] & 0x0c) {
399 		case DS1305_TRICKLE_DS2:
400 			diodes = "2 diodes, ";
401 			break;
402 		case DS1305_TRICKLE_DS1:
403 			diodes = "1 diode, ";
404 			break;
405 		default:
406 			goto done;
407 		}
408 		switch (ds1305->ctrl[2] & 0x03) {
409 		case DS1305_TRICKLE_2K:
410 			resistors = "2k Ohm";
411 			break;
412 		case DS1305_TRICKLE_4K:
413 			resistors = "4k Ohm";
414 			break;
415 		case DS1305_TRICKLE_8K:
416 			resistors = "8k Ohm";
417 			break;
418 		default:
419 			diodes = "no";
420 			break;
421 		}
422 	}
423 
424 done:
425 	seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
426 
427 	return 0;
428 }
429 
430 #else
431 #define ds1305_proc	NULL
432 #endif
433 
434 static const struct rtc_class_ops ds1305_ops = {
435 	.read_time	= ds1305_get_time,
436 	.set_time	= ds1305_set_time,
437 	.read_alarm	= ds1305_get_alarm,
438 	.set_alarm	= ds1305_set_alarm,
439 	.proc		= ds1305_proc,
440 	.alarm_irq_enable = ds1305_alarm_irq_enable,
441 };
442 
ds1305_work(struct work_struct * work)443 static void ds1305_work(struct work_struct *work)
444 {
445 	struct ds1305	*ds1305 = container_of(work, struct ds1305, work);
446 	struct mutex	*lock = &ds1305->rtc->ops_lock;
447 	struct spi_device *spi = ds1305->spi;
448 	u8		buf[3];
449 	int		status;
450 
451 	/* lock to protect ds1305->ctrl */
452 	mutex_lock(lock);
453 
454 	/* Disable the IRQ, and clear its status ... for now, we "know"
455 	 * that if more than one alarm is active, they're in sync.
456 	 * Note that reading ALM data registers also clears IRQ status.
457 	 */
458 	ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
459 	ds1305->ctrl[1] = 0;
460 
461 	buf[0] = DS1305_WRITE | DS1305_CONTROL;
462 	buf[1] = ds1305->ctrl[0];
463 	buf[2] = 0;
464 
465 	status = spi_write_then_read(spi, buf, sizeof(buf),
466 			NULL, 0);
467 	if (status < 0)
468 		dev_dbg(&spi->dev, "clear irq --> %d\n", status);
469 
470 	mutex_unlock(lock);
471 
472 	if (!test_bit(FLAG_EXITING, &ds1305->flags))
473 		enable_irq(spi->irq);
474 
475 	rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
476 }
477 
478 /*
479  * This "real" IRQ handler hands off to a workqueue mostly to allow
480  * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
481  * I/O requests in IRQ context (to clear the IRQ status).
482  */
ds1305_irq(int irq,void * p)483 static irqreturn_t ds1305_irq(int irq, void *p)
484 {
485 	struct ds1305		*ds1305 = p;
486 
487 	disable_irq(irq);
488 	schedule_work(&ds1305->work);
489 	return IRQ_HANDLED;
490 }
491 
492 /*----------------------------------------------------------------------*/
493 
494 /*
495  * Interface for NVRAM
496  */
497 
msg_init(struct spi_message * m,struct spi_transfer * x,u8 * addr,size_t count,char * tx,char * rx)498 static void msg_init(struct spi_message *m, struct spi_transfer *x,
499 		u8 *addr, size_t count, char *tx, char *rx)
500 {
501 	spi_message_init(m);
502 	memset(x, 0, 2 * sizeof(*x));
503 
504 	x->tx_buf = addr;
505 	x->len = 1;
506 	spi_message_add_tail(x, m);
507 
508 	x++;
509 
510 	x->tx_buf = tx;
511 	x->rx_buf = rx;
512 	x->len = count;
513 	spi_message_add_tail(x, m);
514 }
515 
ds1305_nvram_read(void * priv,unsigned int off,void * buf,size_t count)516 static int ds1305_nvram_read(void *priv, unsigned int off, void *buf,
517 			     size_t count)
518 {
519 	struct ds1305		*ds1305 = priv;
520 	struct spi_device	*spi = ds1305->spi;
521 	u8			addr;
522 	struct spi_message	m;
523 	struct spi_transfer	x[2];
524 
525 	addr = DS1305_NVRAM + off;
526 	msg_init(&m, x, &addr, count, NULL, buf);
527 
528 	return spi_sync(spi, &m);
529 }
530 
ds1305_nvram_write(void * priv,unsigned int off,void * buf,size_t count)531 static int ds1305_nvram_write(void *priv, unsigned int off, void *buf,
532 			      size_t count)
533 {
534 	struct ds1305		*ds1305 = priv;
535 	struct spi_device	*spi = ds1305->spi;
536 	u8			addr;
537 	struct spi_message	m;
538 	struct spi_transfer	x[2];
539 
540 	addr = (DS1305_WRITE | DS1305_NVRAM) + off;
541 	msg_init(&m, x, &addr, count, buf, NULL);
542 
543 	return spi_sync(spi, &m);
544 }
545 
546 /*----------------------------------------------------------------------*/
547 
548 /*
549  * Interface to SPI stack
550  */
551 
ds1305_probe(struct spi_device * spi)552 static int ds1305_probe(struct spi_device *spi)
553 {
554 	struct ds1305			*ds1305;
555 	int				status;
556 	u8				addr, value;
557 	struct ds1305_platform_data	*pdata = dev_get_platdata(&spi->dev);
558 	bool				write_ctrl = false;
559 	struct nvmem_config ds1305_nvmem_cfg = {
560 		.name = "ds1305_nvram",
561 		.word_size = 1,
562 		.stride = 1,
563 		.size = DS1305_NVRAM_LEN,
564 		.reg_read = ds1305_nvram_read,
565 		.reg_write = ds1305_nvram_write,
566 	};
567 
568 	/* Sanity check board setup data.  This may be hooked up
569 	 * in 3wire mode, but we don't care.  Note that unless
570 	 * there's an inverter in place, this needs SPI_CS_HIGH!
571 	 */
572 	if ((spi->bits_per_word && spi->bits_per_word != 8)
573 			|| (spi->max_speed_hz > 2000000)
574 			|| !(spi->mode & SPI_CPHA))
575 		return -EINVAL;
576 
577 	/* set up driver data */
578 	ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
579 	if (!ds1305)
580 		return -ENOMEM;
581 	ds1305->spi = spi;
582 	spi_set_drvdata(spi, ds1305);
583 
584 	/* read and cache control registers */
585 	addr = DS1305_CONTROL;
586 	status = spi_write_then_read(spi, &addr, sizeof(addr),
587 			ds1305->ctrl, sizeof(ds1305->ctrl));
588 	if (status < 0) {
589 		dev_dbg(&spi->dev, "can't %s, %d\n",
590 				"read", status);
591 		return status;
592 	}
593 
594 	dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
595 
596 	/* Sanity check register values ... partially compensating for the
597 	 * fact that SPI has no device handshake.  A pullup on MISO would
598 	 * make these tests fail; but not all systems will have one.  If
599 	 * some register is neither 0x00 nor 0xff, a chip is likely there.
600 	 */
601 	if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
602 		dev_dbg(&spi->dev, "RTC chip is not present\n");
603 		return -ENODEV;
604 	}
605 	if (ds1305->ctrl[2] == 0)
606 		dev_dbg(&spi->dev, "chip may not be present\n");
607 
608 	/* enable writes if needed ... if we were paranoid it would
609 	 * make sense to enable them only when absolutely necessary.
610 	 */
611 	if (ds1305->ctrl[0] & DS1305_WP) {
612 		u8		buf[2];
613 
614 		ds1305->ctrl[0] &= ~DS1305_WP;
615 
616 		buf[0] = DS1305_WRITE | DS1305_CONTROL;
617 		buf[1] = ds1305->ctrl[0];
618 		status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
619 
620 		dev_dbg(&spi->dev, "clear WP --> %d\n", status);
621 		if (status < 0)
622 			return status;
623 	}
624 
625 	/* on DS1305, maybe start oscillator; like most low power
626 	 * oscillators, it may take a second to stabilize
627 	 */
628 	if (ds1305->ctrl[0] & DS1305_nEOSC) {
629 		ds1305->ctrl[0] &= ~DS1305_nEOSC;
630 		write_ctrl = true;
631 		dev_warn(&spi->dev, "SET TIME!\n");
632 	}
633 
634 	/* ack any pending IRQs */
635 	if (ds1305->ctrl[1]) {
636 		ds1305->ctrl[1] = 0;
637 		write_ctrl = true;
638 	}
639 
640 	/* this may need one-time (re)init */
641 	if (pdata) {
642 		/* maybe enable trickle charge */
643 		if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
644 			ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
645 						| pdata->trickle;
646 			write_ctrl = true;
647 		}
648 
649 		/* on DS1306, configure 1 Hz signal */
650 		if (pdata->is_ds1306) {
651 			if (pdata->en_1hz) {
652 				if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
653 					ds1305->ctrl[0] |= DS1306_1HZ;
654 					write_ctrl = true;
655 				}
656 			} else {
657 				if (ds1305->ctrl[0] & DS1306_1HZ) {
658 					ds1305->ctrl[0] &= ~DS1306_1HZ;
659 					write_ctrl = true;
660 				}
661 			}
662 		}
663 	}
664 
665 	if (write_ctrl) {
666 		u8		buf[4];
667 
668 		buf[0] = DS1305_WRITE | DS1305_CONTROL;
669 		buf[1] = ds1305->ctrl[0];
670 		buf[2] = ds1305->ctrl[1];
671 		buf[3] = ds1305->ctrl[2];
672 		status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
673 		if (status < 0) {
674 			dev_dbg(&spi->dev, "can't %s, %d\n",
675 					"write", status);
676 			return status;
677 		}
678 
679 		dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
680 	}
681 
682 	/* see if non-Linux software set up AM/PM mode */
683 	addr = DS1305_HOUR;
684 	status = spi_write_then_read(spi, &addr, sizeof(addr),
685 				&value, sizeof(value));
686 	if (status < 0) {
687 		dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
688 		return status;
689 	}
690 
691 	ds1305->hr12 = (DS1305_HR_12 & value) != 0;
692 	if (ds1305->hr12)
693 		dev_dbg(&spi->dev, "AM/PM\n");
694 
695 	/* register RTC ... from here on, ds1305->ctrl needs locking */
696 	ds1305->rtc = devm_rtc_allocate_device(&spi->dev);
697 	if (IS_ERR(ds1305->rtc)) {
698 		return PTR_ERR(ds1305->rtc);
699 	}
700 
701 	ds1305->rtc->ops = &ds1305_ops;
702 
703 	ds1305_nvmem_cfg.priv = ds1305;
704 	ds1305->rtc->nvram_old_abi = true;
705 	status = rtc_register_device(ds1305->rtc);
706 	if (status) {
707 		dev_dbg(&spi->dev, "register rtc --> %d\n", status);
708 		return status;
709 	}
710 
711 	rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg);
712 
713 	/* Maybe set up alarm IRQ; be ready to handle it triggering right
714 	 * away.  NOTE that we don't share this.  The signal is active low,
715 	 * and we can't ack it before a SPI message delay.  We temporarily
716 	 * disable the IRQ until it's acked, which lets us work with more
717 	 * IRQ trigger modes (not all IRQ controllers can do falling edge).
718 	 */
719 	if (spi->irq) {
720 		INIT_WORK(&ds1305->work, ds1305_work);
721 		status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
722 				0, dev_name(&ds1305->rtc->dev), ds1305);
723 		if (status < 0) {
724 			dev_err(&spi->dev, "request_irq %d --> %d\n",
725 					spi->irq, status);
726 		} else {
727 			device_set_wakeup_capable(&spi->dev, 1);
728 		}
729 	}
730 
731 	return 0;
732 }
733 
ds1305_remove(struct spi_device * spi)734 static int ds1305_remove(struct spi_device *spi)
735 {
736 	struct ds1305 *ds1305 = spi_get_drvdata(spi);
737 
738 	/* carefully shut down irq and workqueue, if present */
739 	if (spi->irq) {
740 		set_bit(FLAG_EXITING, &ds1305->flags);
741 		devm_free_irq(&spi->dev, spi->irq, ds1305);
742 		cancel_work_sync(&ds1305->work);
743 	}
744 
745 	return 0;
746 }
747 
748 static struct spi_driver ds1305_driver = {
749 	.driver.name	= "rtc-ds1305",
750 	.probe		= ds1305_probe,
751 	.remove		= ds1305_remove,
752 	/* REVISIT add suspend/resume */
753 };
754 
755 module_spi_driver(ds1305_driver);
756 
757 MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
758 MODULE_LICENSE("GPL");
759 MODULE_ALIAS("spi:rtc-ds1305");
760