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Searched refs:GATE_PERI1 (Results 1 – 5 of 5) sorted by relevance

/linux-4.19.296/drivers/clk/mediatek/
Dclk-mt8135.c457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ macro
501 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
502 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
503 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
504 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
505 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
506 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
507 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
508 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
509 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
Dclk-mt2701.c826 #define GATE_PERI1(_id, _name, _parent, _shift) { \ macro
869 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
870 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
871 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
872 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
873 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
874 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
875 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
876 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
877 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
[all …]
Dclk-mt2712.c1050 #define GATE_PERI1(_id, _name, _parent, _shift) { \ macro
1125 GATE_PERI1(CLK_PERI_SPI, "per_spi",
1127 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1129 GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1131 GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1133 GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1135 GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1137 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1139 GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1141 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
[all …]
Dclk-mt7622.c105 #define GATE_PERI1(_id, _name, _parent, _shift) { \ macro
512 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
513 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
Dclk-mt8173.c678 #define GATE_PERI1(_id, _name, _parent, _shift) { \ macro
722 GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
723 GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
724 GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),