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Searched refs:HCLK_ROM (Results 1 – 11 of 11) sorted by relevance

/linux-4.19.296/include/dt-bindings/clock/
Drk3036-cru.h99 #define HCLK_ROM 467 macro
Drk3188-cru-common.h132 #define HCLK_ROM 463 macro
Drk3288-cru.h194 #define HCLK_ROM 467 macro
Drk3368-cru.h178 #define HCLK_ROM 467 macro
Drk3399-cru.h325 #define HCLK_ROM 476 macro
/linux-4.19.296/drivers/clk/rockchip/
Dclk-rk3036.c376 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
Dclk-rk3188.c459 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
Dclk-rk3368.c697 GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
Dclk-rk3288.c662 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
Dclk-rk3399.c977 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
/linux-4.19.296/drivers/clk/renesas/
Dr9a06g032-clocks.c249 D_GATE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),