1 /* 2 * Device driver for regulators in hi655x IC 3 * 4 * Copyright (c) 2016 Hisilicon. 5 * 6 * Authors: 7 * Chen Feng <puck.chen@hisilicon.com> 8 * Fei Wang <w.f@huawei.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #ifndef __HI655X_PMIC_H 16 #define __HI655X_PMIC_H 17 18 /* Hi655x registers are mapped to memory bus in 4 bytes stride */ 19 #define HI655X_STRIDE 4 20 #define HI655X_BUS_ADDR(x) ((x) << 2) 21 22 #define HI655X_BITS 8 23 24 #define HI655X_NR_IRQ 32 25 26 #define HI655X_IRQ_STAT_BASE (0x003 << 2) 27 #define HI655X_IRQ_MASK_BASE (0x007 << 2) 28 #define HI655X_ANA_IRQM_BASE (0x1b5 << 2) 29 #define HI655X_IRQ_ARRAY 4 30 #define HI655X_IRQ_MASK 0xFF 31 #define HI655X_IRQ_CLR 0xFF 32 #define HI655X_VER_REG 0x00 33 34 #define PMU_VER_START 0x10 35 #define PMU_VER_END 0x38 36 37 #define RESERVE_INT 7 38 #define PWRON_D20R_INT 6 39 #define PWRON_D20F_INT 5 40 #define PWRON_D4SR_INT 4 41 #define VSYS_6P0_D200UR_INT 3 42 #define VSYS_UV_D3R_INT 2 43 #define VSYS_2P5_R_INT 1 44 #define OTMP_D1R_INT 0 45 46 #define RESERVE_INT_MASK BIT(RESERVE_INT) 47 #define PWRON_D20R_INT_MASK BIT(PWRON_D20R_INT) 48 #define PWRON_D20F_INT_MASK BIT(PWRON_D20F_INT) 49 #define PWRON_D4SR_INT_MASK BIT(PWRON_D4SR_INT) 50 #define VSYS_6P0_D200UR_INT_MASK BIT(VSYS_6P0_D200UR_INT) 51 #define VSYS_UV_D3R_INT_MASK BIT(VSYS_UV_D3R_INT) 52 #define VSYS_2P5_R_INT_MASK BIT(VSYS_2P5_R_INT) 53 #define OTMP_D1R_INT_MASK BIT(OTMP_D1R_INT) 54 55 struct hi655x_pmic { 56 struct resource *res; 57 struct device *dev; 58 struct regmap *regmap; 59 int gpio; 60 unsigned int ver; 61 struct regmap_irq_chip_data *irq_data; 62 }; 63 64 #endif 65