1 /* 2 * ISH registers definitions 3 * 4 * Copyright (c) 2012-2016, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _ISHTP_ISH_REGS_H_ 17 #define _ISHTP_ISH_REGS_H_ 18 19 20 /*** IPC PCI Offsets and sizes ***/ 21 /* ISH IPC Base Address */ 22 #define IPC_REG_BASE 0x0000 23 /* Peripheral Interrupt Status Register */ 24 #define IPC_REG_PISR_CHV_AB (IPC_REG_BASE + 0x00) 25 /* Peripheral Interrupt Mask Register */ 26 #define IPC_REG_PIMR_CHV_AB (IPC_REG_BASE + 0x04) 27 /*BXT, CHV_K0*/ 28 /*Peripheral Interrupt Status Register */ 29 #define IPC_REG_PISR_BXT (IPC_REG_BASE + 0x0C) 30 /*Peripheral Interrupt Mask Register */ 31 #define IPC_REG_PIMR_BXT (IPC_REG_BASE + 0x08) 32 /***********************************/ 33 /* ISH Host Firmware status Register */ 34 #define IPC_REG_ISH_HOST_FWSTS (IPC_REG_BASE + 0x34) 35 /* Host Communication Register */ 36 #define IPC_REG_HOST_COMM (IPC_REG_BASE + 0x38) 37 /* Reset register */ 38 #define IPC_REG_ISH_RST (IPC_REG_BASE + 0x44) 39 40 /* Inbound doorbell register Host to ISH */ 41 #define IPC_REG_HOST2ISH_DRBL (IPC_REG_BASE + 0x48) 42 /* Outbound doorbell register ISH to Host */ 43 #define IPC_REG_ISH2HOST_DRBL (IPC_REG_BASE + 0x54) 44 /* ISH to HOST message registers */ 45 #define IPC_REG_ISH2HOST_MSG (IPC_REG_BASE + 0x60) 46 /* HOST to ISH message registers */ 47 #define IPC_REG_HOST2ISH_MSG (IPC_REG_BASE + 0xE0) 48 /* REMAP2 to enable DMA (D3 RCR) */ 49 #define IPC_REG_ISH_RMP2 (IPC_REG_BASE + 0x368) 50 51 #define IPC_REG_MAX (IPC_REG_BASE + 0x400) 52 53 /*** register bits - HISR ***/ 54 /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */ 55 #define IPC_INT_HOST2ISH_BIT (1<<0) 56 /***********************************/ 57 /*CHV_A0, CHV_B0*/ 58 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ 59 #define IPC_INT_ISH2HOST_BIT_CHV_AB (1<<3) 60 /*BXT, CHV_K0*/ 61 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */ 62 #define IPC_INT_ISH2HOST_BIT_BXT (1<<0) 63 /***********************************/ 64 65 /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */ 66 #define IPC_INT_ISH2HOST_CLR_MASK_BIT (1<<11) 67 68 /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ 69 #define IPC_INT_ISH2HOST_CLR_OFFS (0) 70 71 /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */ 72 #define IPC_INT_ISH2HOST_CLR_BIT (1<<IPC_INT_ISH2HOST_CLR_OFFS) 73 74 /* bit corresponds busy bit in doorbell registers */ 75 #define IPC_DRBL_BUSY_OFFS (31) 76 #define IPC_DRBL_BUSY_BIT (1<<IPC_DRBL_BUSY_OFFS) 77 78 #define IPC_HOST_OWNS_MSG_OFFS (30) 79 80 /* 81 * A0: bit means that host owns MSGnn registers and is reading them. 82 * ISH FW may not write to them 83 */ 84 #define IPC_HOST_OWNS_MSG_BIT (1<<IPC_HOST_OWNS_MSG_OFFS) 85 86 /* 87 * Host status bits (HOSTCOMM) 88 */ 89 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */ 90 #define IPC_HOSTCOMM_READY_OFFS (7) 91 #define IPC_HOSTCOMM_READY_BIT (1<<IPC_HOSTCOMM_READY_OFFS) 92 93 /***********************************/ 94 /*CHV_A0, CHV_B0*/ 95 #define IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB (31) 96 #define IPC_HOSTCOMM_INT_EN_BIT_CHV_AB \ 97 (1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB) 98 /*BXT, CHV_K0*/ 99 #define IPC_PIMR_INT_EN_OFFS_BXT (0) 100 #define IPC_PIMR_INT_EN_BIT_BXT (1<<IPC_PIMR_INT_EN_OFFS_BXT) 101 102 #define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT (8) 103 #define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT \ 104 (1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT) 105 /***********************************/ 106 /* 107 * both Host and ISH have ILUP at bit 0 108 * bit corresponds host ready bit in both status registers 109 */ 110 #define IPC_ILUP_OFFS (0) 111 #define IPC_ILUP_BIT (1<<IPC_ILUP_OFFS) 112 113 /* 114 * ISH FW status bits in ISH FW Status Register 115 */ 116 #define IPC_ISH_FWSTS_SHIFT 12 117 #define IPC_ISH_FWSTS_MASK GENMASK(15, 12) 118 #define IPC_GET_ISH_FWSTS(status) \ 119 (((status) & IPC_ISH_FWSTS_MASK) >> IPC_ISH_FWSTS_SHIFT) 120 121 /* 122 * FW status bits (relevant) 123 */ 124 #define IPC_FWSTS_ILUP 0x1 125 #define IPC_FWSTS_ISHTP_UP (1<<1) 126 #define IPC_FWSTS_DMA0 (1<<16) 127 #define IPC_FWSTS_DMA1 (1<<17) 128 #define IPC_FWSTS_DMA2 (1<<18) 129 #define IPC_FWSTS_DMA3 (1<<19) 130 131 #define IPC_ISH_IN_DMA \ 132 (IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3) 133 134 /* bit corresponds host ready bit in ISH FW Status Register */ 135 #define IPC_ISH_ISHTP_READY_OFFS (1) 136 #define IPC_ISH_ISHTP_READY_BIT (1<<IPC_ISH_ISHTP_READY_OFFS) 137 138 #define IPC_RMP2_DMA_ENABLED 0x1 /* Value to enable DMA, per D3 RCR */ 139 140 #define IPC_MSG_MAX_SIZE 0x80 141 142 143 #define IPC_HEADER_LENGTH_MASK 0x03FF 144 #define IPC_HEADER_PROTOCOL_MASK 0x0F 145 #define IPC_HEADER_MNG_CMD_MASK 0x0F 146 147 #define IPC_HEADER_LENGTH_OFFSET 0 148 #define IPC_HEADER_PROTOCOL_OFFSET 10 149 #define IPC_HEADER_MNG_CMD_OFFSET 16 150 151 #define IPC_HEADER_GET_LENGTH(drbl_reg) \ 152 (((drbl_reg) >> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK) 153 #define IPC_HEADER_GET_PROTOCOL(drbl_reg) \ 154 (((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK) 155 #define IPC_HEADER_GET_MNG_CMD(drbl_reg) \ 156 (((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK) 157 158 #define IPC_IS_BUSY(drbl_reg) \ 159 (((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT)) 160 161 /***********************************/ 162 /*CHV_A0, CHV_B0*/ 163 #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \ 164 (((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \ 165 ((u32)IPC_INT_ISH2HOST_BIT_CHV_AB)) 166 /*BXT, CHV_K0*/ 167 #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \ 168 (((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \ 169 ((u32)IPC_INT_ISH2HOST_BIT_BXT)) 170 /***********************************/ 171 172 #define IPC_BUILD_HEADER(length, protocol, busy) \ 173 (((busy)<<IPC_DRBL_BUSY_OFFS) | \ 174 ((protocol) << IPC_HEADER_PROTOCOL_OFFSET) | \ 175 ((length)<<IPC_HEADER_LENGTH_OFFSET)) 176 177 #define IPC_BUILD_MNG_MSG(cmd, length) \ 178 (((1)<<IPC_DRBL_BUSY_OFFS)| \ 179 ((IPC_PROTOCOL_MNG)<<IPC_HEADER_PROTOCOL_OFFSET)| \ 180 ((cmd)<<IPC_HEADER_MNG_CMD_OFFSET)| \ 181 ((length)<<IPC_HEADER_LENGTH_OFFSET)) 182 183 184 #define IPC_SET_HOST_READY(host_status) \ 185 ((host_status) |= (IPC_HOSTCOMM_READY_BIT)) 186 187 #define IPC_SET_HOST_ILUP(host_status) \ 188 ((host_status) |= (IPC_ILUP_BIT)) 189 190 #define IPC_CLEAR_HOST_READY(host_status) \ 191 ((host_status) ^= (IPC_HOSTCOMM_READY_BIT)) 192 193 #define IPC_CLEAR_HOST_ILUP(host_status) \ 194 ((host_status) ^= (IPC_ILUP_BIT)) 195 196 /* todo - temp until PIMR HW ready */ 197 #define IPC_HOST_BUSY_READING_OFFS 6 198 199 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */ 200 #define IPC_HOST_BUSY_READING_BIT (1<<IPC_HOST_BUSY_READING_OFFS) 201 202 #define IPC_SET_HOST_BUSY_READING(host_status) \ 203 ((host_status) |= (IPC_HOST_BUSY_READING_BIT)) 204 205 #define IPC_CLEAR_HOST_BUSY_READING(host_status)\ 206 ((host_status) ^= (IPC_HOST_BUSY_READING_BIT)) 207 208 209 #define IPC_IS_ISH_ISHTP_READY(ish_status) \ 210 (((ish_status) & IPC_ISH_ISHTP_READY_BIT) == \ 211 ((uint32_t)IPC_ISH_ISHTP_READY_BIT)) 212 213 #define IPC_IS_ISH_ILUP(ish_status) \ 214 (((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT)) 215 216 217 #define IPC_PROTOCOL_ISHTP 1 218 #define IPC_PROTOCOL_MNG 3 219 220 #define MNG_RX_CMPL_ENABLE 0 221 #define MNG_RX_CMPL_DISABLE 1 222 #define MNG_RX_CMPL_INDICATION 2 223 #define MNG_RESET_NOTIFY 3 224 #define MNG_RESET_NOTIFY_ACK 4 225 #define MNG_SYNC_FW_CLOCK 5 226 #define MNG_ILLEGAL_CMD 0xFF 227 228 #endif /* _ISHTP_ISH_REGS_H_ */ 229