1 /* 2 * Common variables for the Maxim MAX77843 driver 3 * 4 * Copyright (C) 2015 Samsung Electronics 5 * Author: Jaewon Kim <jaewon02.kim@samsung.com> 6 * Author: Beomho Seo <beomho.seo@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef __MAX77843_PRIVATE_H_ 15 #define __MAX77843_PRIVATE_H_ 16 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 20 #define I2C_ADDR_TOPSYS (0xCC >> 1) 21 #define I2C_ADDR_CHG (0xD2 >> 1) 22 #define I2C_ADDR_FG (0x6C >> 1) 23 #define I2C_ADDR_MUIC (0x4A >> 1) 24 25 /* Topsys, Haptic and LED registers */ 26 enum max77843_sys_reg { 27 MAX77843_SYS_REG_PMICID = 0x00, 28 MAX77843_SYS_REG_PMICREV = 0x01, 29 MAX77843_SYS_REG_MAINCTRL1 = 0x02, 30 MAX77843_SYS_REG_INTSRC = 0x22, 31 MAX77843_SYS_REG_INTSRCMASK = 0x23, 32 MAX77843_SYS_REG_SYSINTSRC = 0x24, 33 MAX77843_SYS_REG_SYSINTMASK = 0x26, 34 MAX77843_SYS_REG_TOPSYS_STAT = 0x28, 35 MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6, 36 37 MAX77843_SYS_REG_END, 38 }; 39 40 enum max77843_haptic_reg { 41 MAX77843_HAP_REG_MCONFIG = 0x10, 42 43 MAX77843_HAP_REG_END, 44 }; 45 46 enum max77843_led_reg { 47 MAX77843_LED_REG_LEDEN = 0x30, 48 MAX77843_LED_REG_LED0BRT = 0x31, 49 MAX77843_LED_REG_LED1BRT = 0x32, 50 MAX77843_LED_REG_LED2BRT = 0x33, 51 MAX77843_LED_REG_LED3BRT = 0x34, 52 MAX77843_LED_REG_LEDBLNK = 0x38, 53 MAX77843_LED_REG_LEDRAMP = 0x36, 54 55 MAX77843_LED_REG_END, 56 }; 57 58 /* Charger registers */ 59 enum max77843_charger_reg { 60 MAX77843_CHG_REG_CHG_INT = 0xB0, 61 MAX77843_CHG_REG_CHG_INT_MASK = 0xB1, 62 MAX77843_CHG_REG_CHG_INT_OK = 0xB2, 63 MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3, 64 MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4, 65 MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5, 66 MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7, 67 MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8, 68 MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9, 69 MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA, 70 MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB, 71 MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD, 72 MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE, 73 MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0, 74 MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1, 75 MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2, 76 MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3, 77 78 MAX77843_CHG_REG_END, 79 }; 80 81 /* Fuel gauge registers */ 82 enum max77843_fuelgauge { 83 MAX77843_FG_REG_STATUS = 0x00, 84 MAX77843_FG_REG_VALRT_TH = 0x01, 85 MAX77843_FG_REG_TALRT_TH = 0x02, 86 MAX77843_FG_REG_SALRT_TH = 0x03, 87 MAX77843_FG_RATE_AT_RATE = 0x04, 88 MAX77843_FG_REG_REMCAP_REP = 0x05, 89 MAX77843_FG_REG_SOCREP = 0x06, 90 MAX77843_FG_REG_AGE = 0x07, 91 MAX77843_FG_REG_TEMP = 0x08, 92 MAX77843_FG_REG_VCELL = 0x09, 93 MAX77843_FG_REG_CURRENT = 0x0A, 94 MAX77843_FG_REG_AVG_CURRENT = 0x0B, 95 MAX77843_FG_REG_SOCMIX = 0x0D, 96 MAX77843_FG_REG_SOCAV = 0x0E, 97 MAX77843_FG_REG_REMCAP_MIX = 0x0F, 98 MAX77843_FG_REG_FULLCAP = 0x10, 99 MAX77843_FG_REG_AVG_TEMP = 0x16, 100 MAX77843_FG_REG_CYCLES = 0x17, 101 MAX77843_FG_REG_AVG_VCELL = 0x19, 102 MAX77843_FG_REG_CONFIG = 0x1D, 103 MAX77843_FG_REG_REMCAP_AV = 0x1F, 104 MAX77843_FG_REG_FULLCAP_NOM = 0x23, 105 MAX77843_FG_REG_MISCCFG = 0x2B, 106 MAX77843_FG_REG_RCOMP = 0x38, 107 MAX77843_FG_REG_FSTAT = 0x3D, 108 MAX77843_FG_REG_DQACC = 0x45, 109 MAX77843_FG_REG_DPACC = 0x46, 110 MAX77843_FG_REG_OCV = 0xEE, 111 MAX77843_FG_REG_VFOCV = 0xFB, 112 MAX77843_FG_SOCVF = 0xFF, 113 114 MAX77843_FG_END, 115 }; 116 117 /* MUIC registers */ 118 enum max77843_muic_reg { 119 MAX77843_MUIC_REG_ID = 0x00, 120 MAX77843_MUIC_REG_INT1 = 0x01, 121 MAX77843_MUIC_REG_INT2 = 0x02, 122 MAX77843_MUIC_REG_INT3 = 0x03, 123 MAX77843_MUIC_REG_STATUS1 = 0x04, 124 MAX77843_MUIC_REG_STATUS2 = 0x05, 125 MAX77843_MUIC_REG_STATUS3 = 0x06, 126 MAX77843_MUIC_REG_INTMASK1 = 0x07, 127 MAX77843_MUIC_REG_INTMASK2 = 0x08, 128 MAX77843_MUIC_REG_INTMASK3 = 0x09, 129 MAX77843_MUIC_REG_CDETCTRL1 = 0x0A, 130 MAX77843_MUIC_REG_CDETCTRL2 = 0x0B, 131 MAX77843_MUIC_REG_CONTROL1 = 0x0C, 132 MAX77843_MUIC_REG_CONTROL2 = 0x0D, 133 MAX77843_MUIC_REG_CONTROL3 = 0x0E, 134 MAX77843_MUIC_REG_CONTROL4 = 0x16, 135 MAX77843_MUIC_REG_HVCONTROL1 = 0x17, 136 MAX77843_MUIC_REG_HVCONTROL2 = 0x18, 137 138 MAX77843_MUIC_REG_END, 139 }; 140 141 enum max77843_irq { 142 /* Topsys: SYSTEM */ 143 MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT, 144 MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT, 145 MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT, 146 MAX77843_SYS_IRQ_SYSINTSRC_TM_INT, 147 148 /* Charger: CHG_INT */ 149 MAX77843_CHG_IRQ_CHG_INT_BYP_I, 150 MAX77843_CHG_IRQ_CHG_INT_BATP_I, 151 MAX77843_CHG_IRQ_CHG_INT_BAT_I, 152 MAX77843_CHG_IRQ_CHG_INT_CHG_I, 153 MAX77843_CHG_IRQ_CHG_INT_WCIN_I, 154 MAX77843_CHG_IRQ_CHG_INT_CHGIN_I, 155 MAX77843_CHG_IRQ_CHG_INT_AICL_I, 156 157 MAX77843_IRQ_NUM, 158 }; 159 160 enum max77843_irq_muic { 161 /* MUIC: INT1 */ 162 MAX77843_MUIC_IRQ_INT1_ADC, 163 MAX77843_MUIC_IRQ_INT1_ADCERROR, 164 MAX77843_MUIC_IRQ_INT1_ADC1K, 165 166 /* MUIC: INT2 */ 167 MAX77843_MUIC_IRQ_INT2_CHGTYP, 168 MAX77843_MUIC_IRQ_INT2_CHGDETRUN, 169 MAX77843_MUIC_IRQ_INT2_DCDTMR, 170 MAX77843_MUIC_IRQ_INT2_DXOVP, 171 MAX77843_MUIC_IRQ_INT2_VBVOLT, 172 173 /* MUIC: INT3 */ 174 MAX77843_MUIC_IRQ_INT3_VBADC, 175 MAX77843_MUIC_IRQ_INT3_VDNMON, 176 MAX77843_MUIC_IRQ_INT3_DNRES, 177 MAX77843_MUIC_IRQ_INT3_MPNACK, 178 MAX77843_MUIC_IRQ_INT3_MRXBUFOW, 179 MAX77843_MUIC_IRQ_INT3_MRXTRF, 180 MAX77843_MUIC_IRQ_INT3_MRXPERR, 181 MAX77843_MUIC_IRQ_INT3_MRXRDY, 182 183 MAX77843_MUIC_IRQ_NUM, 184 }; 185 186 /* MAX77843 interrupts */ 187 #define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0) 188 #define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1) 189 #define MAX77843_SYS_IRQ_TSHDN_INT BIT(2) 190 #define MAX77843_SYS_IRQ_TM_INT BIT(3) 191 192 /* MAX77843 MAINCTRL1 register */ 193 #define MAINCTRL1_BIASEN_SHIFT 7 194 #define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT) 195 196 /* MAX77843 MCONFIG register */ 197 #define MCONFIG_MODE_SHIFT 7 198 #define MCONFIG_MEN_SHIFT 6 199 #define MCONFIG_PDIV_SHIFT 0 200 201 #define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT) 202 #define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT) 203 #define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT) 204 205 /* Max77843 charger insterrupts */ 206 #define MAX77843_CHG_BYP_I BIT(0) 207 #define MAX77843_CHG_BATP_I BIT(2) 208 #define MAX77843_CHG_BAT_I BIT(3) 209 #define MAX77843_CHG_CHG_I BIT(4) 210 #define MAX77843_CHG_WCIN_I BIT(5) 211 #define MAX77843_CHG_CHGIN_I BIT(6) 212 #define MAX77843_CHG_AICL_I BIT(7) 213 214 /* MAX77843 CHG_INT_OK register */ 215 #define MAX77843_CHG_BYP_OK BIT(0) 216 #define MAX77843_CHG_BATP_OK BIT(2) 217 #define MAX77843_CHG_BAT_OK BIT(3) 218 #define MAX77843_CHG_CHG_OK BIT(4) 219 #define MAX77843_CHG_WCIN_OK BIT(5) 220 #define MAX77843_CHG_CHGIN_OK BIT(6) 221 #define MAX77843_CHG_AICL_OK BIT(7) 222 223 /* MAX77843 CHG_DETAILS_00 register */ 224 #define MAX77843_CHG_BAT_DTLS BIT(0) 225 226 /* MAX77843 CHG_DETAILS_01 register */ 227 #define MAX77843_CHG_DTLS_MASK 0x0f 228 #define MAX77843_CHG_PQ_MODE 0x00 229 #define MAX77843_CHG_CC_MODE 0x01 230 #define MAX77843_CHG_CV_MODE 0x02 231 #define MAX77843_CHG_TO_MODE 0x03 232 #define MAX77843_CHG_DO_MODE 0x04 233 #define MAX77843_CHG_HT_MODE 0x05 234 #define MAX77843_CHG_TF_MODE 0x06 235 #define MAX77843_CHG_TS_MODE 0x07 236 #define MAX77843_CHG_OFF_MODE 0x08 237 238 #define MAX77843_CHG_BAT_DTLS_MASK 0xf0 239 #define MAX77843_CHG_NO_BAT (0x00 << 4) 240 #define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4) 241 #define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4) 242 #define MAX77843_CHG_OK_BAT (0x03 << 4) 243 #define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4) 244 #define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4) 245 #define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4) 246 247 /* MAX77843 CHG_CNFG_00 register */ 248 #define MAX77843_CHG_MODE_MASK 0x0f 249 #define MAX77843_CHG_DISABLE 0x00 250 #define MAX77843_CHG_ENABLE 0x05 251 #define MAX77843_CHG_MASK 0x01 252 #define MAX77843_CHG_OTG_MASK 0x02 253 #define MAX77843_CHG_BUCK_MASK 0x04 254 #define MAX77843_CHG_BOOST_MASK 0x08 255 256 /* MAX77843 CHG_CNFG_01 register */ 257 #define MAX77843_CHG_RESTART_THRESHOLD_100 0x00 258 #define MAX77843_CHG_RESTART_THRESHOLD_150 0x10 259 #define MAX77843_CHG_RESTART_THRESHOLD_200 0x20 260 #define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30 261 262 /* MAX77843 CHG_CNFG_02 register */ 263 #define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000 264 #define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000 265 #define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000 266 #define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f 267 #define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6) 268 #define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6) 269 #define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6) 270 #define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6) 271 #define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0 272 273 /* MAX77843 CHG_CNFG_03 register */ 274 #define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000 275 #define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000 276 #define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000 277 #define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07 278 279 /* MAX77843 CHG_CNFG_06 register */ 280 #define MAX77843_CHG_WRITE_CAP_BLOCK 0x10 281 #define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C 282 283 /* MAX77843_CHG_CNFG_09_register */ 284 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000 285 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000 286 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000 287 #define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000 288 289 #define MAX77843_MUIC_ADC BIT(0) 290 #define MAX77843_MUIC_ADCERROR BIT(2) 291 #define MAX77843_MUIC_ADC1K BIT(3) 292 293 #define MAX77843_MUIC_CHGTYP BIT(0) 294 #define MAX77843_MUIC_CHGDETRUN BIT(1) 295 #define MAX77843_MUIC_DCDTMR BIT(2) 296 #define MAX77843_MUIC_DXOVP BIT(3) 297 #define MAX77843_MUIC_VBVOLT BIT(4) 298 299 #define MAX77843_MUIC_VBADC BIT(0) 300 #define MAX77843_MUIC_VDNMON BIT(1) 301 #define MAX77843_MUIC_DNRES BIT(2) 302 #define MAX77843_MUIC_MPNACK BIT(3) 303 #define MAX77843_MUIC_MRXBUFOW BIT(4) 304 #define MAX77843_MUIC_MRXTRF BIT(5) 305 #define MAX77843_MUIC_MRXPERR BIT(6) 306 #define MAX77843_MUIC_MRXRDY BIT(7) 307 308 /* MAX77843 INTSRCMASK register */ 309 #define MAX77843_INTSRCMASK_CHGR 0 310 #define MAX77843_INTSRCMASK_SYS 1 311 #define MAX77843_INTSRCMASK_FG 2 312 #define MAX77843_INTSRCMASK_MUIC 3 313 314 #define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR) 315 #define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS) 316 #define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG) 317 #define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC) 318 319 #define MAX77843_INTSRC_MASK_MASK \ 320 (MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \ 321 MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK) 322 323 /* MAX77843 STATUS register*/ 324 #define MAX77843_MUIC_STATUS1_ADC_SHIFT 0 325 #define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6 326 #define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7 327 #define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0 328 #define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3 329 #define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4 330 #define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5 331 #define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6 332 #define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0 333 #define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4 334 #define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5 335 #define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6 336 337 #define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT) 338 #define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT) 339 #define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT) 340 #define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT) 341 #define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT) 342 #define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT) 343 #define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT) 344 #define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT) 345 #define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT) 346 #define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT) 347 #define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT) 348 #define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT) 349 350 /* MAX77843 CONTROL register */ 351 #define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0 352 #define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3 353 #define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT 6 354 #define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7 355 #define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0 356 #define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1 357 #define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2 358 #define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5 359 #define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6 360 #define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7 361 #define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0 362 #define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0 363 #define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4 364 #define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5 365 #define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6 366 367 #define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT) 368 #define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT) 369 #define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT) 370 #define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT) 371 #define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT) 372 #define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT) 373 #define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT) 374 #define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT) 375 #define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT) 376 #define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT) 377 #define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT) 378 #define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT) 379 #define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) 380 #define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT) 381 #define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT) 382 383 /* MAX77843 switch port */ 384 #define COM_OPEN 0 385 #define COM_USB 1 386 #define COM_AUDIO 2 387 #define COM_UART 3 388 #define COM_AUX_USB 4 389 #define COM_AUX_UART 5 390 391 #define MAX77843_MUIC_CONTROL1_COM_SW \ 392 ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \ 393 MAX77843_MUIC_CONTROL1_COMP2SW_MASK)) 394 395 #define MAX77843_MUIC_CONTROL1_SW_OPEN \ 396 ((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 397 COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 398 #define MAX77843_MUIC_CONTROL1_SW_USB \ 399 ((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 400 COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 401 #define MAX77843_MUIC_CONTROL1_SW_AUDIO \ 402 ((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 403 COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 404 #define MAX77843_MUIC_CONTROL1_SW_UART \ 405 ((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 406 COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 407 #define MAX77843_MUIC_CONTROL1_SW_AUX_USB \ 408 ((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 409 COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 410 #define MAX77843_MUIC_CONTROL1_SW_AUX_UART \ 411 ((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ 412 COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) 413 414 #define MAX77843_DISABLE 0 415 #define MAX77843_ENABLE 1 416 417 #define CONTROL4_AUTO_DISABLE \ 418 ((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ 419 (MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) 420 #define CONTROL4_AUTO_ENABLE \ 421 ((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ 422 (MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) 423 424 /* MAX77843 SAFEOUT LDO Control register */ 425 #define SAFEOUTCTRL_SAFEOUT1_SHIFT 0 426 #define SAFEOUTCTRL_SAFEOUT2_SHIFT 2 427 #define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6 428 #define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7 429 430 #define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \ 431 BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT) 432 #define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \ 433 BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT) 434 #define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \ 435 (0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT) 436 #define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \ 437 (0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT) 438 439 #endif /* __MAX77843_H__ */ 440