Searched refs:Mode (Results 1 – 14 of 14) sorted by relevance
/linux-4.19.296/include/uapi/linux/ |
D | cciss_defs.h | 61 BYTE Mode:2; /* b00 */ member 66 BYTE Mode:2; /* b01 */ member 72 BYTE Mode:2; /* b10 */ member 79 DWORD Mode:2; member 85 DWORD Mode:2; member
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/linux-4.19.296/drivers/media/tuners/ |
D | mt2063.c | 1183 enum mt2063_delivery_sys Mode) in MT2063_SetReceiverMode() argument 1191 if (Mode >= MT2063_NUM_RCVR_MODES) in MT2063_SetReceiverMode() 1198 reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode] in MT2063_SetReceiverMode() 1208 (LNARIN[Mode] & 0x03); in MT2063_SetReceiverMode() 1218 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); in MT2063_SetReceiverMode() 1242 (ACLNAMAX[Mode] & 0x1F); in MT2063_SetReceiverMode() 1250 (LNATGT[Mode] & 0x3F); in MT2063_SetReceiverMode() 1258 (ACRFMAX[Mode] & 0x1F); in MT2063_SetReceiverMode() 1266 (PD1TGT[Mode] & 0x3F); in MT2063_SetReceiverMode() 1273 u8 val = ACFIFMAX[Mode]; in MT2063_SetReceiverMode() [all …]
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D | mxl5005s.c | 243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ member 1672 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ in MXL5005_TunerConfig() argument 1696 state->Mode = Mode; in MXL5005_TunerConfig() 1723 if (state->Mode == 1) /* Digital Mode */ in MXL_SynthIFLO_Calc() 1737 if (state->Mode == 1) /* Digital Mode */ { in MXL_SynthRFTGLO_Calc() 1774 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); in MXL_BlockInit() 1777 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); in MXL_BlockInit() 1778 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); in MXL_BlockInit() 1779 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); in MXL_BlockInit() 1780 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); in MXL_BlockInit() [all …]
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/linux-4.19.296/drivers/pci/controller/dwc/ |
D | Kconfig | 23 bool "TI DRA7xx PCIe controller Host Mode" 39 bool "TI DRA7xx PCIe controller Endpoint Mode" 160 bool "Axis ARTPEC-6 PCIe controller Host Mode" 170 bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
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/linux-4.19.296/fs/cifs/ |
D | smb2inode.c | 138 dst->Mode = src->Mode; in move_smb2_info_to_cifs()
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D | smb2pdu.h | 748 __le32 Mode; member 1397 __le32 Mode; member
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D | cifspdu.h | 975 __le16 Mode; member 2327 __le32 Mode; member 2511 __le32 Mode; member
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D | smb2pdu.c | 568 cpu_to_le16(offsetof(struct create_posix, Mode)); in create_posix_buf() 591 buf->Mode = cpu_to_le32(mode); in create_posix_buf()
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D | cifssmb.c | 1247 pSMB->Mode = cpu_to_le16(access_flags_to_smbopen_mode(access_flags)); in SMBLegacyOpen() 1248 pSMB->Mode |= cpu_to_le16(0x40); /* deny none */ in SMBLegacyOpen()
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/linux-4.19.296/drivers/parisc/ |
D | Kconfig | 26 U2/Uturn chip in "Virtual Mode" and use the I/O MMU.
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/linux-4.19.296/drivers/pwm/ |
D | Kconfig | 307 tristate "OMAP Dual-Mode Timer PWM support" 310 Generic PWM framework driver for OMAP Dual-Mode Timer PWM output
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/linux-4.19.296/drivers/eisa/ |
D | eisa.ids | 856 ISA8C00 "3COM 3C505-2012 EtherLink Plus 16bit Mode" 862 ISA8C06 "3COM 3C505-2012 EtherLink Plus 8bit Mode" 863 ISA8C07 "3COM 3C605-2065 Tokenlink Plus 16bit Mode" 864 ISA8C08 "3COM 3C603 Tokenlink 8bit Mode"
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/linux-4.19.296/drivers/message/fusion/lsi/ |
D | mpi_history.txt | 403 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 689 * 02-28-07 01.05.03 Added new RAID Action, Device FW Update Mode, and
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/linux-4.19.296/crypto/ |
D | Kconfig | 277 Support for Galois/Counter Mode (GCM) and Galois Message 654 GHASH is message digest algorithm for GCM (Galois/Counter Mode). 1019 GHASH is message digest algorithm for GCM (Galois/Counter Mode).
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