1 /*
2 * omap_control_phy.h - Header file for the PHY part of control module.
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19 #ifndef __OMAP_CONTROL_PHY_H__
20 #define __OMAP_CONTROL_PHY_H__
21
22 enum omap_control_phy_type {
23 OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
24 OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
25 OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
26 OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */
27 OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
28 OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
29 };
30
31 struct omap_control_phy {
32 struct device *dev;
33
34 u32 __iomem *otghs_control;
35 u32 __iomem *power;
36 u32 __iomem *power_aux;
37 u32 __iomem *pcie_pcs;
38
39 struct clk *sys_clk;
40
41 enum omap_control_phy_type type;
42 };
43
44 enum omap_control_usb_mode {
45 USB_MODE_UNDEFINED = 0,
46 USB_MODE_HOST,
47 USB_MODE_DEVICE,
48 USB_MODE_DISCONNECT,
49 };
50
51 #define OMAP_CTRL_DEV_PHY_PD BIT(0)
52
53 #define OMAP_CTRL_DEV_AVALID BIT(0)
54 #define OMAP_CTRL_DEV_BVALID BIT(1)
55 #define OMAP_CTRL_DEV_VBUSVALID BIT(2)
56 #define OMAP_CTRL_DEV_SESSEND BIT(3)
57 #define OMAP_CTRL_DEV_IDDIG BIT(4)
58
59 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
60 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
61
62 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
63 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
64
65 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
66 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
67
68 #define OMAP_CTRL_PCIE_PCS_MASK 0xff
69 #define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16
70
71 #define OMAP_CTRL_USB2_PHY_PD BIT(28)
72
73 #define AM437X_CTRL_USB2_PHY_PD BIT(0)
74 #define AM437X_CTRL_USB2_OTG_PD BIT(1)
75 #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
76 #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
77
78 #if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
79 void omap_control_phy_power(struct device *dev, int on);
80 void omap_control_usb_set_mode(struct device *dev,
81 enum omap_control_usb_mode mode);
82 void omap_control_pcie_pcs(struct device *dev, u8 delay);
83 #else
84
omap_control_phy_power(struct device * dev,int on)85 static inline void omap_control_phy_power(struct device *dev, int on)
86 {
87 }
88
omap_control_usb_set_mode(struct device * dev,enum omap_control_usb_mode mode)89 static inline void omap_control_usb_set_mode(struct device *dev,
90 enum omap_control_usb_mode mode)
91 {
92 }
93
omap_control_pcie_pcs(struct device * dev,u8 delay)94 static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
95 {
96 }
97 #endif
98
99 #endif /* __OMAP_CONTROL_PHY_H__ */
100