1 /*
2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
3 * Steven J. Hill <sjhill@realitydiluted.com>
4 * Thomas Gleixner <tglx@linutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Info:
11 * Contains standard defines and IDs for NAND flash devices
12 *
13 * Changelog:
14 * See git changelog.
15 */
16 #ifndef __LINUX_MTD_RAWNAND_H
17 #define __LINUX_MTD_RAWNAND_H
18
19 #include <linux/wait.h>
20 #include <linux/spinlock.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24 #include <linux/of.h>
25 #include <linux/types.h>
26
27 struct nand_chip;
28 struct nand_flash_dev;
29
30 /* Scan and identify a NAND device */
31 int nand_scan_with_ids(struct nand_chip *chip, int max_chips,
32 struct nand_flash_dev *ids);
33
nand_scan(struct nand_chip * chip,int max_chips)34 static inline int nand_scan(struct nand_chip *chip, int max_chips)
35 {
36 return nand_scan_with_ids(chip, max_chips, NULL);
37 }
38
39 /* Internal helper for board drivers which need to override command function */
40 void nand_wait_ready(struct mtd_info *mtd);
41
42 /* The maximum number of NAND chips in an array */
43 #define NAND_MAX_CHIPS 8
44
45 /*
46 * Constants for hardware specific CLE/ALE/NCE function
47 *
48 * These are bits which can be or'ed to set/clear multiple
49 * bits in one go.
50 */
51 /* Select the chip by setting nCE to low */
52 #define NAND_NCE 0x01
53 /* Select the command latch by setting CLE to high */
54 #define NAND_CLE 0x02
55 /* Select the address latch by setting ALE to high */
56 #define NAND_ALE 0x04
57
58 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
59 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
60 #define NAND_CTRL_CHANGE 0x80
61
62 /*
63 * Standard NAND flash commands
64 */
65 #define NAND_CMD_READ0 0
66 #define NAND_CMD_READ1 1
67 #define NAND_CMD_RNDOUT 5
68 #define NAND_CMD_PAGEPROG 0x10
69 #define NAND_CMD_READOOB 0x50
70 #define NAND_CMD_ERASE1 0x60
71 #define NAND_CMD_STATUS 0x70
72 #define NAND_CMD_SEQIN 0x80
73 #define NAND_CMD_RNDIN 0x85
74 #define NAND_CMD_READID 0x90
75 #define NAND_CMD_ERASE2 0xd0
76 #define NAND_CMD_PARAM 0xec
77 #define NAND_CMD_GET_FEATURES 0xee
78 #define NAND_CMD_SET_FEATURES 0xef
79 #define NAND_CMD_RESET 0xff
80
81 /* Extended commands for large page devices */
82 #define NAND_CMD_READSTART 0x30
83 #define NAND_CMD_RNDOUTSTART 0xE0
84 #define NAND_CMD_CACHEDPROG 0x15
85
86 #define NAND_CMD_NONE -1
87
88 /* Status bits */
89 #define NAND_STATUS_FAIL 0x01
90 #define NAND_STATUS_FAIL_N1 0x02
91 #define NAND_STATUS_TRUE_READY 0x20
92 #define NAND_STATUS_READY 0x40
93 #define NAND_STATUS_WP 0x80
94
95 #define NAND_DATA_IFACE_CHECK_ONLY -1
96
97 /*
98 * Constants for ECC_MODES
99 */
100 typedef enum {
101 NAND_ECC_NONE,
102 NAND_ECC_SOFT,
103 NAND_ECC_HW,
104 NAND_ECC_HW_SYNDROME,
105 NAND_ECC_HW_OOB_FIRST,
106 NAND_ECC_ON_DIE,
107 } nand_ecc_modes_t;
108
109 enum nand_ecc_algo {
110 NAND_ECC_UNKNOWN,
111 NAND_ECC_HAMMING,
112 NAND_ECC_BCH,
113 NAND_ECC_RS,
114 };
115
116 /*
117 * Constants for Hardware ECC
118 */
119 /* Reset Hardware ECC for read */
120 #define NAND_ECC_READ 0
121 /* Reset Hardware ECC for write */
122 #define NAND_ECC_WRITE 1
123 /* Enable Hardware ECC before syndrome is read back from flash */
124 #define NAND_ECC_READSYN 2
125
126 /*
127 * Enable generic NAND 'page erased' check. This check is only done when
128 * ecc.correct() returns -EBADMSG.
129 * Set this flag if your implementation does not fix bitflips in erased
130 * pages and you want to rely on the default implementation.
131 */
132 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
133 #define NAND_ECC_MAXIMIZE BIT(1)
134
135 /* Bit mask for flags passed to do_nand_read_ecc */
136 #define NAND_GET_DEVICE 0x80
137
138
139 /*
140 * Option constants for bizarre disfunctionality and real
141 * features.
142 */
143 /* Buswidth is 16 bit */
144 #define NAND_BUSWIDTH_16 0x00000002
145 /* Chip has cache program function */
146 #define NAND_CACHEPRG 0x00000008
147 /*
148 * Chip requires ready check on read (for auto-incremented sequential read).
149 * True only for small page devices; large page devices do not support
150 * autoincrement.
151 */
152 #define NAND_NEED_READRDY 0x00000100
153
154 /* Chip does not allow subpage writes */
155 #define NAND_NO_SUBPAGE_WRITE 0x00000200
156
157 /* Device is one of 'new' xD cards that expose fake nand command set */
158 #define NAND_BROKEN_XD 0x00000400
159
160 /* Device behaves just like nand, but is readonly */
161 #define NAND_ROM 0x00000800
162
163 /* Device supports subpage reads */
164 #define NAND_SUBPAGE_READ 0x00001000
165
166 /*
167 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
168 * patterns.
169 */
170 #define NAND_NEED_SCRAMBLING 0x00002000
171
172 /* Device needs 3rd row address cycle */
173 #define NAND_ROW_ADDR_3 0x00004000
174
175 /* Options valid for Samsung large page devices */
176 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
177
178 /* Macros to identify the above */
179 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
180 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
181 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
182
183 /* Non chip related options */
184 /* This option skips the bbt scan during initialization. */
185 #define NAND_SKIP_BBTSCAN 0x00010000
186 /* Chip may not exist, so silence any errors in scan */
187 #define NAND_SCAN_SILENT_NODEV 0x00040000
188 /*
189 * Autodetect nand buswidth with readid/onfi.
190 * This suppose the driver will configure the hardware in 8 bits mode
191 * when calling nand_scan_ident, and update its configuration
192 * before calling nand_scan_tail.
193 */
194 #define NAND_BUSWIDTH_AUTO 0x00080000
195 /*
196 * This option could be defined by controller drivers to protect against
197 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
198 */
199 #define NAND_USE_BOUNCE_BUFFER 0x00100000
200
201 /*
202 * In case your controller is implementing ->cmd_ctrl() and is relying on the
203 * default ->cmdfunc() implementation, you may want to let the core handle the
204 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
205 * requested.
206 * If your controller already takes care of this delay, you don't need to set
207 * this flag.
208 */
209 #define NAND_WAIT_TCCS 0x00200000
210
211 /*
212 * Whether the NAND chip is a boot medium. Drivers might use this information
213 * to select ECC algorithms supported by the boot ROM or similar restrictions.
214 */
215 #define NAND_IS_BOOT_MEDIUM 0x00400000
216
217 /* Options set by nand scan */
218 /* Nand scan has allocated controller struct */
219 #define NAND_CONTROLLER_ALLOC 0x80000000
220
221 /* Cell info constants */
222 #define NAND_CI_CHIPNR_MSK 0x03
223 #define NAND_CI_CELLTYPE_MSK 0x0C
224 #define NAND_CI_CELLTYPE_SHIFT 2
225
226 /* Keep gcc happy */
227 struct nand_chip;
228
229 /* ONFI version bits */
230 #define ONFI_VERSION_1_0 BIT(1)
231 #define ONFI_VERSION_2_0 BIT(2)
232 #define ONFI_VERSION_2_1 BIT(3)
233 #define ONFI_VERSION_2_2 BIT(4)
234 #define ONFI_VERSION_2_3 BIT(5)
235 #define ONFI_VERSION_3_0 BIT(6)
236 #define ONFI_VERSION_3_1 BIT(7)
237 #define ONFI_VERSION_3_2 BIT(8)
238 #define ONFI_VERSION_4_0 BIT(9)
239
240 /* ONFI features */
241 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
242 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
243
244 /* ONFI timing mode, used in both asynchronous and synchronous mode */
245 #define ONFI_TIMING_MODE_0 (1 << 0)
246 #define ONFI_TIMING_MODE_1 (1 << 1)
247 #define ONFI_TIMING_MODE_2 (1 << 2)
248 #define ONFI_TIMING_MODE_3 (1 << 3)
249 #define ONFI_TIMING_MODE_4 (1 << 4)
250 #define ONFI_TIMING_MODE_5 (1 << 5)
251 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
252
253 /* ONFI feature number/address */
254 #define ONFI_FEATURE_NUMBER 256
255 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
256
257 /* Vendor-specific feature address (Micron) */
258 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
259 #define ONFI_FEATURE_ON_DIE_ECC 0x90
260 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
261
262 /* ONFI subfeature parameters length */
263 #define ONFI_SUBFEATURE_PARAM_LEN 4
264
265 /* ONFI optional commands SET/GET FEATURES supported? */
266 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
267
268 struct nand_onfi_params {
269 /* rev info and features block */
270 /* 'O' 'N' 'F' 'I' */
271 u8 sig[4];
272 __le16 revision;
273 __le16 features;
274 __le16 opt_cmd;
275 u8 reserved0[2];
276 __le16 ext_param_page_length; /* since ONFI 2.1 */
277 u8 num_of_param_pages; /* since ONFI 2.1 */
278 u8 reserved1[17];
279
280 /* manufacturer information block */
281 char manufacturer[12];
282 char model[20];
283 u8 jedec_id;
284 __le16 date_code;
285 u8 reserved2[13];
286
287 /* memory organization block */
288 __le32 byte_per_page;
289 __le16 spare_bytes_per_page;
290 __le32 data_bytes_per_ppage;
291 __le16 spare_bytes_per_ppage;
292 __le32 pages_per_block;
293 __le32 blocks_per_lun;
294 u8 lun_count;
295 u8 addr_cycles;
296 u8 bits_per_cell;
297 __le16 bb_per_lun;
298 __le16 block_endurance;
299 u8 guaranteed_good_blocks;
300 __le16 guaranteed_block_endurance;
301 u8 programs_per_page;
302 u8 ppage_attr;
303 u8 ecc_bits;
304 u8 interleaved_bits;
305 u8 interleaved_ops;
306 u8 reserved3[13];
307
308 /* electrical parameter block */
309 u8 io_pin_capacitance_max;
310 __le16 async_timing_mode;
311 __le16 program_cache_timing_mode;
312 __le16 t_prog;
313 __le16 t_bers;
314 __le16 t_r;
315 __le16 t_ccs;
316 __le16 src_sync_timing_mode;
317 u8 src_ssync_features;
318 __le16 clk_pin_capacitance_typ;
319 __le16 io_pin_capacitance_typ;
320 __le16 input_pin_capacitance_typ;
321 u8 input_pin_capacitance_max;
322 u8 driver_strength_support;
323 __le16 t_int_r;
324 __le16 t_adl;
325 u8 reserved4[8];
326
327 /* vendor */
328 __le16 vendor_revision;
329 u8 vendor[88];
330
331 __le16 crc;
332 } __packed;
333
334 #define ONFI_CRC_BASE 0x4F4E
335
336 /* Extended ECC information Block Definition (since ONFI 2.1) */
337 struct onfi_ext_ecc_info {
338 u8 ecc_bits;
339 u8 codeword_size;
340 __le16 bb_per_lun;
341 __le16 block_endurance;
342 u8 reserved[2];
343 } __packed;
344
345 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
346 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
347 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
348 struct onfi_ext_section {
349 u8 type;
350 u8 length;
351 } __packed;
352
353 #define ONFI_EXT_SECTION_MAX 8
354
355 /* Extended Parameter Page Definition (since ONFI 2.1) */
356 struct onfi_ext_param_page {
357 __le16 crc;
358 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
359 u8 reserved0[10];
360 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
361
362 /*
363 * The actual size of the Extended Parameter Page is in
364 * @ext_param_page_length of nand_onfi_params{}.
365 * The following are the variable length sections.
366 * So we do not add any fields below. Please see the ONFI spec.
367 */
368 } __packed;
369
370 struct jedec_ecc_info {
371 u8 ecc_bits;
372 u8 codeword_size;
373 __le16 bb_per_lun;
374 __le16 block_endurance;
375 u8 reserved[2];
376 } __packed;
377
378 /* JEDEC features */
379 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
380
381 struct nand_jedec_params {
382 /* rev info and features block */
383 /* 'J' 'E' 'S' 'D' */
384 u8 sig[4];
385 __le16 revision;
386 __le16 features;
387 u8 opt_cmd[3];
388 __le16 sec_cmd;
389 u8 num_of_param_pages;
390 u8 reserved0[18];
391
392 /* manufacturer information block */
393 char manufacturer[12];
394 char model[20];
395 u8 jedec_id[6];
396 u8 reserved1[10];
397
398 /* memory organization block */
399 __le32 byte_per_page;
400 __le16 spare_bytes_per_page;
401 u8 reserved2[6];
402 __le32 pages_per_block;
403 __le32 blocks_per_lun;
404 u8 lun_count;
405 u8 addr_cycles;
406 u8 bits_per_cell;
407 u8 programs_per_page;
408 u8 multi_plane_addr;
409 u8 multi_plane_op_attr;
410 u8 reserved3[38];
411
412 /* electrical parameter block */
413 __le16 async_sdr_speed_grade;
414 __le16 toggle_ddr_speed_grade;
415 __le16 sync_ddr_speed_grade;
416 u8 async_sdr_features;
417 u8 toggle_ddr_features;
418 u8 sync_ddr_features;
419 __le16 t_prog;
420 __le16 t_bers;
421 __le16 t_r;
422 __le16 t_r_multi_plane;
423 __le16 t_ccs;
424 __le16 io_pin_capacitance_typ;
425 __le16 input_pin_capacitance_typ;
426 __le16 clk_pin_capacitance_typ;
427 u8 driver_strength_support;
428 __le16 t_adl;
429 u8 reserved4[36];
430
431 /* ECC and endurance block */
432 u8 guaranteed_good_blocks;
433 __le16 guaranteed_block_endurance;
434 struct jedec_ecc_info ecc_info[4];
435 u8 reserved5[29];
436
437 /* reserved */
438 u8 reserved6[148];
439
440 /* vendor */
441 __le16 vendor_rev_num;
442 u8 reserved7[88];
443
444 /* CRC for Parameter Page */
445 __le16 crc;
446 } __packed;
447
448 /**
449 * struct onfi_params - ONFI specific parameters that will be reused
450 * @version: ONFI version (BCD encoded), 0 if ONFI is not supported
451 * @tPROG: Page program time
452 * @tBERS: Block erase time
453 * @tR: Page read time
454 * @tCCS: Change column setup time
455 * @async_timing_mode: Supported asynchronous timing mode
456 * @vendor_revision: Vendor specific revision number
457 * @vendor: Vendor specific data
458 */
459 struct onfi_params {
460 int version;
461 u16 tPROG;
462 u16 tBERS;
463 u16 tR;
464 u16 tCCS;
465 u16 async_timing_mode;
466 u16 vendor_revision;
467 u8 vendor[88];
468 };
469
470 /**
471 * struct nand_parameters - NAND generic parameters from the parameter page
472 * @model: Model name
473 * @supports_set_get_features: The NAND chip supports setting/getting features
474 * @set_feature_list: Bitmap of features that can be set
475 * @get_feature_list: Bitmap of features that can be get
476 * @onfi: ONFI specific parameters
477 */
478 struct nand_parameters {
479 /* Generic parameters */
480 const char *model;
481 bool supports_set_get_features;
482 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
483 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
484
485 /* ONFI parameters */
486 struct onfi_params *onfi;
487 };
488
489 /* The maximum expected count of bytes in the NAND ID sequence */
490 #define NAND_MAX_ID_LEN 8
491
492 /**
493 * struct nand_id - NAND id structure
494 * @data: buffer containing the id bytes.
495 * @len: ID length.
496 */
497 struct nand_id {
498 u8 data[NAND_MAX_ID_LEN];
499 int len;
500 };
501
502 /**
503 * struct nand_controller_ops - Controller operations
504 *
505 * @attach_chip: this method is called after the NAND detection phase after
506 * flash ID and MTD fields such as erase size, page size and OOB
507 * size have been set up. ECC requirements are available if
508 * provided by the NAND chip or device tree. Typically used to
509 * choose the appropriate ECC configuration and allocate
510 * associated resources.
511 * This hook is optional.
512 * @detach_chip: free all resources allocated/claimed in
513 * nand_controller_ops->attach_chip().
514 * This hook is optional.
515 */
516 struct nand_controller_ops {
517 int (*attach_chip)(struct nand_chip *chip);
518 void (*detach_chip)(struct nand_chip *chip);
519 };
520
521 /**
522 * struct nand_controller - Structure used to describe a NAND controller
523 *
524 * @lock: protection lock
525 * @active: the mtd device which holds the controller currently
526 * @wq: wait queue to sleep on if a NAND operation is in
527 * progress used instead of the per chip wait queue
528 * when a hw controller is available.
529 * @ops: NAND controller operations.
530 */
531 struct nand_controller {
532 spinlock_t lock;
533 struct nand_chip *active;
534 wait_queue_head_t wq;
535 const struct nand_controller_ops *ops;
536 };
537
nand_controller_init(struct nand_controller * nfc)538 static inline void nand_controller_init(struct nand_controller *nfc)
539 {
540 nfc->active = NULL;
541 spin_lock_init(&nfc->lock);
542 init_waitqueue_head(&nfc->wq);
543 }
544
545 /**
546 * struct nand_ecc_step_info - ECC step information of ECC engine
547 * @stepsize: data bytes per ECC step
548 * @strengths: array of supported strengths
549 * @nstrengths: number of supported strengths
550 */
551 struct nand_ecc_step_info {
552 int stepsize;
553 const int *strengths;
554 int nstrengths;
555 };
556
557 /**
558 * struct nand_ecc_caps - capability of ECC engine
559 * @stepinfos: array of ECC step information
560 * @nstepinfos: number of ECC step information
561 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
562 */
563 struct nand_ecc_caps {
564 const struct nand_ecc_step_info *stepinfos;
565 int nstepinfos;
566 int (*calc_ecc_bytes)(int step_size, int strength);
567 };
568
569 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
570 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
571 static const int __name##_strengths[] = { __VA_ARGS__ }; \
572 static const struct nand_ecc_step_info __name##_stepinfo = { \
573 .stepsize = __step, \
574 .strengths = __name##_strengths, \
575 .nstrengths = ARRAY_SIZE(__name##_strengths), \
576 }; \
577 static const struct nand_ecc_caps __name = { \
578 .stepinfos = &__name##_stepinfo, \
579 .nstepinfos = 1, \
580 .calc_ecc_bytes = __calc, \
581 }
582
583 /**
584 * struct nand_ecc_ctrl - Control structure for ECC
585 * @mode: ECC mode
586 * @algo: ECC algorithm
587 * @steps: number of ECC steps per page
588 * @size: data bytes per ECC step
589 * @bytes: ECC bytes per step
590 * @strength: max number of correctible bits per ECC step
591 * @total: total number of ECC bytes per page
592 * @prepad: padding information for syndrome based ECC generators
593 * @postpad: padding information for syndrome based ECC generators
594 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
595 * @priv: pointer to private ECC control data
596 * @calc_buf: buffer for calculated ECC, size is oobsize.
597 * @code_buf: buffer for ECC read from flash, size is oobsize.
598 * @hwctl: function to control hardware ECC generator. Must only
599 * be provided if an hardware ECC is available
600 * @calculate: function for ECC calculation or readback from ECC hardware
601 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
602 * Should return a positive number representing the number of
603 * corrected bitflips, -EBADMSG if the number of bitflips exceed
604 * ECC strength, or any other error code if the error is not
605 * directly related to correction.
606 * If -EBADMSG is returned the input buffers should be left
607 * untouched.
608 * @read_page_raw: function to read a raw page without ECC. This function
609 * should hide the specific layout used by the ECC
610 * controller and always return contiguous in-band and
611 * out-of-band data even if they're not stored
612 * contiguously on the NAND chip (e.g.
613 * NAND_ECC_HW_SYNDROME interleaves in-band and
614 * out-of-band data).
615 * @write_page_raw: function to write a raw page without ECC. This function
616 * should hide the specific layout used by the ECC
617 * controller and consider the passed data as contiguous
618 * in-band and out-of-band data. ECC controller is
619 * responsible for doing the appropriate transformations
620 * to adapt to its specific layout (e.g.
621 * NAND_ECC_HW_SYNDROME interleaves in-band and
622 * out-of-band data).
623 * @read_page: function to read a page according to the ECC generator
624 * requirements; returns maximum number of bitflips corrected in
625 * any single ECC step, -EIO hw error
626 * @read_subpage: function to read parts of the page covered by ECC;
627 * returns same as read_page()
628 * @write_subpage: function to write parts of the page covered by ECC.
629 * @write_page: function to write a page according to the ECC generator
630 * requirements.
631 * @write_oob_raw: function to write chip OOB data without ECC
632 * @read_oob_raw: function to read chip OOB data without ECC
633 * @read_oob: function to read chip OOB data
634 * @write_oob: function to write chip OOB data
635 */
636 struct nand_ecc_ctrl {
637 nand_ecc_modes_t mode;
638 enum nand_ecc_algo algo;
639 int steps;
640 int size;
641 int bytes;
642 int total;
643 int strength;
644 int prepad;
645 int postpad;
646 unsigned int options;
647 void *priv;
648 u8 *calc_buf;
649 u8 *code_buf;
650 void (*hwctl)(struct mtd_info *mtd, int mode);
651 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
652 uint8_t *ecc_code);
653 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
654 uint8_t *calc_ecc);
655 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
656 uint8_t *buf, int oob_required, int page);
657 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
658 const uint8_t *buf, int oob_required, int page);
659 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
660 uint8_t *buf, int oob_required, int page);
661 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
662 uint32_t offs, uint32_t len, uint8_t *buf, int page);
663 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
664 uint32_t offset, uint32_t data_len,
665 const uint8_t *data_buf, int oob_required, int page);
666 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
667 const uint8_t *buf, int oob_required, int page);
668 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
669 int page);
670 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
671 int page);
672 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
673 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
674 int page);
675 };
676
677 /**
678 * struct nand_sdr_timings - SDR NAND chip timings
679 *
680 * This struct defines the timing requirements of a SDR NAND chip.
681 * These information can be found in every NAND datasheets and the timings
682 * meaning are described in the ONFI specifications:
683 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
684 * Parameters)
685 *
686 * All these timings are expressed in picoseconds.
687 *
688 * @tBERS_max: Block erase time
689 * @tCCS_min: Change column setup time
690 * @tPROG_max: Page program time
691 * @tR_max: Page read time
692 * @tALH_min: ALE hold time
693 * @tADL_min: ALE to data loading time
694 * @tALS_min: ALE setup time
695 * @tAR_min: ALE to RE# delay
696 * @tCEA_max: CE# access time
697 * @tCEH_min: CE# high hold time
698 * @tCH_min: CE# hold time
699 * @tCHZ_max: CE# high to output hi-Z
700 * @tCLH_min: CLE hold time
701 * @tCLR_min: CLE to RE# delay
702 * @tCLS_min: CLE setup time
703 * @tCOH_min: CE# high to output hold
704 * @tCS_min: CE# setup time
705 * @tDH_min: Data hold time
706 * @tDS_min: Data setup time
707 * @tFEAT_max: Busy time for Set Features and Get Features
708 * @tIR_min: Output hi-Z to RE# low
709 * @tITC_max: Interface and Timing Mode Change time
710 * @tRC_min: RE# cycle time
711 * @tREA_max: RE# access time
712 * @tREH_min: RE# high hold time
713 * @tRHOH_min: RE# high to output hold
714 * @tRHW_min: RE# high to WE# low
715 * @tRHZ_max: RE# high to output hi-Z
716 * @tRLOH_min: RE# low to output hold
717 * @tRP_min: RE# pulse width
718 * @tRR_min: Ready to RE# low (data only)
719 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
720 * rising edge of R/B#.
721 * @tWB_max: WE# high to SR[6] low
722 * @tWC_min: WE# cycle time
723 * @tWH_min: WE# high hold time
724 * @tWHR_min: WE# high to RE# low
725 * @tWP_min: WE# pulse width
726 * @tWW_min: WP# transition to WE# low
727 */
728 struct nand_sdr_timings {
729 u64 tBERS_max;
730 u32 tCCS_min;
731 u64 tPROG_max;
732 u64 tR_max;
733 u32 tALH_min;
734 u32 tADL_min;
735 u32 tALS_min;
736 u32 tAR_min;
737 u32 tCEA_max;
738 u32 tCEH_min;
739 u32 tCH_min;
740 u32 tCHZ_max;
741 u32 tCLH_min;
742 u32 tCLR_min;
743 u32 tCLS_min;
744 u32 tCOH_min;
745 u32 tCS_min;
746 u32 tDH_min;
747 u32 tDS_min;
748 u32 tFEAT_max;
749 u32 tIR_min;
750 u32 tITC_max;
751 u32 tRC_min;
752 u32 tREA_max;
753 u32 tREH_min;
754 u32 tRHOH_min;
755 u32 tRHW_min;
756 u32 tRHZ_max;
757 u32 tRLOH_min;
758 u32 tRP_min;
759 u32 tRR_min;
760 u64 tRST_max;
761 u32 tWB_max;
762 u32 tWC_min;
763 u32 tWH_min;
764 u32 tWHR_min;
765 u32 tWP_min;
766 u32 tWW_min;
767 };
768
769 /**
770 * enum nand_data_interface_type - NAND interface timing type
771 * @NAND_SDR_IFACE: Single Data Rate interface
772 */
773 enum nand_data_interface_type {
774 NAND_SDR_IFACE,
775 };
776
777 /**
778 * struct nand_data_interface - NAND interface timing
779 * @type: type of the timing
780 * @timings: The timing, type according to @type
781 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
782 */
783 struct nand_data_interface {
784 enum nand_data_interface_type type;
785 union {
786 struct nand_sdr_timings sdr;
787 } timings;
788 };
789
790 /**
791 * nand_get_sdr_timings - get SDR timing from data interface
792 * @conf: The data interface
793 */
794 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)795 nand_get_sdr_timings(const struct nand_data_interface *conf)
796 {
797 if (conf->type != NAND_SDR_IFACE)
798 return ERR_PTR(-EINVAL);
799
800 return &conf->timings.sdr;
801 }
802
803 /**
804 * struct nand_manufacturer_ops - NAND Manufacturer operations
805 * @detect: detect the NAND memory organization and capabilities
806 * @init: initialize all vendor specific fields (like the ->read_retry()
807 * implementation) if any.
808 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
809 * is here to let vendor specific code release those resources.
810 * @fixup_onfi_param_page: apply vendor specific fixups to the ONFI parameter
811 * page. This is called after the checksum is verified.
812 */
813 struct nand_manufacturer_ops {
814 void (*detect)(struct nand_chip *chip);
815 int (*init)(struct nand_chip *chip);
816 void (*cleanup)(struct nand_chip *chip);
817 void (*fixup_onfi_param_page)(struct nand_chip *chip,
818 struct nand_onfi_params *p);
819 };
820
821 /**
822 * struct nand_op_cmd_instr - Definition of a command instruction
823 * @opcode: the command to issue in one cycle
824 */
825 struct nand_op_cmd_instr {
826 u8 opcode;
827 };
828
829 /**
830 * struct nand_op_addr_instr - Definition of an address instruction
831 * @naddrs: length of the @addrs array
832 * @addrs: array containing the address cycles to issue
833 */
834 struct nand_op_addr_instr {
835 unsigned int naddrs;
836 const u8 *addrs;
837 };
838
839 /**
840 * struct nand_op_data_instr - Definition of a data instruction
841 * @len: number of data bytes to move
842 * @buf: buffer to fill
843 * @buf.in: buffer to fill when reading from the NAND chip
844 * @buf.out: buffer to read from when writing to the NAND chip
845 * @force_8bit: force 8-bit access
846 *
847 * Please note that "in" and "out" are inverted from the ONFI specification
848 * and are from the controller perspective, so a "in" is a read from the NAND
849 * chip while a "out" is a write to the NAND chip.
850 */
851 struct nand_op_data_instr {
852 unsigned int len;
853 union {
854 void *in;
855 const void *out;
856 } buf;
857 bool force_8bit;
858 };
859
860 /**
861 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
862 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
863 */
864 struct nand_op_waitrdy_instr {
865 unsigned int timeout_ms;
866 };
867
868 /**
869 * enum nand_op_instr_type - Definition of all instruction types
870 * @NAND_OP_CMD_INSTR: command instruction
871 * @NAND_OP_ADDR_INSTR: address instruction
872 * @NAND_OP_DATA_IN_INSTR: data in instruction
873 * @NAND_OP_DATA_OUT_INSTR: data out instruction
874 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
875 */
876 enum nand_op_instr_type {
877 NAND_OP_CMD_INSTR,
878 NAND_OP_ADDR_INSTR,
879 NAND_OP_DATA_IN_INSTR,
880 NAND_OP_DATA_OUT_INSTR,
881 NAND_OP_WAITRDY_INSTR,
882 };
883
884 /**
885 * struct nand_op_instr - Instruction object
886 * @type: the instruction type
887 * @ctx: extra data associated to the instruction. You'll have to use the
888 * appropriate element depending on @type
889 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
890 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
891 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
892 * or %NAND_OP_DATA_OUT_INSTR
893 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
894 * @delay_ns: delay the controller should apply after the instruction has been
895 * issued on the bus. Most modern controllers have internal timings
896 * control logic, and in this case, the controller driver can ignore
897 * this field.
898 */
899 struct nand_op_instr {
900 enum nand_op_instr_type type;
901 union {
902 struct nand_op_cmd_instr cmd;
903 struct nand_op_addr_instr addr;
904 struct nand_op_data_instr data;
905 struct nand_op_waitrdy_instr waitrdy;
906 } ctx;
907 unsigned int delay_ns;
908 };
909
910 /*
911 * Special handling must be done for the WAITRDY timeout parameter as it usually
912 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
913 * tBERS (during an erase) which all of them are u64 values that cannot be
914 * divided by usual kernel macros and must be handled with the special
915 * DIV_ROUND_UP_ULL() macro.
916 *
917 * Cast to type of dividend is needed here to guarantee that the result won't
918 * be an unsigned long long when the dividend is an unsigned long (or smaller),
919 * which is what the compiler does when it sees ternary operator with 2
920 * different return types (picks the largest type to make sure there's no
921 * loss).
922 */
923 #define __DIVIDE(dividend, divisor) ({ \
924 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
925 DIV_ROUND_UP(dividend, divisor) : \
926 DIV_ROUND_UP_ULL(dividend, divisor)); \
927 })
928 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
929 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
930
931 #define NAND_OP_CMD(id, ns) \
932 { \
933 .type = NAND_OP_CMD_INSTR, \
934 .ctx.cmd.opcode = id, \
935 .delay_ns = ns, \
936 }
937
938 #define NAND_OP_ADDR(ncycles, cycles, ns) \
939 { \
940 .type = NAND_OP_ADDR_INSTR, \
941 .ctx.addr = { \
942 .naddrs = ncycles, \
943 .addrs = cycles, \
944 }, \
945 .delay_ns = ns, \
946 }
947
948 #define NAND_OP_DATA_IN(l, b, ns) \
949 { \
950 .type = NAND_OP_DATA_IN_INSTR, \
951 .ctx.data = { \
952 .len = l, \
953 .buf.in = b, \
954 .force_8bit = false, \
955 }, \
956 .delay_ns = ns, \
957 }
958
959 #define NAND_OP_DATA_OUT(l, b, ns) \
960 { \
961 .type = NAND_OP_DATA_OUT_INSTR, \
962 .ctx.data = { \
963 .len = l, \
964 .buf.out = b, \
965 .force_8bit = false, \
966 }, \
967 .delay_ns = ns, \
968 }
969
970 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
971 { \
972 .type = NAND_OP_DATA_IN_INSTR, \
973 .ctx.data = { \
974 .len = l, \
975 .buf.in = b, \
976 .force_8bit = true, \
977 }, \
978 .delay_ns = ns, \
979 }
980
981 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
982 { \
983 .type = NAND_OP_DATA_OUT_INSTR, \
984 .ctx.data = { \
985 .len = l, \
986 .buf.out = b, \
987 .force_8bit = true, \
988 }, \
989 .delay_ns = ns, \
990 }
991
992 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
993 { \
994 .type = NAND_OP_WAITRDY_INSTR, \
995 .ctx.waitrdy.timeout_ms = tout_ms, \
996 .delay_ns = ns, \
997 }
998
999 /**
1000 * struct nand_subop - a sub operation
1001 * @instrs: array of instructions
1002 * @ninstrs: length of the @instrs array
1003 * @first_instr_start_off: offset to start from for the first instruction
1004 * of the sub-operation
1005 * @last_instr_end_off: offset to end at (excluded) for the last instruction
1006 * of the sub-operation
1007 *
1008 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
1009 * address instructions.
1010 *
1011 * When an operation cannot be handled as is by the NAND controller, it will
1012 * be split by the parser into sub-operations which will be passed to the
1013 * controller driver.
1014 */
1015 struct nand_subop {
1016 const struct nand_op_instr *instrs;
1017 unsigned int ninstrs;
1018 unsigned int first_instr_start_off;
1019 unsigned int last_instr_end_off;
1020 };
1021
1022 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
1023 unsigned int op_id);
1024 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
1025 unsigned int op_id);
1026 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
1027 unsigned int op_id);
1028 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
1029 unsigned int op_id);
1030
1031 /**
1032 * struct nand_op_parser_addr_constraints - Constraints for address instructions
1033 * @maxcycles: maximum number of address cycles the controller can issue in a
1034 * single step
1035 */
1036 struct nand_op_parser_addr_constraints {
1037 unsigned int maxcycles;
1038 };
1039
1040 /**
1041 * struct nand_op_parser_data_constraints - Constraints for data instructions
1042 * @maxlen: maximum data length that the controller can handle in a single step
1043 */
1044 struct nand_op_parser_data_constraints {
1045 unsigned int maxlen;
1046 };
1047
1048 /**
1049 * struct nand_op_parser_pattern_elem - One element of a pattern
1050 * @type: the instructuction type
1051 * @optional: whether this element of the pattern is optional or mandatory
1052 * @ctx: address or data constraint
1053 * @ctx.addr: address constraint (number of cycles)
1054 * @ctx.data: data constraint (data length)
1055 */
1056 struct nand_op_parser_pattern_elem {
1057 enum nand_op_instr_type type;
1058 bool optional;
1059 union {
1060 struct nand_op_parser_addr_constraints addr;
1061 struct nand_op_parser_data_constraints data;
1062 } ctx;
1063 };
1064
1065 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
1066 { \
1067 .type = NAND_OP_CMD_INSTR, \
1068 .optional = _opt, \
1069 }
1070
1071 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
1072 { \
1073 .type = NAND_OP_ADDR_INSTR, \
1074 .optional = _opt, \
1075 .ctx.addr.maxcycles = _maxcycles, \
1076 }
1077
1078 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
1079 { \
1080 .type = NAND_OP_DATA_IN_INSTR, \
1081 .optional = _opt, \
1082 .ctx.data.maxlen = _maxlen, \
1083 }
1084
1085 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
1086 { \
1087 .type = NAND_OP_DATA_OUT_INSTR, \
1088 .optional = _opt, \
1089 .ctx.data.maxlen = _maxlen, \
1090 }
1091
1092 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
1093 { \
1094 .type = NAND_OP_WAITRDY_INSTR, \
1095 .optional = _opt, \
1096 }
1097
1098 /**
1099 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
1100 * @elems: array of pattern elements
1101 * @nelems: number of pattern elements in @elems array
1102 * @exec: the function that will issue a sub-operation
1103 *
1104 * A pattern is a list of elements, each element reprensenting one instruction
1105 * with its constraints. The pattern itself is used by the core to match NAND
1106 * chip operation with NAND controller operations.
1107 * Once a match between a NAND controller operation pattern and a NAND chip
1108 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
1109 * hook is called so that the controller driver can issue the operation on the
1110 * bus.
1111 *
1112 * Controller drivers should declare as many patterns as they support and pass
1113 * this list of patterns (created with the help of the following macro) to
1114 * the nand_op_parser_exec_op() helper.
1115 */
1116 struct nand_op_parser_pattern {
1117 const struct nand_op_parser_pattern_elem *elems;
1118 unsigned int nelems;
1119 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
1120 };
1121
1122 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
1123 { \
1124 .exec = _exec, \
1125 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
1126 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
1127 sizeof(struct nand_op_parser_pattern_elem), \
1128 }
1129
1130 /**
1131 * struct nand_op_parser - NAND controller operation parser descriptor
1132 * @patterns: array of supported patterns
1133 * @npatterns: length of the @patterns array
1134 *
1135 * The parser descriptor is just an array of supported patterns which will be
1136 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
1137 * NAND operation (or tries to determine if a specific operation is supported).
1138 *
1139 * It is worth mentioning that patterns will be tested in their declaration
1140 * order, and the first match will be taken, so it's important to order patterns
1141 * appropriately so that simple/inefficient patterns are placed at the end of
1142 * the list. Usually, this is where you put single instruction patterns.
1143 */
1144 struct nand_op_parser {
1145 const struct nand_op_parser_pattern *patterns;
1146 unsigned int npatterns;
1147 };
1148
1149 #define NAND_OP_PARSER(...) \
1150 { \
1151 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
1152 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
1153 sizeof(struct nand_op_parser_pattern), \
1154 }
1155
1156 /**
1157 * struct nand_operation - NAND operation descriptor
1158 * @instrs: array of instructions to execute
1159 * @ninstrs: length of the @instrs array
1160 *
1161 * The actual operation structure that will be passed to chip->exec_op().
1162 */
1163 struct nand_operation {
1164 const struct nand_op_instr *instrs;
1165 unsigned int ninstrs;
1166 };
1167
1168 #define NAND_OPERATION(_instrs) \
1169 { \
1170 .instrs = _instrs, \
1171 .ninstrs = ARRAY_SIZE(_instrs), \
1172 }
1173
1174 int nand_op_parser_exec_op(struct nand_chip *chip,
1175 const struct nand_op_parser *parser,
1176 const struct nand_operation *op, bool check_only);
1177
1178 /**
1179 * struct nand_chip - NAND Private Flash Chip Data
1180 * @mtd: MTD device registered to the MTD framework
1181 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
1182 * flash device
1183 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
1184 * flash device.
1185 * @read_byte: [REPLACEABLE] read one byte from the chip
1186 * @read_word: [REPLACEABLE] read one word from the chip
1187 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
1188 * low 8 I/O lines
1189 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
1190 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
1191 * @select_chip: [REPLACEABLE] select chip nr
1192 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
1193 * @block_markbad: [REPLACEABLE] mark a block bad
1194 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
1195 * ALE/CLE/nCE. Also used to write command and address
1196 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
1197 * device ready/busy line. If set to NULL no access to
1198 * ready/busy is available and the ready/busy information
1199 * is read from the chip status register.
1200 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
1201 * commands to the chip.
1202 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
1203 * ready.
1204 * @exec_op: controller specific method to execute NAND operations.
1205 * This method replaces ->cmdfunc(),
1206 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and
1207 * ->waifunc().
1208 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
1209 * setting the read-retry mode. Mostly needed for MLC NAND.
1210 * @ecc: [BOARDSPECIFIC] ECC control structure
1211 * @buf_align: minimum buffer alignment required by a platform
1212 * @dummy_controller: dummy controller implementation for drivers that can
1213 * only control a single chip
1214 * @erase: [REPLACEABLE] erase function
1215 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
1216 * data from array to read regs (tR).
1217 * @state: [INTERN] the current state of the NAND device
1218 * @oob_poi: "poison value buffer," used for laying out OOB data
1219 * before writing
1220 * @page_shift: [INTERN] number of address bits in a page (column
1221 * address bits).
1222 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
1223 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
1224 * @chip_shift: [INTERN] number of address bits in one chip
1225 * @options: [BOARDSPECIFIC] various chip options. They can partly
1226 * be set to inform nand_scan about special functionality.
1227 * See the defines for further explanation.
1228 * @bbt_options: [INTERN] bad block specific options. All options used
1229 * here must come from bbm.h. By default, these options
1230 * will be copied to the appropriate nand_bbt_descr's.
1231 * @badblockpos: [INTERN] position of the bad block marker in the oob
1232 * area.
1233 * @badblockbits: [INTERN] minimum number of set bits in a good block's
1234 * bad block marker position; i.e., BBM == 11110111b is
1235 * not bad when badblockbits == 7
1236 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
1237 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
1238 * Minimum amount of bit errors per @ecc_step_ds guaranteed
1239 * to be correctable. If unknown, set to zero.
1240 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
1241 * also from the datasheet. It is the recommended ECC step
1242 * size, if known; if unknown, set to zero.
1243 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1244 * set to the actually used ONFI mode if the chip is
1245 * ONFI compliant or deduced from the datasheet if
1246 * the NAND chip is not ONFI compliant.
1247 * @numchips: [INTERN] number of physical chips
1248 * @chipsize: [INTERN] the size of one chip for multichip arrays
1249 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
1250 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
1251 * @pagebuf: [INTERN] holds the pagenumber which is currently in
1252 * data_buf.
1253 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
1254 * currently in data_buf.
1255 * @subpagesize: [INTERN] holds the subpagesize
1256 * @id: [INTERN] holds NAND ID
1257 * @parameters: [INTERN] holds generic parameters under an easily
1258 * readable form.
1259 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
1260 * this nand device will encounter their life times.
1261 * @blocks_per_die: [INTERN] The number of PEBs in a die
1262 * @data_interface: [INTERN] NAND interface timing information
1263 * @read_retries: [INTERN] the number of read retry modes supported
1264 * @set_features: [REPLACEABLE] set the NAND chip features
1265 * @get_features: [REPLACEABLE] get the NAND chip features
1266 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
1267 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
1268 * means the configuration should not be applied but
1269 * only checked.
1270 * @bbt: [INTERN] bad block table pointer
1271 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
1272 * lookup.
1273 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
1274 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
1275 * bad block scan.
1276 * @controller: [REPLACEABLE] a pointer to a hardware controller
1277 * structure which is shared among multiple independent
1278 * devices.
1279 * @priv: [OPTIONAL] pointer to private chip data
1280 * @manufacturer: [INTERN] Contains manufacturer information
1281 * @manufacturer.desc: [INTERN] Contains manufacturer's description
1282 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1283 */
1284
1285 struct nand_chip {
1286 struct mtd_info mtd;
1287 void __iomem *IO_ADDR_R;
1288 void __iomem *IO_ADDR_W;
1289
1290 uint8_t (*read_byte)(struct mtd_info *mtd);
1291 u16 (*read_word)(struct mtd_info *mtd);
1292 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
1293 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1294 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1295 void (*select_chip)(struct mtd_info *mtd, int chip);
1296 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
1297 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
1298 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1299 int (*dev_ready)(struct mtd_info *mtd);
1300 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
1301 int page_addr);
1302 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
1303 int (*exec_op)(struct nand_chip *chip,
1304 const struct nand_operation *op,
1305 bool check_only);
1306 int (*erase)(struct mtd_info *mtd, int page);
1307 int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip,
1308 int feature_addr, uint8_t *subfeature_para);
1309 int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip,
1310 int feature_addr, uint8_t *subfeature_para);
1311 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
1312 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
1313 const struct nand_data_interface *conf);
1314
1315 int chip_delay;
1316 unsigned int options;
1317 unsigned int bbt_options;
1318
1319 int page_shift;
1320 int phys_erase_shift;
1321 int bbt_erase_shift;
1322 int chip_shift;
1323 int numchips;
1324 uint64_t chipsize;
1325 int pagemask;
1326 u8 *data_buf;
1327 int pagebuf;
1328 unsigned int pagebuf_bitflips;
1329 int subpagesize;
1330 uint8_t bits_per_cell;
1331 uint16_t ecc_strength_ds;
1332 uint16_t ecc_step_ds;
1333 int onfi_timing_mode_default;
1334 int badblockpos;
1335 int badblockbits;
1336
1337 struct nand_id id;
1338 struct nand_parameters parameters;
1339 u16 max_bb_per_die;
1340 u32 blocks_per_die;
1341
1342 struct nand_data_interface data_interface;
1343
1344 int read_retries;
1345
1346 flstate_t state;
1347
1348 uint8_t *oob_poi;
1349 struct nand_controller *controller;
1350
1351 struct nand_ecc_ctrl ecc;
1352 unsigned long buf_align;
1353 struct nand_controller dummy_controller;
1354
1355 uint8_t *bbt;
1356 struct nand_bbt_descr *bbt_td;
1357 struct nand_bbt_descr *bbt_md;
1358
1359 struct nand_bbt_descr *badblock_pattern;
1360
1361 void *priv;
1362
1363 struct {
1364 const struct nand_manufacturer *desc;
1365 void *priv;
1366 } manufacturer;
1367 };
1368
nand_exec_op(struct nand_chip * chip,const struct nand_operation * op)1369 static inline int nand_exec_op(struct nand_chip *chip,
1370 const struct nand_operation *op)
1371 {
1372 if (!chip->exec_op)
1373 return -ENOTSUPP;
1374
1375 return chip->exec_op(chip, op, false);
1376 }
1377
1378 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1379 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1380
nand_set_flash_node(struct nand_chip * chip,struct device_node * np)1381 static inline void nand_set_flash_node(struct nand_chip *chip,
1382 struct device_node *np)
1383 {
1384 mtd_set_of_node(&chip->mtd, np);
1385 }
1386
nand_get_flash_node(struct nand_chip * chip)1387 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1388 {
1389 return mtd_get_of_node(&chip->mtd);
1390 }
1391
mtd_to_nand(struct mtd_info * mtd)1392 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1393 {
1394 return container_of(mtd, struct nand_chip, mtd);
1395 }
1396
nand_to_mtd(struct nand_chip * chip)1397 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1398 {
1399 return &chip->mtd;
1400 }
1401
nand_get_controller_data(struct nand_chip * chip)1402 static inline void *nand_get_controller_data(struct nand_chip *chip)
1403 {
1404 return chip->priv;
1405 }
1406
nand_set_controller_data(struct nand_chip * chip,void * priv)1407 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1408 {
1409 chip->priv = priv;
1410 }
1411
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1412 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1413 void *priv)
1414 {
1415 chip->manufacturer.priv = priv;
1416 }
1417
nand_get_manufacturer_data(struct nand_chip * chip)1418 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1419 {
1420 return chip->manufacturer.priv;
1421 }
1422
1423 /*
1424 * NAND Flash Manufacturer ID Codes
1425 */
1426 #define NAND_MFR_TOSHIBA 0x98
1427 #define NAND_MFR_ESMT 0xc8
1428 #define NAND_MFR_SAMSUNG 0xec
1429 #define NAND_MFR_FUJITSU 0x04
1430 #define NAND_MFR_NATIONAL 0x8f
1431 #define NAND_MFR_RENESAS 0x07
1432 #define NAND_MFR_STMICRO 0x20
1433 #define NAND_MFR_HYNIX 0xad
1434 #define NAND_MFR_MICRON 0x2c
1435 #define NAND_MFR_AMD 0x01
1436 #define NAND_MFR_MACRONIX 0xc2
1437 #define NAND_MFR_EON 0x92
1438 #define NAND_MFR_SANDISK 0x45
1439 #define NAND_MFR_INTEL 0x89
1440 #define NAND_MFR_ATO 0x9b
1441 #define NAND_MFR_WINBOND 0xef
1442
1443
1444 /*
1445 * A helper for defining older NAND chips where the second ID byte fully
1446 * defined the chip, including the geometry (chip size, eraseblock size, page
1447 * size). All these chips have 512 bytes NAND page size.
1448 */
1449 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1450 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1451 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1452
1453 /*
1454 * A helper for defining newer chips which report their page size and
1455 * eraseblock size via the extended ID bytes.
1456 *
1457 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1458 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1459 * device ID now only represented a particular total chip size (and voltage,
1460 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1461 * using the same device ID.
1462 */
1463 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1464 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1465 .options = (opts) }
1466
1467 #define NAND_ECC_INFO(_strength, _step) \
1468 { .strength_ds = (_strength), .step_ds = (_step) }
1469 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1470 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1471
1472 /**
1473 * struct nand_flash_dev - NAND Flash Device ID Structure
1474 * @name: a human-readable name of the NAND chip
1475 * @dev_id: the device ID (the second byte of the full chip ID array)
1476 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1477 * memory address as @id[0])
1478 * @dev_id: device ID part of the full chip ID array (refers the same memory
1479 * address as @id[1])
1480 * @id: full device ID array
1481 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1482 * well as the eraseblock size) is determined from the extended NAND
1483 * chip ID array)
1484 * @chipsize: total chip size in MiB
1485 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1486 * @options: stores various chip bit options
1487 * @id_len: The valid length of the @id.
1488 * @oobsize: OOB size
1489 * @ecc: ECC correctability and step information from the datasheet.
1490 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1491 * @ecc_strength_ds in nand_chip{}.
1492 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1493 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1494 * For example, the "4bit ECC for each 512Byte" can be set with
1495 * NAND_ECC_INFO(4, 512).
1496 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1497 * reset. Should be deduced from timings described
1498 * in the datasheet.
1499 *
1500 */
1501 struct nand_flash_dev {
1502 char *name;
1503 union {
1504 struct {
1505 uint8_t mfr_id;
1506 uint8_t dev_id;
1507 };
1508 uint8_t id[NAND_MAX_ID_LEN];
1509 };
1510 unsigned int pagesize;
1511 unsigned int chipsize;
1512 unsigned int erasesize;
1513 unsigned int options;
1514 uint16_t id_len;
1515 uint16_t oobsize;
1516 struct {
1517 uint16_t strength_ds;
1518 uint16_t step_ds;
1519 } ecc;
1520 int onfi_timing_mode_default;
1521 };
1522
1523 /**
1524 * struct nand_manufacturer - NAND Flash Manufacturer structure
1525 * @name: Manufacturer name
1526 * @id: manufacturer ID code of device.
1527 * @ops: manufacturer operations
1528 */
1529 struct nand_manufacturer {
1530 int id;
1531 char *name;
1532 const struct nand_manufacturer_ops *ops;
1533 };
1534
1535 const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1536
1537 static inline const char *
nand_manufacturer_name(const struct nand_manufacturer * manufacturer)1538 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1539 {
1540 return manufacturer ? manufacturer->name : "Unknown";
1541 }
1542
1543 extern struct nand_flash_dev nand_flash_ids[];
1544
1545 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1546 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1547 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1548 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1549 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1550 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1551
1552 int nand_create_bbt(struct nand_chip *chip);
1553 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1554 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1555 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1556 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1557 int allowbbt);
1558
1559 /**
1560 * struct platform_nand_chip - chip level device structure
1561 * @nr_chips: max. number of chips to scan for
1562 * @chip_offset: chip number offset
1563 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1564 * @partitions: mtd partition list
1565 * @chip_delay: R/B delay value in us
1566 * @options: Option flags, e.g. 16bit buswidth
1567 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1568 * @part_probe_types: NULL-terminated array of probe types
1569 */
1570 struct platform_nand_chip {
1571 int nr_chips;
1572 int chip_offset;
1573 int nr_partitions;
1574 struct mtd_partition *partitions;
1575 int chip_delay;
1576 unsigned int options;
1577 unsigned int bbt_options;
1578 const char **part_probe_types;
1579 };
1580
1581 /* Keep gcc happy */
1582 struct platform_device;
1583
1584 /**
1585 * struct platform_nand_ctrl - controller level device structure
1586 * @probe: platform specific function to probe/setup hardware
1587 * @remove: platform specific function to remove/teardown hardware
1588 * @dev_ready: platform specific function to read ready/busy pin
1589 * @select_chip: platform specific chip select function
1590 * @cmd_ctrl: platform specific function for controlling
1591 * ALE/CLE/nCE. Also used to write command and address
1592 * @write_buf: platform specific function for write buffer
1593 * @read_buf: platform specific function for read buffer
1594 * @priv: private data to transport driver specific settings
1595 *
1596 * All fields are optional and depend on the hardware driver requirements
1597 */
1598 struct platform_nand_ctrl {
1599 int (*probe)(struct platform_device *pdev);
1600 void (*remove)(struct platform_device *pdev);
1601 int (*dev_ready)(struct mtd_info *mtd);
1602 void (*select_chip)(struct mtd_info *mtd, int chip);
1603 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1604 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1605 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1606 void *priv;
1607 };
1608
1609 /**
1610 * struct platform_nand_data - container structure for platform-specific data
1611 * @chip: chip level chip structure
1612 * @ctrl: controller level device structure
1613 */
1614 struct platform_nand_data {
1615 struct platform_nand_chip chip;
1616 struct platform_nand_ctrl ctrl;
1617 };
1618
1619 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1620 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1621 {
1622 if (!chip->parameters.onfi)
1623 return ONFI_TIMING_MODE_UNKNOWN;
1624
1625 return chip->parameters.onfi->async_timing_mode;
1626 }
1627
1628 int onfi_fill_data_interface(struct nand_chip *chip,
1629 enum nand_data_interface_type type,
1630 int timing_mode);
1631
1632 /*
1633 * Check if it is a SLC nand.
1634 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1635 * We do not distinguish the MLC and TLC now.
1636 */
nand_is_slc(struct nand_chip * chip)1637 static inline bool nand_is_slc(struct nand_chip *chip)
1638 {
1639 WARN(chip->bits_per_cell == 0,
1640 "chip->bits_per_cell is used uninitialized\n");
1641 return chip->bits_per_cell == 1;
1642 }
1643
1644 /**
1645 * Check if the opcode's address should be sent only on the lower 8 bits
1646 * @command: opcode to check
1647 */
nand_opcode_8bits(unsigned int command)1648 static inline int nand_opcode_8bits(unsigned int command)
1649 {
1650 switch (command) {
1651 case NAND_CMD_READID:
1652 case NAND_CMD_PARAM:
1653 case NAND_CMD_GET_FEATURES:
1654 case NAND_CMD_SET_FEATURES:
1655 return 1;
1656 default:
1657 break;
1658 }
1659 return 0;
1660 }
1661
1662 /* get timing characteristics from ONFI timing mode. */
1663 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1664
1665 int nand_check_erased_ecc_chunk(void *data, int datalen,
1666 void *ecc, int ecclen,
1667 void *extraoob, int extraooblen,
1668 int threshold);
1669
1670 int nand_ecc_choose_conf(struct nand_chip *chip,
1671 const struct nand_ecc_caps *caps, int oobavail);
1672
1673 /* Default write_oob implementation */
1674 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1675
1676 /* Default write_oob syndrome implementation */
1677 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1678 int page);
1679
1680 /* Default read_oob implementation */
1681 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1682
1683 /* Default read_oob syndrome implementation */
1684 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1685 int page);
1686
1687 /* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */
1688 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1689 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1690 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1691 int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1692 int addr, u8 *subfeature_param);
1693
1694 /* Default read_page_raw implementation */
1695 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1696 uint8_t *buf, int oob_required, int page);
1697 int nand_read_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1698 u8 *buf, int oob_required, int page);
1699
1700 /* Default write_page_raw implementation */
1701 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1702 const uint8_t *buf, int oob_required, int page);
1703 int nand_write_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1704 const u8 *buf, int oob_required, int page);
1705
1706 /* Reset and initialize a NAND device */
1707 int nand_reset(struct nand_chip *chip, int chipnr);
1708
1709 /* NAND operation helpers */
1710 int nand_reset_op(struct nand_chip *chip);
1711 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1712 unsigned int len);
1713 int nand_status_op(struct nand_chip *chip, u8 *status);
1714 int nand_exit_status_op(struct nand_chip *chip);
1715 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1716 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1717 unsigned int offset_in_page, void *buf, unsigned int len);
1718 int nand_change_read_column_op(struct nand_chip *chip,
1719 unsigned int offset_in_page, void *buf,
1720 unsigned int len, bool force_8bit);
1721 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1722 unsigned int offset_in_page, void *buf, unsigned int len);
1723 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1724 unsigned int offset_in_page, const void *buf,
1725 unsigned int len);
1726 int nand_prog_page_end_op(struct nand_chip *chip);
1727 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1728 unsigned int offset_in_page, const void *buf,
1729 unsigned int len);
1730 int nand_change_write_column_op(struct nand_chip *chip,
1731 unsigned int offset_in_page, const void *buf,
1732 unsigned int len, bool force_8bit);
1733 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1734 bool force_8bit);
1735 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1736 unsigned int len, bool force_8bit);
1737
1738 /*
1739 * Free resources held by the NAND device, must be called on error after a
1740 * sucessful nand_scan().
1741 */
1742 void nand_cleanup(struct nand_chip *chip);
1743 /* Unregister the MTD device and calls nand_cleanup() */
1744 void nand_release(struct nand_chip *chip);
1745
1746 /* Default extended ID decoding function */
1747 void nand_decode_ext_id(struct nand_chip *chip);
1748
1749 /*
1750 * External helper for controller drivers that have to implement the WAITRDY
1751 * instruction and have no physical pin to check it.
1752 */
1753 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1754
1755 #endif /* __LINUX_MTD_RAWNAND_H */
1756