1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
4  *
5  * For further information, please see http://wiki.openezx.org/PCAP2
6  */
7 
8 #ifndef EZX_PCAP_H
9 #define EZX_PCAP_H
10 
11 struct pcap_subdev {
12 	int id;
13 	const char *name;
14 	void *platform_data;
15 };
16 
17 struct pcap_platform_data {
18 	unsigned int irq_base;
19 	unsigned int config;
20 	int gpio;
21 	void (*init) (void *);	/* board specific init */
22 	int num_subdevs;
23 	struct pcap_subdev *subdevs;
24 };
25 
26 struct pcap_chip;
27 
28 int ezx_pcap_write(struct pcap_chip *, u8, u32);
29 int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
30 int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
31 int pcap_to_irq(struct pcap_chip *, int);
32 int irq_to_pcap(struct pcap_chip *, int);
33 int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
34 int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
35 void pcap_set_ts_bits(struct pcap_chip *, u32);
36 
37 #define PCAP_SECOND_PORT	1
38 #define PCAP_CS_AH		2
39 
40 #define PCAP_REGISTER_WRITE_OP_BIT	0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT	0x00000000
42 
43 #define PCAP_REGISTER_VALUE_MASK	0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK	0x7c000000
45 #define PCAP_REGISTER_ADDRESS_SHIFT	26
46 #define PCAP_REGISTER_NUMBER		32
47 #define PCAP_CLEAR_INTERRUPT_REGISTER	0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT		0x01ffffff
49 
50 /* registers accessible by both pcap ports */
51 #define PCAP_REG_ISR		0x0	/* Interrupt Status */
52 #define PCAP_REG_MSR		0x1	/* Interrupt Mask */
53 #define PCAP_REG_PSTAT		0x2	/* Processor Status */
54 #define PCAP_REG_VREG2		0x6	/* Regulator Bank 2 Control */
55 #define PCAP_REG_AUXVREG	0x7	/* Auxiliary Regulator Control */
56 #define PCAP_REG_BATT		0x8	/* Battery Control */
57 #define PCAP_REG_ADC		0x9	/* AD Control */
58 #define PCAP_REG_ADR		0xa	/* AD Result */
59 #define PCAP_REG_CODEC		0xb	/* Audio Codec Control */
60 #define PCAP_REG_RX_AMPS	0xc	/* RX Audio Amplifiers Control */
61 #define PCAP_REG_ST_DAC		0xd	/* Stereo DAC Control */
62 #define PCAP_REG_BUSCTRL	0x14	/* Connectivity Control */
63 #define PCAP_REG_PERIPH		0x15	/* Peripheral Control */
64 #define PCAP_REG_LOWPWR		0x18	/* Regulator Low Power Control */
65 #define PCAP_REG_TX_AMPS	0x1a	/* TX Audio Amplifiers Control */
66 #define PCAP_REG_GP		0x1b	/* General Purpose */
67 #define PCAP_REG_TEST1		0x1c
68 #define PCAP_REG_TEST2		0x1d
69 #define PCAP_REG_VENDOR_TEST1	0x1e
70 #define PCAP_REG_VENDOR_TEST2	0x1f
71 
72 /* registers accessible by pcap port 1 only (a1200, e2 & e6) */
73 #define PCAP_REG_INT_SEL	0x3	/* Interrupt Select */
74 #define PCAP_REG_SWCTRL		0x4	/* Switching Regulator Control */
75 #define PCAP_REG_VREG1		0x5	/* Regulator Bank 1 Control */
76 #define PCAP_REG_RTC_TOD	0xe	/* RTC Time of Day */
77 #define PCAP_REG_RTC_TODA	0xf	/* RTC Time of Day Alarm */
78 #define PCAP_REG_RTC_DAY	0x10	/* RTC Day */
79 #define PCAP_REG_RTC_DAYA	0x11	/* RTC Day Alarm */
80 #define PCAP_REG_MTRTMR		0x12	/* AD Monitor Timer */
81 #define PCAP_REG_PWR		0x13	/* Power Control */
82 #define PCAP_REG_AUXVREG_MASK	0x16	/* Auxiliary Regulator Mask */
83 #define PCAP_REG_VENDOR_REV	0x17
84 #define PCAP_REG_PERIPH_MASK	0x19	/* Peripheral Mask */
85 
86 /* PCAP2 Interrupts */
87 #define PCAP_NIRQS		23
88 #define PCAP_IRQ_ADCDONE	0	/* ADC done port 1 */
89 #define PCAP_IRQ_TS		1	/* Touch Screen */
90 #define PCAP_IRQ_1HZ		2	/* 1HZ timer */
91 #define PCAP_IRQ_WH		3	/* ADC above high limit */
92 #define PCAP_IRQ_WL		4	/* ADC below low limit */
93 #define PCAP_IRQ_TODA		5	/* Time of day alarm */
94 #define PCAP_IRQ_USB4V		6	/* USB above 4V */
95 #define PCAP_IRQ_ONOFF		7	/* On/Off button */
96 #define PCAP_IRQ_ONOFF2		8	/* On/Off button 2 */
97 #define PCAP_IRQ_USB1V		9	/* USB above 1V */
98 #define PCAP_IRQ_MOBPORT	10
99 #define PCAP_IRQ_MIC		11	/* Mic attach/HS button */
100 #define PCAP_IRQ_HS		12	/* Headset attach */
101 #define PCAP_IRQ_ST		13
102 #define PCAP_IRQ_PC		14	/* Power Cut */
103 #define PCAP_IRQ_WARM		15
104 #define PCAP_IRQ_EOL		16	/* Battery End Of Life */
105 #define PCAP_IRQ_CLK		17
106 #define PCAP_IRQ_SYSRST		18	/* System Reset */
107 #define PCAP_IRQ_DUMMY		19
108 #define PCAP_IRQ_ADCDONE2	20	/* ADC done port 2 */
109 #define PCAP_IRQ_SOFTRESET	21
110 #define PCAP_IRQ_MNEXB		22
111 
112 /* voltage regulators */
113 #define V1		0
114 #define V2		1
115 #define V3		2
116 #define V4		3
117 #define V5		4
118 #define V6		5
119 #define V7		6
120 #define V8		7
121 #define V9		8
122 #define V10		9
123 #define VAUX1		10
124 #define VAUX2		11
125 #define VAUX3		12
126 #define VAUX4		13
127 #define VSIM		14
128 #define VSIM2		15
129 #define VVIB		16
130 #define SW1		17
131 #define SW2		18
132 #define SW3		19
133 #define SW1S		20
134 #define SW2S		21
135 
136 #define PCAP_BATT_DAC_MASK		0x000000ff
137 #define PCAP_BATT_DAC_SHIFT		0
138 #define PCAP_BATT_B_FDBK		(1 << 8)
139 #define PCAP_BATT_EXT_ISENSE		(1 << 9)
140 #define PCAP_BATT_V_COIN_MASK		0x00003c00
141 #define PCAP_BATT_V_COIN_SHIFT		10
142 #define PCAP_BATT_I_COIN		(1 << 14)
143 #define PCAP_BATT_COIN_CH_EN		(1 << 15)
144 #define PCAP_BATT_EOL_SEL_MASK		0x000e0000
145 #define PCAP_BATT_EOL_SEL_SHIFT		17
146 #define PCAP_BATT_EOL_CMP_EN		(1 << 20)
147 #define PCAP_BATT_BATT_DET_EN		(1 << 21)
148 #define PCAP_BATT_THERMBIAS_CTRL	(1 << 22)
149 
150 #define PCAP_ADC_ADEN			(1 << 0)
151 #define PCAP_ADC_RAND			(1 << 1)
152 #define PCAP_ADC_AD_SEL1		(1 << 2)
153 #define PCAP_ADC_AD_SEL2		(1 << 3)
154 #define PCAP_ADC_ADA1_MASK		0x00000070
155 #define PCAP_ADC_ADA1_SHIFT		4
156 #define PCAP_ADC_ADA2_MASK		0x00000380
157 #define PCAP_ADC_ADA2_SHIFT		7
158 #define PCAP_ADC_ATO_MASK		0x00003c00
159 #define PCAP_ADC_ATO_SHIFT		10
160 #define PCAP_ADC_ATOX			(1 << 14)
161 #define PCAP_ADC_MTR1			(1 << 15)
162 #define PCAP_ADC_MTR2			(1 << 16)
163 #define PCAP_ADC_TS_M_MASK		0x000e0000
164 #define PCAP_ADC_TS_M_SHIFT		17
165 #define PCAP_ADC_TS_REF_LOWPWR		(1 << 20)
166 #define PCAP_ADC_TS_REFENB		(1 << 21)
167 #define PCAP_ADC_BATT_I_POLARITY	(1 << 22)
168 #define PCAP_ADC_BATT_I_ADC		(1 << 23)
169 
170 #define PCAP_ADC_BANK_0			0
171 #define PCAP_ADC_BANK_1			1
172 /* ADC bank 0 */
173 #define PCAP_ADC_CH_COIN		0
174 #define PCAP_ADC_CH_BATT		1
175 #define PCAP_ADC_CH_BPLUS		2
176 #define PCAP_ADC_CH_MOBPORTB		3
177 #define PCAP_ADC_CH_TEMPERATURE		4
178 #define PCAP_ADC_CH_CHARGER_ID		5
179 #define PCAP_ADC_CH_AD6			6
180 /* ADC bank 1 */
181 #define PCAP_ADC_CH_AD7			0
182 #define PCAP_ADC_CH_AD8			1
183 #define PCAP_ADC_CH_AD9			2
184 #define PCAP_ADC_CH_TS_X1		3
185 #define PCAP_ADC_CH_TS_X2		4
186 #define PCAP_ADC_CH_TS_Y1		5
187 #define PCAP_ADC_CH_TS_Y2		6
188 
189 #define PCAP_ADC_T_NOW			0
190 #define PCAP_ADC_T_IN_BURST		1
191 #define PCAP_ADC_T_OUT_BURST		2
192 
193 #define PCAP_ADC_ATO_IN_BURST		6
194 #define PCAP_ADC_ATO_OUT_BURST		0
195 
196 #define PCAP_ADC_TS_M_XY		1
197 #define PCAP_ADC_TS_M_PRESSURE		2
198 #define PCAP_ADC_TS_M_PLATE_X		3
199 #define PCAP_ADC_TS_M_PLATE_Y		4
200 #define PCAP_ADC_TS_M_STANDBY		5
201 #define PCAP_ADC_TS_M_NONTS		6
202 
203 #define PCAP_ADR_ADD1_MASK		0x000003ff
204 #define PCAP_ADR_ADD1_SHIFT		0
205 #define PCAP_ADR_ADD2_MASK		0x000ffc00
206 #define PCAP_ADR_ADD2_SHIFT		10
207 #define PCAP_ADR_ADINC1			(1 << 20)
208 #define PCAP_ADR_ADINC2			(1 << 21)
209 #define PCAP_ADR_ASC			(1 << 22)
210 #define PCAP_ADR_ONESHOT		(1 << 23)
211 
212 #define PCAP_BUSCTRL_FSENB		(1 << 0)
213 #define PCAP_BUSCTRL_USB_SUSPEND	(1 << 1)
214 #define PCAP_BUSCTRL_USB_PU		(1 << 2)
215 #define PCAP_BUSCTRL_USB_PD		(1 << 3)
216 #define PCAP_BUSCTRL_VUSB_EN		(1 << 4)
217 #define PCAP_BUSCTRL_USB_PS		(1 << 5)
218 #define PCAP_BUSCTRL_VUSB_MSTR_EN	(1 << 6)
219 #define PCAP_BUSCTRL_VBUS_PD_ENB	(1 << 7)
220 #define PCAP_BUSCTRL_CURRLIM		(1 << 8)
221 #define PCAP_BUSCTRL_RS232ENB		(1 << 9)
222 #define PCAP_BUSCTRL_RS232_DIR		(1 << 10)
223 #define PCAP_BUSCTRL_SE0_CONN		(1 << 11)
224 #define PCAP_BUSCTRL_USB_PDM		(1 << 12)
225 #define PCAP_BUSCTRL_BUS_PRI_ADJ	(1 << 24)
226 
227 /* leds */
228 #define PCAP_LED0		0
229 #define PCAP_LED1		1
230 #define PCAP_BL0		2
231 #define PCAP_BL1		3
232 #define PCAP_LED_3MA		0
233 #define PCAP_LED_4MA		1
234 #define PCAP_LED_5MA		2
235 #define PCAP_LED_9MA		3
236 #define PCAP_LED_T_MASK		0xf
237 #define PCAP_LED_C_MASK		0x3
238 #define PCAP_BL_MASK		0x1f
239 #define PCAP_BL0_SHIFT		0
240 #define PCAP_LED0_EN		(1 << 5)
241 #define PCAP_LED1_EN		(1 << 6)
242 #define PCAP_LED0_T_SHIFT	7
243 #define PCAP_LED1_T_SHIFT	11
244 #define PCAP_LED0_C_SHIFT	15
245 #define PCAP_LED1_C_SHIFT	17
246 #define PCAP_BL1_SHIFT		20
247 
248 /* RTC */
249 #define PCAP_RTC_DAY_MASK	0x3fff
250 #define PCAP_RTC_TOD_MASK	0xffff
251 #define PCAP_RTC_PC_MASK	0x7
252 #define SEC_PER_DAY		86400
253 
254 #endif
255