1 /*
2 * Intel E3-1200
3 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
4 *
5 * Support for the E3-1200 processor family. Heavily based on previous
6 * Intel EDAC drivers.
7 *
8 * Since the DRAM controller is on the cpu chip, we can use its PCI device
9 * id to identify these processors.
10 *
11 * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/)
12 *
13 * 0108: Xeon E3-1200 Processor Family DRAM Controller
14 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
15 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
16 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
17 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
18 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
19 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
20 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
21 * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
22 *
23 * Based on Intel specification:
24 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
25 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
26 * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
27 *
28 * According to the above datasheet (p.16):
29 * "
30 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
31 * requests that cross a DW boundary.
32 * "
33 *
34 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
35 * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
36 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
37 */
38
39 #include <linux/module.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/pci_ids.h>
43 #include <linux/edac.h>
44
45 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include "edac_module.h"
47
48 #define EDAC_MOD_STR "ie31200_edac"
49
50 #define ie31200_printk(level, fmt, arg...) \
51 edac_printk(level, "ie31200", fmt, ##arg)
52
53 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
54 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
55 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
56 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
57 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
58 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
59 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
62
63 #define IE31200_DIMMS 4
64 #define IE31200_RANKS 8
65 #define IE31200_RANKS_PER_CHANNEL 4
66 #define IE31200_DIMMS_PER_CHANNEL 2
67 #define IE31200_CHANNELS 2
68
69 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
70 #define IE31200_MCHBAR_LOW 0x48
71 #define IE31200_MCHBAR_HIGH 0x4c
72 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
73 #define IE31200_MMR_WINDOW_SIZE BIT(15)
74
75 /*
76 * Error Status Register (16b)
77 *
78 * 15 reserved
79 * 14 Isochronous TBWRR Run Behind FIFO Full
80 * (ITCV)
81 * 13 Isochronous TBWRR Run Behind FIFO Put
82 * (ITSTV)
83 * 12 reserved
84 * 11 MCH Thermal Sensor Event
85 * for SMI/SCI/SERR (GTSE)
86 * 10 reserved
87 * 9 LOCK to non-DRAM Memory Flag (LCKF)
88 * 8 reserved
89 * 7 DRAM Throttle Flag (DTF)
90 * 6:2 reserved
91 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
92 * 0 Single-bit DRAM ECC Error Flag (DSERR)
93 */
94 #define IE31200_ERRSTS 0xc8
95 #define IE31200_ERRSTS_UE BIT(1)
96 #define IE31200_ERRSTS_CE BIT(0)
97 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
98
99 /*
100 * Channel 0 ECC Error Log (64b)
101 *
102 * 63:48 Error Column Address (ERRCOL)
103 * 47:32 Error Row Address (ERRROW)
104 * 31:29 Error Bank Address (ERRBANK)
105 * 28:27 Error Rank Address (ERRRANK)
106 * 26:24 reserved
107 * 23:16 Error Syndrome (ERRSYND)
108 * 15: 2 reserved
109 * 1 Multiple Bit Error Status (MERRSTS)
110 * 0 Correctable Error Status (CERRSTS)
111 */
112
113 #define IE31200_C0ECCERRLOG 0x40c8
114 #define IE31200_C1ECCERRLOG 0x44c8
115 #define IE31200_C0ECCERRLOG_SKL 0x4048
116 #define IE31200_C1ECCERRLOG_SKL 0x4448
117 #define IE31200_ECCERRLOG_CE BIT(0)
118 #define IE31200_ECCERRLOG_UE BIT(1)
119 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
120 #define IE31200_ECCERRLOG_RANK_SHIFT 27
121 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
122 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
123
124 #define IE31200_ECCERRLOG_SYNDROME(log) \
125 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
126 IE31200_ECCERRLOG_SYNDROME_SHIFT)
127
128 #define IE31200_CAPID0 0xe4
129 #define IE31200_CAPID0_PDCD BIT(4)
130 #define IE31200_CAPID0_DDPCD BIT(6)
131 #define IE31200_CAPID0_ECC BIT(1)
132
133 #define IE31200_MAD_DIMM_0_OFFSET 0x5004
134 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
135 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
136 #define IE31200_MAD_DIMM_A_RANK BIT(17)
137 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
138 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
139 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
140 #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
141 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
142 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
143 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
144
145 /* Skylake reports 1GB increments, everything else is 256MB */
146 #define IE31200_PAGES(n, skl) \
147 (n << (28 + (2 * skl) - PAGE_SHIFT))
148
149 static int nr_channels;
150 static struct pci_dev *mci_pdev;
151 static int ie31200_registered = 1;
152
153 struct ie31200_priv {
154 void __iomem *window;
155 void __iomem *c0errlog;
156 void __iomem *c1errlog;
157 };
158
159 enum ie31200_chips {
160 IE31200 = 0,
161 };
162
163 struct ie31200_dev_info {
164 const char *ctl_name;
165 };
166
167 struct ie31200_error_info {
168 u16 errsts;
169 u16 errsts2;
170 u64 eccerrlog[IE31200_CHANNELS];
171 };
172
173 static const struct ie31200_dev_info ie31200_devs[] = {
174 [IE31200] = {
175 .ctl_name = "IE31200"
176 },
177 };
178
179 struct dimm_data {
180 u8 size; /* in multiples of 256MB, except Skylake is 1GB */
181 u8 dual_rank : 1,
182 x16_width : 2; /* 0 means x8 width */
183 };
184
how_many_channels(struct pci_dev * pdev)185 static int how_many_channels(struct pci_dev *pdev)
186 {
187 int n_channels;
188 unsigned char capid0_2b; /* 2nd byte of CAPID0 */
189
190 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
191
192 /* check PDCD: Dual Channel Disable */
193 if (capid0_2b & IE31200_CAPID0_PDCD) {
194 edac_dbg(0, "In single channel mode\n");
195 n_channels = 1;
196 } else {
197 edac_dbg(0, "In dual channel mode\n");
198 n_channels = 2;
199 }
200
201 /* check DDPCD - check if both channels are filled */
202 if (capid0_2b & IE31200_CAPID0_DDPCD)
203 edac_dbg(0, "2 DIMMS per channel disabled\n");
204 else
205 edac_dbg(0, "2 DIMMS per channel enabled\n");
206
207 return n_channels;
208 }
209
ecc_capable(struct pci_dev * pdev)210 static bool ecc_capable(struct pci_dev *pdev)
211 {
212 unsigned char capid0_4b; /* 4th byte of CAPID0 */
213
214 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
215 if (capid0_4b & IE31200_CAPID0_ECC)
216 return false;
217 return true;
218 }
219
eccerrlog_row(u64 log)220 static int eccerrlog_row(u64 log)
221 {
222 return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
223 IE31200_ECCERRLOG_RANK_SHIFT);
224 }
225
ie31200_clear_error_info(struct mem_ctl_info * mci)226 static void ie31200_clear_error_info(struct mem_ctl_info *mci)
227 {
228 /*
229 * Clear any error bits.
230 * (Yes, we really clear bits by writing 1 to them.)
231 */
232 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
233 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
234 }
235
ie31200_get_and_clear_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)236 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
237 struct ie31200_error_info *info)
238 {
239 struct pci_dev *pdev;
240 struct ie31200_priv *priv = mci->pvt_info;
241
242 pdev = to_pci_dev(mci->pdev);
243
244 /*
245 * This is a mess because there is no atomic way to read all the
246 * registers at once and the registers can transition from CE being
247 * overwritten by UE.
248 */
249 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
250 if (!(info->errsts & IE31200_ERRSTS_BITS))
251 return;
252
253 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
254 if (nr_channels == 2)
255 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
256
257 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
258
259 /*
260 * If the error is the same for both reads then the first set
261 * of reads is valid. If there is a change then there is a CE
262 * with no info and the second set of reads is valid and
263 * should be UE info.
264 */
265 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
266 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
267 if (nr_channels == 2)
268 info->eccerrlog[1] =
269 lo_hi_readq(priv->c1errlog);
270 }
271
272 ie31200_clear_error_info(mci);
273 }
274
ie31200_process_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)275 static void ie31200_process_error_info(struct mem_ctl_info *mci,
276 struct ie31200_error_info *info)
277 {
278 int channel;
279 u64 log;
280
281 if (!(info->errsts & IE31200_ERRSTS_BITS))
282 return;
283
284 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
285 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
286 -1, -1, -1, "UE overwrote CE", "");
287 info->errsts = info->errsts2;
288 }
289
290 for (channel = 0; channel < nr_channels; channel++) {
291 log = info->eccerrlog[channel];
292 if (log & IE31200_ECCERRLOG_UE) {
293 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
294 0, 0, 0,
295 eccerrlog_row(log),
296 channel, -1,
297 "ie31200 UE", "");
298 } else if (log & IE31200_ECCERRLOG_CE) {
299 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
300 0, 0,
301 IE31200_ECCERRLOG_SYNDROME(log),
302 eccerrlog_row(log),
303 channel, -1,
304 "ie31200 CE", "");
305 }
306 }
307 }
308
ie31200_check(struct mem_ctl_info * mci)309 static void ie31200_check(struct mem_ctl_info *mci)
310 {
311 struct ie31200_error_info info;
312
313 edac_dbg(1, "MC%d\n", mci->mc_idx);
314 ie31200_get_and_clear_error_info(mci, &info);
315 ie31200_process_error_info(mci, &info);
316 }
317
ie31200_map_mchbar(struct pci_dev * pdev)318 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
319 {
320 union {
321 u64 mchbar;
322 struct {
323 u32 mchbar_low;
324 u32 mchbar_high;
325 };
326 } u;
327 void __iomem *window;
328
329 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
330 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
331 u.mchbar &= IE31200_MCHBAR_MASK;
332
333 if (u.mchbar != (resource_size_t)u.mchbar) {
334 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
335 (unsigned long long)u.mchbar);
336 return NULL;
337 }
338
339 window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
340 if (!window)
341 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
342 (unsigned long long)u.mchbar);
343
344 return window;
345 }
346
__skl_populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)347 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
348 int chan)
349 {
350 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
351 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
352 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
353 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
354 }
355
__populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)356 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
357 int chan)
358 {
359 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
360 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
361 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
362 }
363
populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan,bool skl)364 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
365 bool skl)
366 {
367 if (skl)
368 __skl_populate_dimm_info(dd, addr_decode, chan);
369 else
370 __populate_dimm_info(dd, addr_decode, chan);
371 }
372
373
ie31200_probe1(struct pci_dev * pdev,int dev_idx)374 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
375 {
376 int i, j, ret;
377 struct mem_ctl_info *mci = NULL;
378 struct edac_mc_layer layers[2];
379 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
380 void __iomem *window;
381 struct ie31200_priv *priv;
382 u32 addr_decode, mad_offset;
383
384 /*
385 * Kaby Lake seems to work like Skylake. Please re-visit this logic
386 * when adding new CPU support.
387 */
388 bool skl = (pdev->device >= PCI_DEVICE_ID_INTEL_IE31200_HB_8);
389
390 edac_dbg(0, "MC:\n");
391
392 if (!ecc_capable(pdev)) {
393 ie31200_printk(KERN_INFO, "No ECC support\n");
394 return -ENODEV;
395 }
396
397 nr_channels = how_many_channels(pdev);
398 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
399 layers[0].size = IE31200_DIMMS;
400 layers[0].is_virt_csrow = true;
401 layers[1].type = EDAC_MC_LAYER_CHANNEL;
402 layers[1].size = nr_channels;
403 layers[1].is_virt_csrow = false;
404 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
405 sizeof(struct ie31200_priv));
406 if (!mci)
407 return -ENOMEM;
408
409 window = ie31200_map_mchbar(pdev);
410 if (!window) {
411 ret = -ENODEV;
412 goto fail_free;
413 }
414
415 edac_dbg(3, "MC: init mci\n");
416 mci->pdev = &pdev->dev;
417 if (skl)
418 mci->mtype_cap = MEM_FLAG_DDR4;
419 else
420 mci->mtype_cap = MEM_FLAG_DDR3;
421 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
422 mci->edac_cap = EDAC_FLAG_SECDED;
423 mci->mod_name = EDAC_MOD_STR;
424 mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
425 mci->dev_name = pci_name(pdev);
426 mci->edac_check = ie31200_check;
427 mci->ctl_page_to_phys = NULL;
428 priv = mci->pvt_info;
429 priv->window = window;
430 if (skl) {
431 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
432 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
433 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
434 } else {
435 priv->c0errlog = window + IE31200_C0ECCERRLOG;
436 priv->c1errlog = window + IE31200_C1ECCERRLOG;
437 mad_offset = IE31200_MAD_DIMM_0_OFFSET;
438 }
439
440 /* populate DIMM info */
441 for (i = 0; i < IE31200_CHANNELS; i++) {
442 addr_decode = readl(window + mad_offset +
443 (i * 4));
444 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
445 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
446 populate_dimm_info(&dimm_info[i][j], addr_decode, j,
447 skl);
448 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
449 dimm_info[i][j].size,
450 dimm_info[i][j].dual_rank,
451 dimm_info[i][j].x16_width);
452 }
453 }
454
455 /*
456 * The dram rank boundary (DRB) reg values are boundary addresses
457 * for each DRAM rank with a granularity of 64MB. DRB regs are
458 * cumulative; the last one will contain the total memory
459 * contained in all ranks.
460 */
461 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
462 for (j = 0; j < IE31200_CHANNELS; j++) {
463 struct dimm_info *dimm;
464 unsigned long nr_pages;
465
466 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
467 if (nr_pages == 0)
468 continue;
469
470 if (dimm_info[j][i].dual_rank) {
471 nr_pages = nr_pages / 2;
472 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
473 mci->n_layers, (i * 2) + 1,
474 j, 0);
475 dimm->nr_pages = nr_pages;
476 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
477 dimm->grain = 8; /* just a guess */
478 if (skl)
479 dimm->mtype = MEM_DDR4;
480 else
481 dimm->mtype = MEM_DDR3;
482 dimm->dtype = DEV_UNKNOWN;
483 dimm->edac_mode = EDAC_UNKNOWN;
484 }
485 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
486 mci->n_layers, i * 2, j, 0);
487 dimm->nr_pages = nr_pages;
488 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
489 dimm->grain = 8; /* same guess */
490 if (skl)
491 dimm->mtype = MEM_DDR4;
492 else
493 dimm->mtype = MEM_DDR3;
494 dimm->dtype = DEV_UNKNOWN;
495 dimm->edac_mode = EDAC_UNKNOWN;
496 }
497 }
498
499 ie31200_clear_error_info(mci);
500
501 if (edac_mc_add_mc(mci)) {
502 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
503 ret = -ENODEV;
504 goto fail_unmap;
505 }
506
507 /* get this far and it's successful */
508 edac_dbg(3, "MC: success\n");
509 return 0;
510
511 fail_unmap:
512 iounmap(window);
513
514 fail_free:
515 edac_mc_free(mci);
516
517 return ret;
518 }
519
ie31200_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)520 static int ie31200_init_one(struct pci_dev *pdev,
521 const struct pci_device_id *ent)
522 {
523 int rc;
524
525 edac_dbg(0, "MC:\n");
526 if (pci_enable_device(pdev) < 0)
527 return -EIO;
528 rc = ie31200_probe1(pdev, ent->driver_data);
529 if (rc == 0 && !mci_pdev)
530 mci_pdev = pci_dev_get(pdev);
531
532 return rc;
533 }
534
ie31200_remove_one(struct pci_dev * pdev)535 static void ie31200_remove_one(struct pci_dev *pdev)
536 {
537 struct mem_ctl_info *mci;
538 struct ie31200_priv *priv;
539
540 edac_dbg(0, "\n");
541 pci_dev_put(mci_pdev);
542 mci_pdev = NULL;
543 mci = edac_mc_del_mc(&pdev->dev);
544 if (!mci)
545 return;
546 priv = mci->pvt_info;
547 iounmap(priv->window);
548 edac_mc_free(mci);
549 }
550
551 static const struct pci_device_id ie31200_pci_tbl[] = {
552 {
553 PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
554 IE31200},
555 {
556 PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
557 IE31200},
558 {
559 PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
560 IE31200},
561 {
562 PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
563 IE31200},
564 {
565 PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
566 IE31200},
567 {
568 PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
569 IE31200},
570 {
571 PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
572 IE31200},
573 {
574 PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
575 IE31200},
576 {
577 PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
578 IE31200},
579 {
580 0,
581 } /* 0 terminated list. */
582 };
583 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
584
585 static struct pci_driver ie31200_driver = {
586 .name = EDAC_MOD_STR,
587 .probe = ie31200_init_one,
588 .remove = ie31200_remove_one,
589 .id_table = ie31200_pci_tbl,
590 };
591
ie31200_init(void)592 static int __init ie31200_init(void)
593 {
594 int pci_rc, i;
595
596 edac_dbg(3, "MC:\n");
597 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
598 opstate_init();
599
600 pci_rc = pci_register_driver(&ie31200_driver);
601 if (pci_rc < 0)
602 goto fail0;
603
604 if (!mci_pdev) {
605 ie31200_registered = 0;
606 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
607 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
608 ie31200_pci_tbl[i].device,
609 NULL);
610 if (mci_pdev)
611 break;
612 }
613 if (!mci_pdev) {
614 edac_dbg(0, "ie31200 pci_get_device fail\n");
615 pci_rc = -ENODEV;
616 goto fail1;
617 }
618 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
619 if (pci_rc < 0) {
620 edac_dbg(0, "ie31200 init fail\n");
621 pci_rc = -ENODEV;
622 goto fail1;
623 }
624 }
625 return 0;
626
627 fail1:
628 pci_unregister_driver(&ie31200_driver);
629 fail0:
630 pci_dev_put(mci_pdev);
631
632 return pci_rc;
633 }
634
ie31200_exit(void)635 static void __exit ie31200_exit(void)
636 {
637 edac_dbg(3, "MC:\n");
638 pci_unregister_driver(&ie31200_driver);
639 if (!ie31200_registered)
640 ie31200_remove_one(mci_pdev);
641 }
642
643 module_init(ie31200_init);
644 module_exit(ie31200_exit);
645
646 MODULE_LICENSE("GPL");
647 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
648 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
649