| /linux-4.19.296/include/dt-bindings/clock/ |
| D | s3c2412.h | 44 #define PCLK_WDT 32 macro
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| D | s3c2443.h | 82 #define PCLK_WDT 83 macro
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| D | samsung,s3c64xx-clock.h | 87 #define PCLK_WDT 69 macro
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| D | rk3036-cru.h | 86 #define PCLK_WDT 368 macro
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| D | exynos7-clk.h | 128 #define PCLK_WDT 3 macro
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| D | rk3188-cru-common.h | 92 #define PCLK_WDT 331 macro
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| D | rk3128-cru.h | 101 #define PCLK_WDT 319 macro
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| D | rv1108-cru.h | 144 #define PCLK_WDT 284 macro
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| D | rk3288-cru.h | 169 #define PCLK_WDT 368 macro
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| D | rk3368-cru.h | 158 #define PCLK_WDT 368 macro
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| D | rk3399-cru.h | 284 #define PCLK_WDT 380 macro
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| /linux-4.19.296/drivers/clk/samsung/ |
| D | clk-s3c2443.c | 173 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
204 ALIAS(PCLK_WDT, NULL, "watchdog"),
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| D | clk-s3c64xx.c | 301 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
406 ALIAS(PCLK_WDT, NULL, "watchdog"),
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| D | clk-s3c2412.c | 147 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
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| D | clk-exynos7.c | 848 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
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| /linux-4.19.296/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 422 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| D | clk-rk3128.c | 519 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| D | clk-rv1108.c | 640 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
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| D | clk-rk3188.c | 526 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| D | clk-rk3368.c | 894 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); in rk3368_clk_init()
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| D | clk-rk3288.c | 926 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); in rk3288_clk_init()
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| D | clk-rk3399.c | 1554 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); in rk3399_clk_init()
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