Searched refs:PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (Results 1 – 2 of 2) sorted by relevance
219 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) macro2906 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; in tegra210_init_pllu()
231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) macro