1 /*
2 * DaVinci Power Management and Real Time Clock Driver for TI platforms
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc
5 *
6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/spinlock.h>
28 #include <linux/rtc.h>
29 #include <linux/bcd.h>
30 #include <linux/platform_device.h>
31 #include <linux/io.h>
32 #include <linux/slab.h>
33
34 /*
35 * The DaVinci RTC is a simple RTC with the following
36 * Sec: 0 - 59 : BCD count
37 * Min: 0 - 59 : BCD count
38 * Hour: 0 - 23 : BCD count
39 * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
40 */
41
42 /* PRTC interface registers */
43 #define DAVINCI_PRTCIF_PID 0x00
44 #define PRTCIF_CTLR 0x04
45 #define PRTCIF_LDATA 0x08
46 #define PRTCIF_UDATA 0x0C
47 #define PRTCIF_INTEN 0x10
48 #define PRTCIF_INTFLG 0x14
49
50 /* PRTCIF_CTLR bit fields */
51 #define PRTCIF_CTLR_BUSY BIT(31)
52 #define PRTCIF_CTLR_SIZE BIT(25)
53 #define PRTCIF_CTLR_DIR BIT(24)
54 #define PRTCIF_CTLR_BENU_MSB BIT(23)
55 #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
56 #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
57 #define PRTCIF_CTLR_BENU_LSB BIT(20)
58 #define PRTCIF_CTLR_BENU_MASK (0x00F00000)
59 #define PRTCIF_CTLR_BENL_MSB BIT(19)
60 #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
61 #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
62 #define PRTCIF_CTLR_BENL_LSB BIT(16)
63 #define PRTCIF_CTLR_BENL_MASK (0x000F0000)
64
65 /* PRTCIF_INTEN bit fields */
66 #define PRTCIF_INTEN_RTCSS BIT(1)
67 #define PRTCIF_INTEN_RTCIF BIT(0)
68 #define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
69 | PRTCIF_INTEN_RTCIF)
70
71 /* PRTCIF_INTFLG bit fields */
72 #define PRTCIF_INTFLG_RTCSS BIT(1)
73 #define PRTCIF_INTFLG_RTCIF BIT(0)
74 #define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
75 | PRTCIF_INTFLG_RTCIF)
76
77 /* PRTC subsystem registers */
78 #define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
79 #define PRTCSS_RTC_CTRL (0x10)
80 #define PRTCSS_RTC_WDT (0x11)
81 #define PRTCSS_RTC_TMR0 (0x12)
82 #define PRTCSS_RTC_TMR1 (0x13)
83 #define PRTCSS_RTC_CCTRL (0x14)
84 #define PRTCSS_RTC_SEC (0x15)
85 #define PRTCSS_RTC_MIN (0x16)
86 #define PRTCSS_RTC_HOUR (0x17)
87 #define PRTCSS_RTC_DAY0 (0x18)
88 #define PRTCSS_RTC_DAY1 (0x19)
89 #define PRTCSS_RTC_AMIN (0x1A)
90 #define PRTCSS_RTC_AHOUR (0x1B)
91 #define PRTCSS_RTC_ADAY0 (0x1C)
92 #define PRTCSS_RTC_ADAY1 (0x1D)
93 #define PRTCSS_RTC_CLKC_CNT (0x20)
94
95 /* PRTCSS_RTC_INTC_EXTENA1 */
96 #define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
97
98 /* PRTCSS_RTC_CTRL bit fields */
99 #define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
100 #define PRTCSS_RTC_CTRL_WEN BIT(6)
101 #define PRTCSS_RTC_CTRL_WDRT BIT(5)
102 #define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
103 #define PRTCSS_RTC_CTRL_TE BIT(3)
104 #define PRTCSS_RTC_CTRL_TIEN BIT(2)
105 #define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
106 #define PRTCSS_RTC_CTRL_TMMD BIT(0)
107
108 /* PRTCSS_RTC_CCTRL bit fields */
109 #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
110 #define PRTCSS_RTC_CCTRL_DAEN BIT(5)
111 #define PRTCSS_RTC_CCTRL_HAEN BIT(4)
112 #define PRTCSS_RTC_CCTRL_MAEN BIT(3)
113 #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
114 #define PRTCSS_RTC_CCTRL_AIEN BIT(1)
115 #define PRTCSS_RTC_CCTRL_CAEN BIT(0)
116
117 static DEFINE_SPINLOCK(davinci_rtc_lock);
118
119 struct davinci_rtc {
120 struct rtc_device *rtc;
121 void __iomem *base;
122 int irq;
123 };
124
rtcif_write(struct davinci_rtc * davinci_rtc,u32 val,u32 addr)125 static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
126 u32 val, u32 addr)
127 {
128 writel(val, davinci_rtc->base + addr);
129 }
130
rtcif_read(struct davinci_rtc * davinci_rtc,u32 addr)131 static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
132 {
133 return readl(davinci_rtc->base + addr);
134 }
135
rtcif_wait(struct davinci_rtc * davinci_rtc)136 static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
137 {
138 while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
139 cpu_relax();
140 }
141
rtcss_write(struct davinci_rtc * davinci_rtc,unsigned long val,u8 addr)142 static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
143 unsigned long val, u8 addr)
144 {
145 rtcif_wait(davinci_rtc);
146
147 rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
148 rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
149
150 rtcif_wait(davinci_rtc);
151 }
152
rtcss_read(struct davinci_rtc * davinci_rtc,u8 addr)153 static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
154 {
155 rtcif_wait(davinci_rtc);
156
157 rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
158 PRTCIF_CTLR);
159
160 rtcif_wait(davinci_rtc);
161
162 return rtcif_read(davinci_rtc, PRTCIF_LDATA);
163 }
164
davinci_rtcss_calendar_wait(struct davinci_rtc * davinci_rtc)165 static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
166 {
167 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
168 PRTCSS_RTC_CCTRL_CALBUSY)
169 cpu_relax();
170 }
171
davinci_rtc_interrupt(int irq,void * class_dev)172 static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
173 {
174 struct davinci_rtc *davinci_rtc = class_dev;
175 unsigned long events = 0;
176 u32 irq_flg;
177 u8 alm_irq, tmr_irq;
178 u8 rtc_ctrl, rtc_cctrl;
179 int ret = IRQ_NONE;
180
181 irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
182 PRTCIF_INTFLG_RTCSS;
183
184 alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
185 PRTCSS_RTC_CCTRL_ALMFLG;
186
187 tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
188 PRTCSS_RTC_CTRL_TMRFLG;
189
190 if (irq_flg) {
191 if (alm_irq) {
192 events |= RTC_IRQF | RTC_AF;
193 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
194 rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
195 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
196 } else if (tmr_irq) {
197 events |= RTC_IRQF | RTC_PF;
198 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
199 rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
200 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
201 }
202
203 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
204 PRTCIF_INTFLG);
205 rtc_update_irq(davinci_rtc->rtc, 1, events);
206
207 ret = IRQ_HANDLED;
208 }
209
210 return ret;
211 }
212
213 static int
davinci_rtc_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)214 davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
215 {
216 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
217 u8 rtc_ctrl;
218 unsigned long flags;
219 int ret = 0;
220
221 spin_lock_irqsave(&davinci_rtc_lock, flags);
222
223 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
224
225 switch (cmd) {
226 case RTC_WIE_ON:
227 rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
228 break;
229 case RTC_WIE_OFF:
230 rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
231 break;
232 default:
233 ret = -ENOIOCTLCMD;
234 }
235
236 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
237
238 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
239
240 return ret;
241 }
242
convertfromdays(u16 days,struct rtc_time * tm)243 static int convertfromdays(u16 days, struct rtc_time *tm)
244 {
245 int tmp_days, year, mon;
246
247 for (year = 2000;; year++) {
248 tmp_days = rtc_year_days(1, 12, year);
249 if (days >= tmp_days)
250 days -= tmp_days;
251 else {
252 for (mon = 0;; mon++) {
253 tmp_days = rtc_month_days(mon, year);
254 if (days >= tmp_days) {
255 days -= tmp_days;
256 } else {
257 tm->tm_year = year - 1900;
258 tm->tm_mon = mon;
259 tm->tm_mday = days + 1;
260 break;
261 }
262 }
263 break;
264 }
265 }
266 return 0;
267 }
268
convert2days(u16 * days,struct rtc_time * tm)269 static int convert2days(u16 *days, struct rtc_time *tm)
270 {
271 int i;
272 *days = 0;
273
274 /* epoch == 1900 */
275 if (tm->tm_year < 100 || tm->tm_year > 199)
276 return -EINVAL;
277
278 for (i = 2000; i < 1900 + tm->tm_year; i++)
279 *days += rtc_year_days(1, 12, i);
280
281 *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
282
283 return 0;
284 }
285
davinci_rtc_read_time(struct device * dev,struct rtc_time * tm)286 static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
287 {
288 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
289 u16 days = 0;
290 u8 day0, day1;
291 unsigned long flags;
292
293 spin_lock_irqsave(&davinci_rtc_lock, flags);
294
295 davinci_rtcss_calendar_wait(davinci_rtc);
296 tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
297
298 davinci_rtcss_calendar_wait(davinci_rtc);
299 tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
300
301 davinci_rtcss_calendar_wait(davinci_rtc);
302 tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
303
304 davinci_rtcss_calendar_wait(davinci_rtc);
305 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
306
307 davinci_rtcss_calendar_wait(davinci_rtc);
308 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
309
310 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
311
312 days |= day1;
313 days <<= 8;
314 days |= day0;
315
316 if (convertfromdays(days, tm) < 0)
317 return -EINVAL;
318
319 return 0;
320 }
321
davinci_rtc_set_time(struct device * dev,struct rtc_time * tm)322 static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
323 {
324 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
325 u16 days;
326 u8 rtc_cctrl;
327 unsigned long flags;
328
329 if (convert2days(&days, tm) < 0)
330 return -EINVAL;
331
332 spin_lock_irqsave(&davinci_rtc_lock, flags);
333
334 davinci_rtcss_calendar_wait(davinci_rtc);
335 rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
336
337 davinci_rtcss_calendar_wait(davinci_rtc);
338 rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
339
340 davinci_rtcss_calendar_wait(davinci_rtc);
341 rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
342
343 davinci_rtcss_calendar_wait(davinci_rtc);
344 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
345
346 davinci_rtcss_calendar_wait(davinci_rtc);
347 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
348
349 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
350 rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
351 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
352
353 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
354
355 return 0;
356 }
357
davinci_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)358 static int davinci_rtc_alarm_irq_enable(struct device *dev,
359 unsigned int enabled)
360 {
361 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
362 unsigned long flags;
363 u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
364
365 spin_lock_irqsave(&davinci_rtc_lock, flags);
366
367 if (enabled)
368 rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
369 PRTCSS_RTC_CCTRL_HAEN |
370 PRTCSS_RTC_CCTRL_MAEN |
371 PRTCSS_RTC_CCTRL_ALMFLG |
372 PRTCSS_RTC_CCTRL_AIEN;
373 else
374 rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
375
376 davinci_rtcss_calendar_wait(davinci_rtc);
377 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
378
379 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
380
381 return 0;
382 }
383
davinci_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)384 static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
385 {
386 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
387 u16 days = 0;
388 u8 day0, day1;
389 unsigned long flags;
390
391 alm->time.tm_sec = 0;
392
393 spin_lock_irqsave(&davinci_rtc_lock, flags);
394
395 davinci_rtcss_calendar_wait(davinci_rtc);
396 alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
397
398 davinci_rtcss_calendar_wait(davinci_rtc);
399 alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
400
401 davinci_rtcss_calendar_wait(davinci_rtc);
402 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
403
404 davinci_rtcss_calendar_wait(davinci_rtc);
405 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
406
407 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
408 days |= day1;
409 days <<= 8;
410 days |= day0;
411
412 if (convertfromdays(days, &alm->time) < 0)
413 return -EINVAL;
414
415 alm->pending = !!(rtcss_read(davinci_rtc,
416 PRTCSS_RTC_CCTRL) &
417 PRTCSS_RTC_CCTRL_AIEN);
418 alm->enabled = alm->pending && device_may_wakeup(dev);
419
420 return 0;
421 }
422
davinci_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)423 static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
424 {
425 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
426 unsigned long flags;
427 u16 days;
428
429 if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
430 && alm->time.tm_year < 0) {
431 struct rtc_time tm;
432 unsigned long now, then;
433
434 davinci_rtc_read_time(dev, &tm);
435 rtc_tm_to_time(&tm, &now);
436
437 alm->time.tm_mday = tm.tm_mday;
438 alm->time.tm_mon = tm.tm_mon;
439 alm->time.tm_year = tm.tm_year;
440 rtc_tm_to_time(&alm->time, &then);
441
442 if (then < now) {
443 rtc_time_to_tm(now + 24 * 60 * 60, &tm);
444 alm->time.tm_mday = tm.tm_mday;
445 alm->time.tm_mon = tm.tm_mon;
446 alm->time.tm_year = tm.tm_year;
447 }
448 }
449
450 if (convert2days(&days, &alm->time) < 0)
451 return -EINVAL;
452
453 spin_lock_irqsave(&davinci_rtc_lock, flags);
454
455 davinci_rtcss_calendar_wait(davinci_rtc);
456 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
457
458 davinci_rtcss_calendar_wait(davinci_rtc);
459 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
460
461 davinci_rtcss_calendar_wait(davinci_rtc);
462 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
463
464 davinci_rtcss_calendar_wait(davinci_rtc);
465 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
466
467 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
468
469 return 0;
470 }
471
472 static const struct rtc_class_ops davinci_rtc_ops = {
473 .ioctl = davinci_rtc_ioctl,
474 .read_time = davinci_rtc_read_time,
475 .set_time = davinci_rtc_set_time,
476 .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
477 .read_alarm = davinci_rtc_read_alarm,
478 .set_alarm = davinci_rtc_set_alarm,
479 };
480
davinci_rtc_probe(struct platform_device * pdev)481 static int __init davinci_rtc_probe(struct platform_device *pdev)
482 {
483 struct device *dev = &pdev->dev;
484 struct davinci_rtc *davinci_rtc;
485 struct resource *res;
486 int ret = 0;
487
488 davinci_rtc = devm_kzalloc(&pdev->dev, sizeof(struct davinci_rtc), GFP_KERNEL);
489 if (!davinci_rtc)
490 return -ENOMEM;
491
492 davinci_rtc->irq = platform_get_irq(pdev, 0);
493 if (davinci_rtc->irq < 0) {
494 dev_err(dev, "no RTC irq\n");
495 return davinci_rtc->irq;
496 }
497
498 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
499 davinci_rtc->base = devm_ioremap_resource(dev, res);
500 if (IS_ERR(davinci_rtc->base))
501 return PTR_ERR(davinci_rtc->base);
502
503 platform_set_drvdata(pdev, davinci_rtc);
504
505 davinci_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
506 &davinci_rtc_ops, THIS_MODULE);
507 if (IS_ERR(davinci_rtc->rtc)) {
508 dev_err(dev, "unable to register RTC device, err %d\n",
509 ret);
510 return PTR_ERR(davinci_rtc->rtc);
511 }
512
513 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
514 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
515 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
516
517 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
518 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
519
520 ret = devm_request_irq(dev, davinci_rtc->irq, davinci_rtc_interrupt,
521 0, "davinci_rtc", davinci_rtc);
522 if (ret < 0) {
523 dev_err(dev, "unable to register davinci RTC interrupt\n");
524 return ret;
525 }
526
527 /* Enable interrupts */
528 rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
529 rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
530 PRTCSS_RTC_INTC_EXTENA1);
531
532 rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
533
534 device_init_wakeup(&pdev->dev, 0);
535
536 return 0;
537 }
538
davinci_rtc_remove(struct platform_device * pdev)539 static int __exit davinci_rtc_remove(struct platform_device *pdev)
540 {
541 struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
542
543 device_init_wakeup(&pdev->dev, 0);
544
545 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
546
547 return 0;
548 }
549
550 static struct platform_driver davinci_rtc_driver = {
551 .remove = __exit_p(davinci_rtc_remove),
552 .driver = {
553 .name = "rtc_davinci",
554 },
555 };
556
557 module_platform_driver_probe(davinci_rtc_driver, davinci_rtc_probe);
558
559 MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
560 MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
561 MODULE_LICENSE("GPL");
562