1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __DTS_MARVELL_PXA1928_CLOCK_H 3 #define __DTS_MARVELL_PXA1928_CLOCK_H 4 5 /* 6 * Clock ID values here correspond to the control register offset/4. 7 */ 8 9 /* apb peripherals */ 10 #define PXA1928_CLK_RTC 0x00 11 #define PXA1928_CLK_TWSI0 0x01 12 #define PXA1928_CLK_TWSI1 0x02 13 #define PXA1928_CLK_TWSI2 0x03 14 #define PXA1928_CLK_TWSI3 0x04 15 #define PXA1928_CLK_OWIRE 0x05 16 #define PXA1928_CLK_KPC 0x06 17 #define PXA1928_CLK_TB_ROTARY 0x07 18 #define PXA1928_CLK_SW_JTAG 0x08 19 #define PXA1928_CLK_TIMER1 0x09 20 #define PXA1928_CLK_UART0 0x0b 21 #define PXA1928_CLK_UART1 0x0c 22 #define PXA1928_CLK_UART2 0x0d 23 #define PXA1928_CLK_GPIO 0x0e 24 #define PXA1928_CLK_PWM0 0x0f 25 #define PXA1928_CLK_PWM1 0x10 26 #define PXA1928_CLK_PWM2 0x11 27 #define PXA1928_CLK_PWM3 0x12 28 #define PXA1928_CLK_SSP0 0x13 29 #define PXA1928_CLK_SSP1 0x14 30 #define PXA1928_CLK_SSP2 0x15 31 32 #define PXA1928_CLK_TWSI4 0x1f 33 #define PXA1928_CLK_TWSI5 0x20 34 #define PXA1928_CLK_UART3 0x22 35 #define PXA1928_CLK_THSENS_GLOB 0x24 36 #define PXA1928_CLK_THSENS_CPU 0x26 37 #define PXA1928_CLK_THSENS_VPU 0x27 38 #define PXA1928_CLK_THSENS_GC 0x28 39 #define PXA1928_APBC_NR_CLKS 0x30 40 41 42 /* axi peripherals */ 43 #define PXA1928_CLK_SDH0 0x15 44 #define PXA1928_CLK_SDH1 0x16 45 #define PXA1928_CLK_USB 0x17 46 #define PXA1928_CLK_NAND 0x18 47 #define PXA1928_CLK_DMA 0x19 48 49 #define PXA1928_CLK_SDH2 0x3a 50 #define PXA1928_CLK_SDH3 0x3b 51 #define PXA1928_CLK_HSIC 0x3e 52 #define PXA1928_CLK_SDH4 0x57 53 #define PXA1928_CLK_GC3D 0x5d 54 #define PXA1928_CLK_GC2D 0x5f 55 56 #define PXA1928_APMU_NR_CLKS 0x60 57 58 #endif 59