1 /*
2  * stv0900_reg.h
3  *
4  * Driver for ST STV0900 satellite demodulator IC.
5  *
6  * Copyright (C) ST Microelectronics.
7  * Copyright (C) 2009 NetUP Inc.
8  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  *
19  * GNU General Public License for more details.
20  */
21 
22 #ifndef STV0900_REG_H
23 #define STV0900_REG_H
24 
25 extern s32 shiftx(s32 x, int demod, s32 shift);
26 
27 #define REGx(x) shiftx(x, demod, 0x200)
28 #define FLDx(x) shiftx(x, demod, 0x2000000)
29 
30 /*MID*/
31 #define R0900_MID 0xf100
32 #define F0900_MCHIP_IDENT 0xf10000f0
33 #define F0900_MRELEASE 0xf100000f
34 
35 /*DACR1*/
36 #define R0900_DACR1 0xf113
37 #define F0900_DAC_MODE 0xf11300e0
38 #define F0900_DAC_VALUE1 0xf113000f
39 
40 /*DACR2*/
41 #define R0900_DACR2 0xf114
42 #define F0900_DAC_VALUE0 0xf11400ff
43 
44 /*OUTCFG*/
45 #define R0900_OUTCFG 0xf11c
46 #define F0900_OUTSERRS1_HZ 0xf11c0040
47 #define F0900_OUTSERRS2_HZ 0xf11c0020
48 #define F0900_OUTSERRS3_HZ 0xf11c0010
49 #define F0900_OUTPARRS3_HZ 0xf11c0008
50 
51 /*IRQSTATUS3*/
52 #define R0900_IRQSTATUS3 0xf120
53 #define F0900_SPLL_LOCK 0xf1200020
54 #define F0900_SSTREAM_LCK_3 0xf1200010
55 #define F0900_SSTREAM_LCK_2 0xf1200008
56 #define F0900_SSTREAM_LCK_1 0xf1200004
57 #define F0900_SDVBS1_PRF_2 0xf1200002
58 #define F0900_SDVBS1_PRF_1 0xf1200001
59 
60 /*IRQSTATUS2*/
61 #define R0900_IRQSTATUS2 0xf121
62 #define F0900_SSPY_ENDSIM_3 0xf1210080
63 #define F0900_SSPY_ENDSIM_2 0xf1210040
64 #define F0900_SSPY_ENDSIM_1 0xf1210020
65 #define F0900_SPKTDEL_ERROR_2 0xf1210010
66 #define F0900_SPKTDEL_LOCKB_2 0xf1210008
67 #define F0900_SPKTDEL_LOCK_2 0xf1210004
68 #define F0900_SPKTDEL_ERROR_1 0xf1210002
69 #define F0900_SPKTDEL_LOCKB_1 0xf1210001
70 
71 /*IRQSTATUS1*/
72 #define R0900_IRQSTATUS1 0xf122
73 #define F0900_SPKTDEL_LOCK_1 0xf1220080
74 #define F0900_SDEMOD_LOCKB_2 0xf1220004
75 #define F0900_SDEMOD_LOCK_2 0xf1220002
76 #define F0900_SDEMOD_IRQ_2 0xf1220001
77 
78 /*IRQSTATUS0*/
79 #define R0900_IRQSTATUS0 0xf123
80 #define F0900_SDEMOD_LOCKB_1 0xf1230080
81 #define F0900_SDEMOD_LOCK_1 0xf1230040
82 #define F0900_SDEMOD_IRQ_1 0xf1230020
83 #define F0900_SBCH_ERRFLAG 0xf1230010
84 #define F0900_SDISEQC2RX_IRQ 0xf1230008
85 #define F0900_SDISEQC2TX_IRQ 0xf1230004
86 #define F0900_SDISEQC1RX_IRQ 0xf1230002
87 #define F0900_SDISEQC1TX_IRQ 0xf1230001
88 
89 /*IRQMASK3*/
90 #define R0900_IRQMASK3 0xf124
91 #define F0900_MPLL_LOCK 0xf1240020
92 #define F0900_MSTREAM_LCK_3 0xf1240010
93 #define F0900_MSTREAM_LCK_2 0xf1240008
94 #define F0900_MSTREAM_LCK_1 0xf1240004
95 #define F0900_MDVBS1_PRF_2 0xf1240002
96 #define F0900_MDVBS1_PRF_1 0xf1240001
97 
98 /*IRQMASK2*/
99 #define R0900_IRQMASK2 0xf125
100 #define F0900_MSPY_ENDSIM_3 0xf1250080
101 #define F0900_MSPY_ENDSIM_2 0xf1250040
102 #define F0900_MSPY_ENDSIM_1 0xf1250020
103 #define F0900_MPKTDEL_ERROR_2 0xf1250010
104 #define F0900_MPKTDEL_LOCKB_2 0xf1250008
105 #define F0900_MPKTDEL_LOCK_2 0xf1250004
106 #define F0900_MPKTDEL_ERROR_1 0xf1250002
107 #define F0900_MPKTDEL_LOCKB_1 0xf1250001
108 
109 /*IRQMASK1*/
110 #define R0900_IRQMASK1 0xf126
111 #define F0900_MPKTDEL_LOCK_1 0xf1260080
112 #define F0900_MEXTPINB2 0xf1260040
113 #define F0900_MEXTPIN2 0xf1260020
114 #define F0900_MEXTPINB1 0xf1260010
115 #define F0900_MEXTPIN1 0xf1260008
116 #define F0900_MDEMOD_LOCKB_2 0xf1260004
117 #define F0900_MDEMOD_LOCK_2 0xf1260002
118 #define F0900_MDEMOD_IRQ_2 0xf1260001
119 
120 /*IRQMASK0*/
121 #define R0900_IRQMASK0 0xf127
122 #define F0900_MDEMOD_LOCKB_1 0xf1270080
123 #define F0900_MDEMOD_LOCK_1 0xf1270040
124 #define F0900_MDEMOD_IRQ_1 0xf1270020
125 #define F0900_MBCH_ERRFLAG 0xf1270010
126 #define F0900_MDISEQC2RX_IRQ 0xf1270008
127 #define F0900_MDISEQC2TX_IRQ 0xf1270004
128 #define F0900_MDISEQC1RX_IRQ 0xf1270002
129 #define F0900_MDISEQC1TX_IRQ 0xf1270001
130 
131 /*I2CCFG*/
132 #define R0900_I2CCFG 0xf129
133 #define F0900_I2C_FASTMODE 0xf1290008
134 #define F0900_I2CADDR_INC 0xf1290003
135 
136 /*P1_I2CRPT*/
137 #define R0900_P1_I2CRPT 0xf12a
138 #define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
139 #define F0900_P1_I2CT_ON 0xf12a0080
140 #define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
141 #define F0900_P1_ENARPT_LEVEL 0xf12a0070
142 #define F0900_P1_SCLT_DELAY 0xf12a0008
143 #define F0900_P1_STOP_ENABLE 0xf12a0004
144 #define F0900_P1_STOP_SDAT2SDA 0xf12a0002
145 
146 /*P2_I2CRPT*/
147 #define R0900_P2_I2CRPT 0xf12b
148 #define F0900_P2_I2CT_ON 0xf12b0080
149 #define F0900_P2_ENARPT_LEVEL 0xf12b0070
150 #define F0900_P2_SCLT_DELAY 0xf12b0008
151 #define F0900_P2_STOP_ENABLE 0xf12b0004
152 #define F0900_P2_STOP_SDAT2SDA 0xf12b0002
153 
154 /*IOPVALUE6*/
155 #define R0900_IOPVALUE6 0xf138
156 #define F0900_VSCL 0xf1380004
157 #define F0900_VSDA 0xf1380002
158 #define F0900_VDATA3_0 0xf1380001
159 
160 /*IOPVALUE5*/
161 #define R0900_IOPVALUE5 0xf139
162 #define F0900_VDATA3_1 0xf1390080
163 #define F0900_VDATA3_2 0xf1390040
164 #define F0900_VDATA3_3 0xf1390020
165 #define F0900_VDATA3_4 0xf1390010
166 #define F0900_VDATA3_5 0xf1390008
167 #define F0900_VDATA3_6 0xf1390004
168 #define F0900_VDATA3_7 0xf1390002
169 #define F0900_VCLKOUT3 0xf1390001
170 
171 /*IOPVALUE4*/
172 #define R0900_IOPVALUE4 0xf13a
173 #define F0900_VSTROUT3 0xf13a0080
174 #define F0900_VDPN3 0xf13a0040
175 #define F0900_VERROR3 0xf13a0020
176 #define F0900_VDATA2_7 0xf13a0010
177 #define F0900_VCLKOUT2 0xf13a0008
178 #define F0900_VSTROUT2 0xf13a0004
179 #define F0900_VDPN2 0xf13a0002
180 #define F0900_VERROR2 0xf13a0001
181 
182 /*IOPVALUE3*/
183 #define R0900_IOPVALUE3 0xf13b
184 #define F0900_VDATA1_7 0xf13b0080
185 #define F0900_VCLKOUT1 0xf13b0040
186 #define F0900_VSTROUT1 0xf13b0020
187 #define F0900_VDPN1 0xf13b0010
188 #define F0900_VERROR1 0xf13b0008
189 #define F0900_VCLKOUT27 0xf13b0004
190 #define F0900_VDISEQCOUT2 0xf13b0002
191 #define F0900_VSCLT2 0xf13b0001
192 
193 /*IOPVALUE2*/
194 #define R0900_IOPVALUE2 0xf13c
195 #define F0900_VSDAT2 0xf13c0080
196 #define F0900_VAGCRF2 0xf13c0040
197 #define F0900_VDISEQCOUT1 0xf13c0020
198 #define F0900_VSCLT1 0xf13c0010
199 #define F0900_VSDAT1 0xf13c0008
200 #define F0900_VAGCRF1 0xf13c0004
201 #define F0900_VDIRCLK 0xf13c0002
202 #define F0900_VSTDBY 0xf13c0001
203 
204 /*IOPVALUE1*/
205 #define R0900_IOPVALUE1 0xf13d
206 #define F0900_VCS1 0xf13d0080
207 #define F0900_VCS0 0xf13d0040
208 #define F0900_VGPIO13 0xf13d0020
209 #define F0900_VGPIO12 0xf13d0010
210 #define F0900_VGPIO11 0xf13d0008
211 #define F0900_VGPIO10 0xf13d0004
212 #define F0900_VGPIO9 0xf13d0002
213 #define F0900_VGPIO8 0xf13d0001
214 
215 /*IOPVALUE0*/
216 #define R0900_IOPVALUE0 0xf13e
217 #define F0900_VGPIO7 0xf13e0080
218 #define F0900_VGPIO6 0xf13e0040
219 #define F0900_VGPIO5 0xf13e0020
220 #define F0900_VGPIO4 0xf13e0010
221 #define F0900_VGPIO3 0xf13e0008
222 #define F0900_VGPIO2 0xf13e0004
223 #define F0900_VGPIO1 0xf13e0002
224 #define F0900_VCLKI2 0xf13e0001
225 
226 /*CLKI2CFG*/
227 #define R0900_CLKI2CFG 0xf140
228 #define F0900_CLKI2_OPD 0xf1400080
229 #define F0900_CLKI2_CONFIG 0xf140007e
230 #define F0900_CLKI2_XOR 0xf1400001
231 
232 /*GPIO1CFG*/
233 #define R0900_GPIO1CFG 0xf141
234 #define F0900_GPIO1_OPD 0xf1410080
235 #define F0900_GPIO1_CONFIG 0xf141007e
236 #define F0900_GPIO1_XOR 0xf1410001
237 
238 /*GPIO2CFG*/
239 #define R0900_GPIO2CFG 0xf142
240 #define F0900_GPIO2_OPD 0xf1420080
241 #define F0900_GPIO2_CONFIG 0xf142007e
242 #define F0900_GPIO2_XOR 0xf1420001
243 
244 /*GPIO3CFG*/
245 #define R0900_GPIO3CFG 0xf143
246 #define F0900_GPIO3_OPD 0xf1430080
247 #define F0900_GPIO3_CONFIG 0xf143007e
248 #define F0900_GPIO3_XOR 0xf1430001
249 
250 /*GPIO4CFG*/
251 #define R0900_GPIO4CFG 0xf144
252 #define F0900_GPIO4_OPD 0xf1440080
253 #define F0900_GPIO4_CONFIG 0xf144007e
254 #define F0900_GPIO4_XOR 0xf1440001
255 
256 /*GPIO5CFG*/
257 #define R0900_GPIO5CFG 0xf145
258 #define F0900_GPIO5_OPD 0xf1450080
259 #define F0900_GPIO5_CONFIG 0xf145007e
260 #define F0900_GPIO5_XOR 0xf1450001
261 
262 /*GPIO6CFG*/
263 #define R0900_GPIO6CFG 0xf146
264 #define F0900_GPIO6_OPD 0xf1460080
265 #define F0900_GPIO6_CONFIG 0xf146007e
266 #define F0900_GPIO6_XOR 0xf1460001
267 
268 /*GPIO7CFG*/
269 #define R0900_GPIO7CFG 0xf147
270 #define F0900_GPIO7_OPD 0xf1470080
271 #define F0900_GPIO7_CONFIG 0xf147007e
272 #define F0900_GPIO7_XOR 0xf1470001
273 
274 /*GPIO8CFG*/
275 #define R0900_GPIO8CFG 0xf148
276 #define F0900_GPIO8_OPD 0xf1480080
277 #define F0900_GPIO8_CONFIG 0xf148007e
278 #define F0900_GPIO8_XOR 0xf1480001
279 
280 /*GPIO9CFG*/
281 #define R0900_GPIO9CFG 0xf149
282 #define F0900_GPIO9_OPD 0xf1490080
283 #define F0900_GPIO9_CONFIG 0xf149007e
284 #define F0900_GPIO9_XOR 0xf1490001
285 
286 /*GPIO10CFG*/
287 #define R0900_GPIO10CFG 0xf14a
288 #define F0900_GPIO10_OPD 0xf14a0080
289 #define F0900_GPIO10_CONFIG 0xf14a007e
290 #define F0900_GPIO10_XOR 0xf14a0001
291 
292 /*GPIO11CFG*/
293 #define R0900_GPIO11CFG 0xf14b
294 #define F0900_GPIO11_OPD 0xf14b0080
295 #define F0900_GPIO11_CONFIG 0xf14b007e
296 #define F0900_GPIO11_XOR 0xf14b0001
297 
298 /*GPIO12CFG*/
299 #define R0900_GPIO12CFG 0xf14c
300 #define F0900_GPIO12_OPD 0xf14c0080
301 #define F0900_GPIO12_CONFIG 0xf14c007e
302 #define F0900_GPIO12_XOR 0xf14c0001
303 
304 /*GPIO13CFG*/
305 #define R0900_GPIO13CFG 0xf14d
306 #define F0900_GPIO13_OPD 0xf14d0080
307 #define F0900_GPIO13_CONFIG 0xf14d007e
308 #define F0900_GPIO13_XOR 0xf14d0001
309 
310 /*CS0CFG*/
311 #define R0900_CS0CFG 0xf14e
312 #define F0900_CS0_OPD 0xf14e0080
313 #define F0900_CS0_CONFIG 0xf14e007e
314 #define F0900_CS0_XOR 0xf14e0001
315 
316 /*CS1CFG*/
317 #define R0900_CS1CFG 0xf14f
318 #define F0900_CS1_OPD 0xf14f0080
319 #define F0900_CS1_CONFIG 0xf14f007e
320 #define F0900_CS1_XOR 0xf14f0001
321 
322 /*STDBYCFG*/
323 #define R0900_STDBYCFG 0xf150
324 #define F0900_STDBY_OPD 0xf1500080
325 #define F0900_STDBY_CONFIG 0xf150007e
326 #define F0900_STBDY_XOR 0xf1500001
327 
328 /*DIRCLKCFG*/
329 #define R0900_DIRCLKCFG 0xf151
330 #define F0900_DIRCLK_OPD 0xf1510080
331 #define F0900_DIRCLK_CONFIG 0xf151007e
332 #define F0900_DIRCLK_XOR 0xf1510001
333 
334 /*AGCRF1CFG*/
335 #define R0900_AGCRF1CFG 0xf152
336 #define F0900_AGCRF1_OPD 0xf1520080
337 #define F0900_AGCRF1_CONFIG 0xf152007e
338 #define F0900_AGCRF1_XOR 0xf1520001
339 
340 /*SDAT1CFG*/
341 #define R0900_SDAT1CFG 0xf153
342 #define F0900_SDAT1_OPD 0xf1530080
343 #define F0900_SDAT1_CONFIG 0xf153007e
344 #define F0900_SDAT1_XOR 0xf1530001
345 
346 /*SCLT1CFG*/
347 #define R0900_SCLT1CFG 0xf154
348 #define F0900_SCLT1_OPD 0xf1540080
349 #define F0900_SCLT1_CONFIG 0xf154007e
350 #define F0900_SCLT1_XOR 0xf1540001
351 
352 /*DISEQCO1CFG*/
353 #define R0900_DISEQCO1CFG 0xf155
354 #define F0900_DISEQCO1_OPD 0xf1550080
355 #define F0900_DISEQCO1_CONFIG 0xf155007e
356 #define F0900_DISEQC1_XOR 0xf1550001
357 
358 /*AGCRF2CFG*/
359 #define R0900_AGCRF2CFG 0xf156
360 #define F0900_AGCRF2_OPD 0xf1560080
361 #define F0900_AGCRF2_CONFIG 0xf156007e
362 #define F0900_AGCRF2_XOR 0xf1560001
363 
364 /*SDAT2CFG*/
365 #define R0900_SDAT2CFG 0xf157
366 #define F0900_SDAT2_OPD 0xf1570080
367 #define F0900_SDAT2_CONFIG 0xf157007e
368 #define F0900_SDAT2_XOR 0xf1570001
369 
370 /*SCLT2CFG*/
371 #define R0900_SCLT2CFG 0xf158
372 #define F0900_SCLT2_OPD 0xf1580080
373 #define F0900_SCLT2_CONFIG 0xf158007e
374 #define F0900_SCLT2_XOR 0xf1580001
375 
376 /*DISEQCO2CFG*/
377 #define R0900_DISEQCO2CFG 0xf159
378 #define F0900_DISEQCO2_OPD 0xf1590080
379 #define F0900_DISEQCO2_CONFIG 0xf159007e
380 #define F0900_DISEQC2_XOR 0xf1590001
381 
382 /*CLKOUT27CFG*/
383 #define R0900_CLKOUT27CFG 0xf15a
384 #define F0900_CLKOUT27_OPD 0xf15a0080
385 #define F0900_CLKOUT27_CONFIG 0xf15a007e
386 #define F0900_CLKOUT27_XOR 0xf15a0001
387 
388 /*ERROR1CFG*/
389 #define R0900_ERROR1CFG 0xf15b
390 #define F0900_ERROR1_OPD 0xf15b0080
391 #define F0900_ERROR1_CONFIG 0xf15b007e
392 #define F0900_ERROR1_XOR 0xf15b0001
393 
394 /*DPN1CFG*/
395 #define R0900_DPN1CFG 0xf15c
396 #define F0900_DPN1_OPD 0xf15c0080
397 #define F0900_DPN1_CONFIG 0xf15c007e
398 #define F0900_DPN1_XOR 0xf15c0001
399 
400 /*STROUT1CFG*/
401 #define R0900_STROUT1CFG 0xf15d
402 #define F0900_STROUT1_OPD 0xf15d0080
403 #define F0900_STROUT1_CONFIG 0xf15d007e
404 #define F0900_STROUT1_XOR 0xf15d0001
405 
406 /*CLKOUT1CFG*/
407 #define R0900_CLKOUT1CFG 0xf15e
408 #define F0900_CLKOUT1_OPD 0xf15e0080
409 #define F0900_CLKOUT1_CONFIG 0xf15e007e
410 #define F0900_CLKOUT1_XOR 0xf15e0001
411 
412 /*DATA71CFG*/
413 #define R0900_DATA71CFG 0xf15f
414 #define F0900_DATA71_OPD 0xf15f0080
415 #define F0900_DATA71_CONFIG 0xf15f007e
416 #define F0900_DATA71_XOR 0xf15f0001
417 
418 /*ERROR2CFG*/
419 #define R0900_ERROR2CFG 0xf160
420 #define F0900_ERROR2_OPD 0xf1600080
421 #define F0900_ERROR2_CONFIG 0xf160007e
422 #define F0900_ERROR2_XOR 0xf1600001
423 
424 /*DPN2CFG*/
425 #define R0900_DPN2CFG 0xf161
426 #define F0900_DPN2_OPD 0xf1610080
427 #define F0900_DPN2_CONFIG 0xf161007e
428 #define F0900_DPN2_XOR 0xf1610001
429 
430 /*STROUT2CFG*/
431 #define R0900_STROUT2CFG 0xf162
432 #define F0900_STROUT2_OPD 0xf1620080
433 #define F0900_STROUT2_CONFIG 0xf162007e
434 #define F0900_STROUT2_XOR 0xf1620001
435 
436 /*CLKOUT2CFG*/
437 #define R0900_CLKOUT2CFG 0xf163
438 #define F0900_CLKOUT2_OPD 0xf1630080
439 #define F0900_CLKOUT2_CONFIG 0xf163007e
440 #define F0900_CLKOUT2_XOR 0xf1630001
441 
442 /*DATA72CFG*/
443 #define R0900_DATA72CFG 0xf164
444 #define F0900_DATA72_OPD 0xf1640080
445 #define F0900_DATA72_CONFIG 0xf164007e
446 #define F0900_DATA72_XOR 0xf1640001
447 
448 /*ERROR3CFG*/
449 #define R0900_ERROR3CFG 0xf165
450 #define F0900_ERROR3_OPD 0xf1650080
451 #define F0900_ERROR3_CONFIG 0xf165007e
452 #define F0900_ERROR3_XOR 0xf1650001
453 
454 /*DPN3CFG*/
455 #define R0900_DPN3CFG 0xf166
456 #define F0900_DPN3_OPD 0xf1660080
457 #define F0900_DPN3_CONFIG 0xf166007e
458 #define F0900_DPN3_XOR 0xf1660001
459 
460 /*STROUT3CFG*/
461 #define R0900_STROUT3CFG 0xf167
462 #define F0900_STROUT3_OPD 0xf1670080
463 #define F0900_STROUT3_CONFIG 0xf167007e
464 #define F0900_STROUT3_XOR 0xf1670001
465 
466 /*CLKOUT3CFG*/
467 #define R0900_CLKOUT3CFG 0xf168
468 #define F0900_CLKOUT3_OPD 0xf1680080
469 #define F0900_CLKOUT3_CONFIG 0xf168007e
470 #define F0900_CLKOUT3_XOR 0xf1680001
471 
472 /*DATA73CFG*/
473 #define R0900_DATA73CFG 0xf169
474 #define F0900_DATA73_OPD 0xf1690080
475 #define F0900_DATA73_CONFIG 0xf169007e
476 #define F0900_DATA73_XOR 0xf1690001
477 
478 /*STRSTATUS1*/
479 #define R0900_STRSTATUS1 0xf16a
480 #define F0900_STRSTATUS_SEL2 0xf16a00f0
481 #define F0900_STRSTATUS_SEL1 0xf16a000f
482 
483 /*STRSTATUS2*/
484 #define R0900_STRSTATUS2 0xf16b
485 #define F0900_STRSTATUS_SEL4 0xf16b00f0
486 #define F0900_STRSTATUS_SEL3 0xf16b000f
487 
488 /*STRSTATUS3*/
489 #define R0900_STRSTATUS3 0xf16c
490 #define F0900_STRSTATUS_SEL6 0xf16c00f0
491 #define F0900_STRSTATUS_SEL5 0xf16c000f
492 
493 /*FSKTFC2*/
494 #define R0900_FSKTFC2 0xf170
495 #define F0900_FSKT_KMOD 0xf17000fc
496 #define F0900_FSKT_CAR2 0xf1700003
497 
498 /*FSKTFC1*/
499 #define R0900_FSKTFC1 0xf171
500 #define F0900_FSKT_CAR1 0xf17100ff
501 
502 /*FSKTFC0*/
503 #define R0900_FSKTFC0 0xf172
504 #define F0900_FSKT_CAR0 0xf17200ff
505 
506 /*FSKTDELTAF1*/
507 #define R0900_FSKTDELTAF1 0xf173
508 #define F0900_FSKT_DELTAF1 0xf173000f
509 
510 /*FSKTDELTAF0*/
511 #define R0900_FSKTDELTAF0 0xf174
512 #define F0900_FSKT_DELTAF0 0xf17400ff
513 
514 /*FSKTCTRL*/
515 #define R0900_FSKTCTRL 0xf175
516 #define F0900_FSKT_EN_SGN 0xf1750040
517 #define F0900_FSKT_MOD_SGN 0xf1750020
518 #define F0900_FSKT_MOD_EN 0xf175001c
519 #define F0900_FSKT_DACMODE 0xf1750003
520 
521 /*FSKRFC2*/
522 #define R0900_FSKRFC2 0xf176
523 #define F0900_FSKR_DETSGN 0xf1760040
524 #define F0900_FSKR_OUTSGN 0xf1760020
525 #define F0900_FSKR_KAGC 0xf176001c
526 #define F0900_FSKR_CAR2 0xf1760003
527 
528 /*FSKRFC1*/
529 #define R0900_FSKRFC1 0xf177
530 #define F0900_FSKR_CAR1 0xf17700ff
531 
532 /*FSKRFC0*/
533 #define R0900_FSKRFC0 0xf178
534 #define F0900_FSKR_CAR0 0xf17800ff
535 
536 /*FSKRK1*/
537 #define R0900_FSKRK1 0xf179
538 #define F0900_FSKR_K1_EXP 0xf17900e0
539 #define F0900_FSKR_K1_MANT 0xf179001f
540 
541 /*FSKRK2*/
542 #define R0900_FSKRK2 0xf17a
543 #define F0900_FSKR_K2_EXP 0xf17a00e0
544 #define F0900_FSKR_K2_MANT 0xf17a001f
545 
546 /*FSKRAGCR*/
547 #define R0900_FSKRAGCR 0xf17b
548 #define F0900_FSKR_OUTCTL 0xf17b00c0
549 #define F0900_FSKR_AGC_REF 0xf17b003f
550 
551 /*FSKRAGC*/
552 #define R0900_FSKRAGC 0xf17c
553 #define F0900_FSKR_AGC_ACCU 0xf17c00ff
554 
555 /*FSKRALPHA*/
556 #define R0900_FSKRALPHA 0xf17d
557 #define F0900_FSKR_ALPHA_EXP 0xf17d001c
558 #define F0900_FSKR_ALPHA_M 0xf17d0003
559 
560 /*FSKRPLTH1*/
561 #define R0900_FSKRPLTH1 0xf17e
562 #define F0900_FSKR_BETA 0xf17e00f0
563 #define F0900_FSKR_PLL_TRESH1 0xf17e000f
564 
565 /*FSKRPLTH0*/
566 #define R0900_FSKRPLTH0 0xf17f
567 #define F0900_FSKR_PLL_TRESH0 0xf17f00ff
568 
569 /*FSKRDF1*/
570 #define R0900_FSKRDF1 0xf180
571 #define F0900_FSKR_OUT 0xf1800080
572 #define F0900_FSKR_DELTAF1 0xf180001f
573 
574 /*FSKRDF0*/
575 #define R0900_FSKRDF0 0xf181
576 #define F0900_FSKR_DELTAF0 0xf18100ff
577 
578 /*FSKRSTEPP*/
579 #define R0900_FSKRSTEPP 0xf182
580 #define F0900_FSKR_STEP_PLUS 0xf18200ff
581 
582 /*FSKRSTEPM*/
583 #define R0900_FSKRSTEPM 0xf183
584 #define F0900_FSKR_STEP_MINUS 0xf18300ff
585 
586 /*FSKRDET1*/
587 #define R0900_FSKRDET1 0xf184
588 #define F0900_FSKR_DETECT 0xf1840080
589 #define F0900_FSKR_CARDET_ACCU1 0xf184000f
590 
591 /*FSKRDET0*/
592 #define R0900_FSKRDET0 0xf185
593 #define F0900_FSKR_CARDET_ACCU0 0xf18500ff
594 
595 /*FSKRDTH1*/
596 #define R0900_FSKRDTH1 0xf186
597 #define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
598 #define F0900_FSKR_CARDET_THRESH1 0xf186000f
599 
600 /*FSKRDTH0*/
601 #define R0900_FSKRDTH0 0xf187
602 #define F0900_FSKR_CARDET_THRESH0 0xf18700ff
603 
604 /*FSKRLOSS*/
605 #define R0900_FSKRLOSS 0xf188
606 #define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
607 
608 /*P2_DISTXCTL*/
609 #define R0900_P2_DISTXCTL 0xf190
610 #define F0900_P2_TIM_OFF 0xf1900080
611 #define F0900_P2_DISEQC_RESET 0xf1900040
612 #define F0900_P2_TIM_CMD 0xf1900030
613 #define F0900_P2_DIS_PRECHARGE 0xf1900008
614 #define F0900_P2_DISTX_MODE 0xf1900007
615 
616 /*P2_DISRXCTL*/
617 #define R0900_P2_DISRXCTL 0xf191
618 #define F0900_P2_RECEIVER_ON 0xf1910080
619 #define F0900_P2_IGNO_SHORT22K 0xf1910040
620 #define F0900_P2_ONECHIP_TRX 0xf1910020
621 #define F0900_P2_EXT_ENVELOP 0xf1910010
622 #define F0900_P2_PIN_SELECT0 0xf191000c
623 #define F0900_P2_IRQ_RXEND 0xf1910002
624 #define F0900_P2_IRQ_4NBYTES 0xf1910001
625 
626 /*P2_DISRX_ST0*/
627 #define R0900_P2_DISRX_ST0 0xf194
628 #define F0900_P2_RX_END 0xf1940080
629 #define F0900_P2_RX_ACTIVE 0xf1940040
630 #define F0900_P2_SHORT_22KHZ 0xf1940020
631 #define F0900_P2_CONT_TONE 0xf1940010
632 #define F0900_P2_FIFO_4BREADY 0xf1940008
633 #define F0900_P2_FIFO_EMPTY 0xf1940004
634 #define F0900_P2_ABORT_DISRX 0xf1940001
635 
636 /*P2_DISRX_ST1*/
637 #define R0900_P2_DISRX_ST1 0xf195
638 #define F0900_P2_RX_FAIL 0xf1950080
639 #define F0900_P2_FIFO_PARITYFAIL 0xf1950040
640 #define F0900_P2_RX_NONBYTE 0xf1950020
641 #define F0900_P2_FIFO_OVERFLOW 0xf1950010
642 #define F0900_P2_FIFO_BYTENBR 0xf195000f
643 
644 /*P2_DISRXDATA*/
645 #define R0900_P2_DISRXDATA 0xf196
646 #define F0900_P2_DISRX_DATA 0xf19600ff
647 
648 /*P2_DISTXDATA*/
649 #define R0900_P2_DISTXDATA 0xf197
650 #define F0900_P2_DISEQC_FIFO 0xf19700ff
651 
652 /*P2_DISTXSTATUS*/
653 #define R0900_P2_DISTXSTATUS 0xf198
654 #define F0900_P2_TX_FAIL 0xf1980080
655 #define F0900_P2_FIFO_FULL 0xf1980040
656 #define F0900_P2_TX_IDLE 0xf1980020
657 #define F0900_P2_GAP_BURST 0xf1980010
658 #define F0900_P2_TXFIFO_BYTES 0xf198000f
659 
660 /*P2_F22TX*/
661 #define R0900_P2_F22TX 0xf199
662 #define F0900_P2_F22_REG 0xf19900ff
663 
664 /*P2_F22RX*/
665 #define R0900_P2_F22RX 0xf19a
666 #define F0900_P2_F22RX_REG 0xf19a00ff
667 
668 /*P2_ACRPRESC*/
669 #define R0900_P2_ACRPRESC 0xf19c
670 #define F0900_P2_ACR_PRESC 0xf19c0007
671 
672 /*P2_ACRDIV*/
673 #define R0900_P2_ACRDIV 0xf19d
674 #define F0900_P2_ACR_DIV 0xf19d00ff
675 
676 /*P1_DISTXCTL*/
677 #define R0900_P1_DISTXCTL 0xf1a0
678 #define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
679 #define F0900_P1_TIM_OFF 0xf1a00080
680 #define F0900_P1_DISEQC_RESET 0xf1a00040
681 #define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
682 #define F0900_P1_TIM_CMD 0xf1a00030
683 #define F0900_P1_DIS_PRECHARGE 0xf1a00008
684 #define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
685 #define F0900_P1_DISTX_MODE 0xf1a00007
686 #define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
687 
688 /*P1_DISRXCTL*/
689 #define R0900_P1_DISRXCTL 0xf1a1
690 #define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
691 #define F0900_P1_RECEIVER_ON 0xf1a10080
692 #define F0900_P1_IGNO_SHORT22K 0xf1a10040
693 #define F0900_P1_ONECHIP_TRX 0xf1a10020
694 #define F0900_P1_EXT_ENVELOP 0xf1a10010
695 #define F0900_P1_PIN_SELECT0 0xf1a1000c
696 #define F0900_P1_IRQ_RXEND 0xf1a10002
697 #define F0900_P1_IRQ_4NBYTES 0xf1a10001
698 
699 /*P1_DISRX_ST0*/
700 #define R0900_P1_DISRX_ST0 0xf1a4
701 #define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
702 #define F0900_P1_RX_END 0xf1a40080
703 #define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
704 #define F0900_P1_RX_ACTIVE 0xf1a40040
705 #define F0900_P1_SHORT_22KHZ 0xf1a40020
706 #define F0900_P1_CONT_TONE 0xf1a40010
707 #define F0900_P1_FIFO_4BREADY 0xf1a40008
708 #define F0900_P1_FIFO_EMPTY 0xf1a40004
709 #define F0900_P1_ABORT_DISRX 0xf1a40001
710 
711 /*P1_DISRX_ST1*/
712 #define R0900_P1_DISRX_ST1 0xf1a5
713 #define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
714 #define F0900_P1_RX_FAIL 0xf1a50080
715 #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
716 #define F0900_P1_RX_NONBYTE 0xf1a50020
717 #define F0900_P1_FIFO_OVERFLOW 0xf1a50010
718 #define F0900_P1_FIFO_BYTENBR 0xf1a5000f
719 #define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
720 
721 /*P1_DISRXDATA*/
722 #define R0900_P1_DISRXDATA 0xf1a6
723 #define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
724 #define F0900_P1_DISRX_DATA 0xf1a600ff
725 
726 /*P1_DISTXDATA*/
727 #define R0900_P1_DISTXDATA 0xf1a7
728 #define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
729 #define F0900_P1_DISEQC_FIFO 0xf1a700ff
730 
731 /*P1_DISTXSTATUS*/
732 #define R0900_P1_DISTXSTATUS 0xf1a8
733 #define F0900_P1_TX_FAIL 0xf1a80080
734 #define F0900_P1_FIFO_FULL 0xf1a80040
735 #define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
736 #define F0900_P1_TX_IDLE 0xf1a80020
737 #define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
738 #define F0900_P1_GAP_BURST 0xf1a80010
739 #define F0900_P1_TXFIFO_BYTES 0xf1a8000f
740 
741 /*P1_F22TX*/
742 #define R0900_P1_F22TX 0xf1a9
743 #define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
744 #define F0900_P1_F22_REG 0xf1a900ff
745 
746 /*P1_F22RX*/
747 #define R0900_P1_F22RX 0xf1aa
748 #define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
749 #define F0900_P1_F22RX_REG 0xf1aa00ff
750 
751 /*P1_ACRPRESC*/
752 #define R0900_P1_ACRPRESC 0xf1ac
753 #define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
754 #define F0900_P1_ACR_PRESC 0xf1ac0007
755 
756 /*P1_ACRDIV*/
757 #define R0900_P1_ACRDIV 0xf1ad
758 #define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
759 #define F0900_P1_ACR_DIV 0xf1ad00ff
760 
761 /*NCOARSE*/
762 #define R0900_NCOARSE 0xf1b3
763 #define F0900_M_DIV 0xf1b300ff
764 
765 /*SYNTCTRL*/
766 #define R0900_SYNTCTRL 0xf1b6
767 #define F0900_STANDBY 0xf1b60080
768 #define F0900_BYPASSPLLCORE 0xf1b60040
769 #define F0900_SELX1RATIO 0xf1b60020
770 #define F0900_STOP_PLL 0xf1b60008
771 #define F0900_BYPASSPLLFSK 0xf1b60004
772 #define F0900_SELOSCI 0xf1b60002
773 #define F0900_BYPASSPLLADC 0xf1b60001
774 
775 /*FILTCTRL*/
776 #define R0900_FILTCTRL 0xf1b7
777 #define F0900_INV_CLK135 0xf1b70080
778 #define F0900_SEL_FSKCKDIV 0xf1b70004
779 #define F0900_INV_CLKFSK 0xf1b70002
780 #define F0900_BYPASS_APPLI 0xf1b70001
781 
782 /*PLLSTAT*/
783 #define R0900_PLLSTAT 0xf1b8
784 #define F0900_PLLLOCK 0xf1b80001
785 
786 /*STOPCLK1*/
787 #define R0900_STOPCLK1 0xf1c2
788 #define F0900_STOP_CLKPKDT2 0xf1c20040
789 #define F0900_STOP_CLKPKDT1 0xf1c20020
790 #define F0900_STOP_CLKFEC 0xf1c20010
791 #define F0900_STOP_CLKADCI2 0xf1c20008
792 #define F0900_INV_CLKADCI2 0xf1c20004
793 #define F0900_STOP_CLKADCI1 0xf1c20002
794 #define F0900_INV_CLKADCI1 0xf1c20001
795 
796 /*STOPCLK2*/
797 #define R0900_STOPCLK2 0xf1c3
798 #define F0900_STOP_CLKSAMP2 0xf1c30010
799 #define F0900_STOP_CLKSAMP1 0xf1c30008
800 #define F0900_STOP_CLKVIT2 0xf1c30004
801 #define F0900_STOP_CLKVIT1 0xf1c30002
802 #define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
803 #define F0900_STOP_CLKTS 0xf1c30001
804 
805 /*TSTTNR0*/
806 #define R0900_TSTTNR0 0xf1df
807 #define F0900_SEL_FSK 0xf1df0080
808 #define F0900_FSK_PON 0xf1df0004
809 
810 /*TSTTNR1*/
811 #define R0900_TSTTNR1 0xf1e0
812 #define F0900_ADC1_PON 0xf1e00002
813 #define F0900_ADC1_INMODE 0xf1e00001
814 
815 /*TSTTNR2*/
816 #define R0900_TSTTNR2 0xf1e1
817 #define F0900_DISEQC1_PON 0xf1e10020
818 
819 /*TSTTNR3*/
820 #define R0900_TSTTNR3 0xf1e2
821 #define F0900_ADC2_PON 0xf1e20002
822 #define F0900_ADC2_INMODE 0xf1e20001
823 
824 /*TSTTNR4*/
825 #define R0900_TSTTNR4 0xf1e3
826 #define F0900_DISEQC2_PON 0xf1e30020
827 
828 /*P2_IQCONST*/
829 #define R0900_P2_IQCONST 0xf200
830 #define F0900_P2_CONSTEL_SELECT 0xf2000060
831 #define F0900_P2_IQSYMB_SEL 0xf200001f
832 
833 /*P2_NOSCFG*/
834 #define R0900_P2_NOSCFG 0xf201
835 #define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
836 #define F0900_P2_NOSPLH_BETA 0xf2010018
837 #define F0900_P2_NOSDATA_BETA 0xf2010007
838 
839 /*P2_ISYMB*/
840 #define R0900_P2_ISYMB 0xf202
841 #define F0900_P2_I_SYMBOL 0xf20201ff
842 
843 /*P2_QSYMB*/
844 #define R0900_P2_QSYMB 0xf203
845 #define F0900_P2_Q_SYMBOL 0xf20301ff
846 
847 /*P2_AGC1CFG*/
848 #define R0900_P2_AGC1CFG 0xf204
849 #define F0900_P2_DC_FROZEN 0xf2040080
850 #define F0900_P2_DC_CORRECT 0xf2040040
851 #define F0900_P2_AMM_FROZEN 0xf2040020
852 #define F0900_P2_AMM_CORRECT 0xf2040010
853 #define F0900_P2_QUAD_FROZEN 0xf2040008
854 #define F0900_P2_QUAD_CORRECT 0xf2040004
855 
856 /*P2_AGC1CN*/
857 #define R0900_P2_AGC1CN 0xf206
858 #define F0900_P2_AGC1_LOCKED 0xf2060080
859 #define F0900_P2_AGC1_MINPOWER 0xf2060010
860 #define F0900_P2_AGCOUT_FAST 0xf2060008
861 #define F0900_P2_AGCIQ_BETA 0xf2060007
862 
863 /*P2_AGC1REF*/
864 #define R0900_P2_AGC1REF 0xf207
865 #define F0900_P2_AGCIQ_REF 0xf20700ff
866 
867 /*P2_IDCCOMP*/
868 #define R0900_P2_IDCCOMP 0xf208
869 #define F0900_P2_IAVERAGE_ADJ 0xf20801ff
870 
871 /*P2_QDCCOMP*/
872 #define R0900_P2_QDCCOMP 0xf209
873 #define F0900_P2_QAVERAGE_ADJ 0xf20901ff
874 
875 /*P2_POWERI*/
876 #define R0900_P2_POWERI 0xf20a
877 #define F0900_P2_POWER_I 0xf20a00ff
878 
879 /*P2_POWERQ*/
880 #define R0900_P2_POWERQ 0xf20b
881 #define F0900_P2_POWER_Q 0xf20b00ff
882 
883 /*P2_AGC1AMM*/
884 #define R0900_P2_AGC1AMM 0xf20c
885 #define F0900_P2_AMM_VALUE 0xf20c00ff
886 
887 /*P2_AGC1QUAD*/
888 #define R0900_P2_AGC1QUAD 0xf20d
889 #define F0900_P2_QUAD_VALUE 0xf20d01ff
890 
891 /*P2_AGCIQIN1*/
892 #define R0900_P2_AGCIQIN1 0xf20e
893 #define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
894 
895 /*P2_AGCIQIN0*/
896 #define R0900_P2_AGCIQIN0 0xf20f
897 #define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
898 
899 /*P2_DEMOD*/
900 #define R0900_P2_DEMOD 0xf210
901 #define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
902 #define F0900_P2_SPECINV_CONTROL 0xf2100030
903 #define F0900_P2_FORCE_ENASAMP 0xf2100008
904 #define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
905 #define F0900_P2_ROLLOFF_CONTROL 0xf2100003
906 
907 /*P2_DMDMODCOD*/
908 #define R0900_P2_DMDMODCOD 0xf211
909 #define F0900_P2_MANUAL_MODCOD 0xf2110080
910 #define F0900_P2_DEMOD_MODCOD 0xf211007c
911 #define F0900_P2_DEMOD_TYPE 0xf2110003
912 
913 /*P2_DSTATUS*/
914 #define R0900_P2_DSTATUS 0xf212
915 #define F0900_P2_CAR_LOCK 0xf2120080
916 #define F0900_P2_TMGLOCK_QUALITY 0xf2120060
917 #define F0900_P2_LOCK_DEFINITIF 0xf2120008
918 #define F0900_P2_OVADC_DETECT 0xf2120001
919 
920 /*P2_DSTATUS2*/
921 #define R0900_P2_DSTATUS2 0xf213
922 #define F0900_P2_DEMOD_DELOCK 0xf2130080
923 #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
924 #define F0900_P2_AGC2_OVERFLOW 0xf2130004
925 #define F0900_P2_CFR_OVERFLOW 0xf2130002
926 #define F0900_P2_GAMMA_OVERUNDER 0xf2130001
927 
928 /*P2_DMDCFGMD*/
929 #define R0900_P2_DMDCFGMD 0xf214
930 #define F0900_P2_DVBS2_ENABLE 0xf2140080
931 #define F0900_P2_DVBS1_ENABLE 0xf2140040
932 #define F0900_P2_SCAN_ENABLE 0xf2140010
933 #define F0900_P2_CFR_AUTOSCAN 0xf2140008
934 #define F0900_P2_TUN_RNG 0xf2140003
935 
936 /*P2_DMDCFG2*/
937 #define R0900_P2_DMDCFG2 0xf215
938 #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
939 #define F0900_P2_INFINITE_RELOCK 0xf2150010
940 
941 /*P2_DMDISTATE*/
942 #define R0900_P2_DMDISTATE 0xf216
943 #define F0900_P2_I2C_DEMOD_MODE 0xf216001f
944 
945 /*P2_DMDT0M*/
946 #define R0900_P2_DMDT0M 0xf217
947 #define F0900_P2_DMDT0_MIN 0xf21700ff
948 
949 /*P2_DMDSTATE*/
950 #define R0900_P2_DMDSTATE 0xf21b
951 #define F0900_P2_HEADER_MODE 0xf21b0060
952 
953 /*P2_DMDFLYW*/
954 #define R0900_P2_DMDFLYW 0xf21c
955 #define F0900_P2_I2C_IRQVAL 0xf21c00f0
956 #define F0900_P2_FLYWHEEL_CPT 0xf21c000f
957 
958 /*P2_DSTATUS3*/
959 #define R0900_P2_DSTATUS3 0xf21d
960 #define F0900_P2_DEMOD_CFGMODE 0xf21d0060
961 
962 /*P2_DMDCFG3*/
963 #define R0900_P2_DMDCFG3 0xf21e
964 #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
965 
966 /*P2_DMDCFG4*/
967 #define R0900_P2_DMDCFG4 0xf21f
968 #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
969 
970 /*P2_CORRELMANT*/
971 #define R0900_P2_CORRELMANT 0xf220
972 #define F0900_P2_CORREL_MANT 0xf22000ff
973 
974 /*P2_CORRELABS*/
975 #define R0900_P2_CORRELABS 0xf221
976 #define F0900_P2_CORREL_ABS 0xf22100ff
977 
978 /*P2_CORRELEXP*/
979 #define R0900_P2_CORRELEXP 0xf222
980 #define F0900_P2_CORREL_ABSEXP 0xf22200f0
981 #define F0900_P2_CORREL_EXP 0xf222000f
982 
983 /*P2_PLHMODCOD*/
984 #define R0900_P2_PLHMODCOD 0xf224
985 #define F0900_P2_SPECINV_DEMOD 0xf2240080
986 #define F0900_P2_PLH_MODCOD 0xf224007c
987 #define F0900_P2_PLH_TYPE 0xf2240003
988 
989 /*P2_DMDREG*/
990 #define R0900_P2_DMDREG 0xf225
991 #define F0900_P2_DECIM_PLFRAMES 0xf2250001
992 
993 /*P2_AGC2O*/
994 #define R0900_P2_AGC2O 0xf22c
995 #define F0900_P2_AGC2_COEF 0xf22c0007
996 
997 /*P2_AGC2REF*/
998 #define R0900_P2_AGC2REF 0xf22d
999 #define F0900_P2_AGC2_REF 0xf22d00ff
1000 
1001 /*P2_AGC1ADJ*/
1002 #define R0900_P2_AGC1ADJ 0xf22e
1003 #define F0900_P2_AGC1_ADJUSTED 0xf22e007f
1004 
1005 /*P2_AGC2I1*/
1006 #define R0900_P2_AGC2I1 0xf236
1007 #define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
1008 
1009 /*P2_AGC2I0*/
1010 #define R0900_P2_AGC2I0 0xf237
1011 #define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
1012 
1013 /*P2_CARCFG*/
1014 #define R0900_P2_CARCFG 0xf238
1015 #define F0900_P2_CFRUPLOW_AUTO 0xf2380080
1016 #define F0900_P2_CFRUPLOW_TEST 0xf2380040
1017 #define F0900_P2_ROTAON 0xf2380004
1018 #define F0900_P2_PH_DET_ALGO 0xf2380003
1019 
1020 /*P2_ACLC*/
1021 #define R0900_P2_ACLC 0xf239
1022 #define F0900_P2_CAR_ALPHA_MANT 0xf2390030
1023 #define F0900_P2_CAR_ALPHA_EXP 0xf239000f
1024 
1025 /*P2_BCLC*/
1026 #define R0900_P2_BCLC 0xf23a
1027 #define F0900_P2_CAR_BETA_MANT 0xf23a0030
1028 #define F0900_P2_CAR_BETA_EXP 0xf23a000f
1029 
1030 /*P2_CARFREQ*/
1031 #define R0900_P2_CARFREQ 0xf23d
1032 #define F0900_P2_KC_COARSE_EXP 0xf23d00f0
1033 #define F0900_P2_BETA_FREQ 0xf23d000f
1034 
1035 /*P2_CARHDR*/
1036 #define R0900_P2_CARHDR 0xf23e
1037 #define F0900_P2_K_FREQ_HDR 0xf23e00ff
1038 
1039 /*P2_LDT*/
1040 #define R0900_P2_LDT 0xf23f
1041 #define F0900_P2_CARLOCK_THRES 0xf23f01ff
1042 
1043 /*P2_LDT2*/
1044 #define R0900_P2_LDT2 0xf240
1045 #define F0900_P2_CARLOCK_THRES2 0xf24001ff
1046 
1047 /*P2_CFRICFG*/
1048 #define R0900_P2_CFRICFG 0xf241
1049 #define F0900_P2_NEG_CFRSTEP 0xf2410001
1050 
1051 /*P2_CFRUP1*/
1052 #define R0900_P2_CFRUP1 0xf242
1053 #define F0900_P2_CFR_UP1 0xf24201ff
1054 
1055 /*P2_CFRUP0*/
1056 #define R0900_P2_CFRUP0 0xf243
1057 #define F0900_P2_CFR_UP0 0xf24300ff
1058 
1059 /*P2_CFRLOW1*/
1060 #define R0900_P2_CFRLOW1 0xf246
1061 #define F0900_P2_CFR_LOW1 0xf24601ff
1062 
1063 /*P2_CFRLOW0*/
1064 #define R0900_P2_CFRLOW0 0xf247
1065 #define F0900_P2_CFR_LOW0 0xf24700ff
1066 
1067 /*P2_CFRINIT1*/
1068 #define R0900_P2_CFRINIT1 0xf248
1069 #define F0900_P2_CFR_INIT1 0xf24801ff
1070 
1071 /*P2_CFRINIT0*/
1072 #define R0900_P2_CFRINIT0 0xf249
1073 #define F0900_P2_CFR_INIT0 0xf24900ff
1074 
1075 /*P2_CFRINC1*/
1076 #define R0900_P2_CFRINC1 0xf24a
1077 #define F0900_P2_MANUAL_CFRINC 0xf24a0080
1078 #define F0900_P2_CFR_INC1 0xf24a003f
1079 
1080 /*P2_CFRINC0*/
1081 #define R0900_P2_CFRINC0 0xf24b
1082 #define F0900_P2_CFR_INC0 0xf24b00f8
1083 
1084 /*P2_CFR2*/
1085 #define R0900_P2_CFR2 0xf24c
1086 #define F0900_P2_CAR_FREQ2 0xf24c01ff
1087 
1088 /*P2_CFR1*/
1089 #define R0900_P2_CFR1 0xf24d
1090 #define F0900_P2_CAR_FREQ1 0xf24d00ff
1091 
1092 /*P2_CFR0*/
1093 #define R0900_P2_CFR0 0xf24e
1094 #define F0900_P2_CAR_FREQ0 0xf24e00ff
1095 
1096 /*P2_LDI*/
1097 #define R0900_P2_LDI 0xf24f
1098 #define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
1099 
1100 /*P2_TMGCFG*/
1101 #define R0900_P2_TMGCFG 0xf250
1102 #define F0900_P2_TMGLOCK_BETA 0xf25000c0
1103 #define F0900_P2_DO_TIMING_CORR 0xf2500010
1104 #define F0900_P2_TMG_MINFREQ 0xf2500003
1105 
1106 /*P2_RTC*/
1107 #define R0900_P2_RTC 0xf251
1108 #define F0900_P2_TMGALPHA_EXP 0xf25100f0
1109 #define F0900_P2_TMGBETA_EXP 0xf251000f
1110 
1111 /*P2_RTCS2*/
1112 #define R0900_P2_RTCS2 0xf252
1113 #define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
1114 #define F0900_P2_TMGBETAS2_EXP 0xf252000f
1115 
1116 /*P2_TMGTHRISE*/
1117 #define R0900_P2_TMGTHRISE 0xf253
1118 #define F0900_P2_TMGLOCK_THRISE 0xf25300ff
1119 
1120 /*P2_TMGTHFALL*/
1121 #define R0900_P2_TMGTHFALL 0xf254
1122 #define F0900_P2_TMGLOCK_THFALL 0xf25400ff
1123 
1124 /*P2_SFRUPRATIO*/
1125 #define R0900_P2_SFRUPRATIO 0xf255
1126 #define F0900_P2_SFR_UPRATIO 0xf25500ff
1127 
1128 /*P2_SFRLOWRATIO*/
1129 #define R0900_P2_SFRLOWRATIO 0xf256
1130 #define F0900_P2_SFR_LOWRATIO 0xf25600ff
1131 
1132 /*P2_KREFTMG*/
1133 #define R0900_P2_KREFTMG 0xf258
1134 #define F0900_P2_KREF_TMG 0xf25800ff
1135 
1136 /*P2_SFRSTEP*/
1137 #define R0900_P2_SFRSTEP 0xf259
1138 #define F0900_P2_SFR_SCANSTEP 0xf25900f0
1139 #define F0900_P2_SFR_CENTERSTEP 0xf259000f
1140 
1141 /*P2_TMGCFG2*/
1142 #define R0900_P2_TMGCFG2 0xf25a
1143 #define F0900_P2_SFRRATIO_FINE 0xf25a0001
1144 
1145 /*P2_KREFTMG2*/
1146 #define R0900_P2_KREFTMG2 0xf25b
1147 #define F0900_P2_KREF_TMG2 0xf25b00ff
1148 
1149 /*P2_SFRINIT1*/
1150 #define R0900_P2_SFRINIT1 0xf25e
1151 #define F0900_P2_SFR_INIT1 0xf25e007f
1152 
1153 /*P2_SFRINIT0*/
1154 #define R0900_P2_SFRINIT0 0xf25f
1155 #define F0900_P2_SFR_INIT0 0xf25f00ff
1156 
1157 /*P2_SFRUP1*/
1158 #define R0900_P2_SFRUP1 0xf260
1159 #define F0900_P2_AUTO_GUP 0xf2600080
1160 #define F0900_P2_SYMB_FREQ_UP1 0xf260007f
1161 
1162 /*P2_SFRUP0*/
1163 #define R0900_P2_SFRUP0 0xf261
1164 #define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
1165 
1166 /*P2_SFRLOW1*/
1167 #define R0900_P2_SFRLOW1 0xf262
1168 #define F0900_P2_AUTO_GLOW 0xf2620080
1169 #define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
1170 
1171 /*P2_SFRLOW0*/
1172 #define R0900_P2_SFRLOW0 0xf263
1173 #define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
1174 
1175 /*P2_SFR3*/
1176 #define R0900_P2_SFR3 0xf264
1177 #define F0900_P2_SYMB_FREQ3 0xf26400ff
1178 
1179 /*P2_SFR2*/
1180 #define R0900_P2_SFR2 0xf265
1181 #define F0900_P2_SYMB_FREQ2 0xf26500ff
1182 
1183 /*P2_SFR1*/
1184 #define R0900_P2_SFR1 0xf266
1185 #define F0900_P2_SYMB_FREQ1 0xf26600ff
1186 
1187 /*P2_SFR0*/
1188 #define R0900_P2_SFR0 0xf267
1189 #define F0900_P2_SYMB_FREQ0 0xf26700ff
1190 
1191 /*P2_TMGREG2*/
1192 #define R0900_P2_TMGREG2 0xf268
1193 #define F0900_P2_TMGREG2 0xf26800ff
1194 
1195 /*P2_TMGREG1*/
1196 #define R0900_P2_TMGREG1 0xf269
1197 #define F0900_P2_TMGREG1 0xf26900ff
1198 
1199 /*P2_TMGREG0*/
1200 #define R0900_P2_TMGREG0 0xf26a
1201 #define F0900_P2_TMGREG0 0xf26a00ff
1202 
1203 /*P2_TMGLOCK1*/
1204 #define R0900_P2_TMGLOCK1 0xf26b
1205 #define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
1206 
1207 /*P2_TMGLOCK0*/
1208 #define R0900_P2_TMGLOCK0 0xf26c
1209 #define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
1210 
1211 /*P2_TMGOBS*/
1212 #define R0900_P2_TMGOBS 0xf26d
1213 #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
1214 
1215 /*P2_EQUALCFG*/
1216 #define R0900_P2_EQUALCFG 0xf26f
1217 #define F0900_P2_EQUAL_ON 0xf26f0040
1218 #define F0900_P2_MU_EQUALDFE 0xf26f0007
1219 
1220 /*P2_EQUAI1*/
1221 #define R0900_P2_EQUAI1 0xf270
1222 #define F0900_P2_EQUA_ACCI1 0xf27001ff
1223 
1224 /*P2_EQUAQ1*/
1225 #define R0900_P2_EQUAQ1 0xf271
1226 #define F0900_P2_EQUA_ACCQ1 0xf27101ff
1227 
1228 /*P2_EQUAI2*/
1229 #define R0900_P2_EQUAI2 0xf272
1230 #define F0900_P2_EQUA_ACCI2 0xf27201ff
1231 
1232 /*P2_EQUAQ2*/
1233 #define R0900_P2_EQUAQ2 0xf273
1234 #define F0900_P2_EQUA_ACCQ2 0xf27301ff
1235 
1236 /*P2_EQUAI3*/
1237 #define R0900_P2_EQUAI3 0xf274
1238 #define F0900_P2_EQUA_ACCI3 0xf27401ff
1239 
1240 /*P2_EQUAQ3*/
1241 #define R0900_P2_EQUAQ3 0xf275
1242 #define F0900_P2_EQUA_ACCQ3 0xf27501ff
1243 
1244 /*P2_EQUAI4*/
1245 #define R0900_P2_EQUAI4 0xf276
1246 #define F0900_P2_EQUA_ACCI4 0xf27601ff
1247 
1248 /*P2_EQUAQ4*/
1249 #define R0900_P2_EQUAQ4 0xf277
1250 #define F0900_P2_EQUA_ACCQ4 0xf27701ff
1251 
1252 /*P2_EQUAI5*/
1253 #define R0900_P2_EQUAI5 0xf278
1254 #define F0900_P2_EQUA_ACCI5 0xf27801ff
1255 
1256 /*P2_EQUAQ5*/
1257 #define R0900_P2_EQUAQ5 0xf279
1258 #define F0900_P2_EQUA_ACCQ5 0xf27901ff
1259 
1260 /*P2_EQUAI6*/
1261 #define R0900_P2_EQUAI6 0xf27a
1262 #define F0900_P2_EQUA_ACCI6 0xf27a01ff
1263 
1264 /*P2_EQUAQ6*/
1265 #define R0900_P2_EQUAQ6 0xf27b
1266 #define F0900_P2_EQUA_ACCQ6 0xf27b01ff
1267 
1268 /*P2_EQUAI7*/
1269 #define R0900_P2_EQUAI7 0xf27c
1270 #define F0900_P2_EQUA_ACCI7 0xf27c01ff
1271 
1272 /*P2_EQUAQ7*/
1273 #define R0900_P2_EQUAQ7 0xf27d
1274 #define F0900_P2_EQUA_ACCQ7 0xf27d01ff
1275 
1276 /*P2_EQUAI8*/
1277 #define R0900_P2_EQUAI8 0xf27e
1278 #define F0900_P2_EQUA_ACCI8 0xf27e01ff
1279 
1280 /*P2_EQUAQ8*/
1281 #define R0900_P2_EQUAQ8 0xf27f
1282 #define F0900_P2_EQUA_ACCQ8 0xf27f01ff
1283 
1284 /*P2_NNOSDATAT1*/
1285 #define R0900_P2_NNOSDATAT1 0xf280
1286 #define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
1287 
1288 /*P2_NNOSDATAT0*/
1289 #define R0900_P2_NNOSDATAT0 0xf281
1290 #define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
1291 
1292 /*P2_NNOSDATA1*/
1293 #define R0900_P2_NNOSDATA1 0xf282
1294 #define F0900_P2_NOSDATA_NORMED1 0xf28200ff
1295 
1296 /*P2_NNOSDATA0*/
1297 #define R0900_P2_NNOSDATA0 0xf283
1298 #define F0900_P2_NOSDATA_NORMED0 0xf28300ff
1299 
1300 /*P2_NNOSPLHT1*/
1301 #define R0900_P2_NNOSPLHT1 0xf284
1302 #define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
1303 
1304 /*P2_NNOSPLHT0*/
1305 #define R0900_P2_NNOSPLHT0 0xf285
1306 #define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
1307 
1308 /*P2_NNOSPLH1*/
1309 #define R0900_P2_NNOSPLH1 0xf286
1310 #define F0900_P2_NOSPLH_NORMED1 0xf28600ff
1311 
1312 /*P2_NNOSPLH0*/
1313 #define R0900_P2_NNOSPLH0 0xf287
1314 #define F0900_P2_NOSPLH_NORMED0 0xf28700ff
1315 
1316 /*P2_NOSDATAT1*/
1317 #define R0900_P2_NOSDATAT1 0xf288
1318 #define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
1319 
1320 /*P2_NOSDATAT0*/
1321 #define R0900_P2_NOSDATAT0 0xf289
1322 #define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
1323 
1324 /*P2_NOSDATA1*/
1325 #define R0900_P2_NOSDATA1 0xf28a
1326 #define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
1327 
1328 /*P2_NOSDATA0*/
1329 #define R0900_P2_NOSDATA0 0xf28b
1330 #define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
1331 
1332 /*P2_NOSPLHT1*/
1333 #define R0900_P2_NOSPLHT1 0xf28c
1334 #define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
1335 
1336 /*P2_NOSPLHT0*/
1337 #define R0900_P2_NOSPLHT0 0xf28d
1338 #define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
1339 
1340 /*P2_NOSPLH1*/
1341 #define R0900_P2_NOSPLH1 0xf28e
1342 #define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
1343 
1344 /*P2_NOSPLH0*/
1345 #define R0900_P2_NOSPLH0 0xf28f
1346 #define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
1347 
1348 /*P2_CAR2CFG*/
1349 #define R0900_P2_CAR2CFG 0xf290
1350 #define F0900_P2_CARRIER3_DISABLE 0xf2900040
1351 #define F0900_P2_ROTA2ON 0xf2900004
1352 #define F0900_P2_PH_DET_ALGO2 0xf2900003
1353 
1354 /*P2_CFR2CFR1*/
1355 #define R0900_P2_CFR2CFR1 0xf291
1356 #define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
1357 #define F0900_P2_EN_S2CAR2CENTER 0xf2910020
1358 #define F0900_P2_DIS_BCHERRCFR2 0xf2910010
1359 #define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
1360 
1361 /*P2_CFR22*/
1362 #define R0900_P2_CFR22 0xf293
1363 #define F0900_P2_CAR2_FREQ2 0xf29301ff
1364 
1365 /*P2_CFR21*/
1366 #define R0900_P2_CFR21 0xf294
1367 #define F0900_P2_CAR2_FREQ1 0xf29400ff
1368 
1369 /*P2_CFR20*/
1370 #define R0900_P2_CFR20 0xf295
1371 #define F0900_P2_CAR2_FREQ0 0xf29500ff
1372 
1373 /*P2_ACLC2S2Q*/
1374 #define R0900_P2_ACLC2S2Q 0xf297
1375 #define F0900_P2_ENAB_SPSKSYMB 0xf2970080
1376 #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
1377 #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
1378 
1379 /*P2_ACLC2S28*/
1380 #define R0900_P2_ACLC2S28 0xf298
1381 #define F0900_P2_OLDI3Q_MODE 0xf2980080
1382 #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
1383 #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
1384 
1385 /*P2_ACLC2S216A*/
1386 #define R0900_P2_ACLC2S216A 0xf299
1387 #define F0900_P2_DIS_C3STOPA2 0xf2990080
1388 #define F0900_P2_CAR2S2_16ADERAT 0xf2990040
1389 #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
1390 #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
1391 
1392 /*P2_ACLC2S232A*/
1393 #define R0900_P2_ACLC2S232A 0xf29a
1394 #define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
1395 #define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
1396 #define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
1397 
1398 /*P2_BCLC2S2Q*/
1399 #define R0900_P2_BCLC2S2Q 0xf29c
1400 #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
1401 #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
1402 
1403 /*P2_BCLC2S28*/
1404 #define R0900_P2_BCLC2S28 0xf29d
1405 #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
1406 #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
1407 
1408 /*P2_BCLC2S216A*/
1409 #define R0900_P2_BCLC2S216A 0xf29e
1410 
1411 /*P2_BCLC2S232A*/
1412 #define R0900_P2_BCLC2S232A 0xf29f
1413 
1414 /*P2_PLROOT2*/
1415 #define R0900_P2_PLROOT2 0xf2ac
1416 #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
1417 #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
1418 
1419 /*P2_PLROOT1*/
1420 #define R0900_P2_PLROOT1 0xf2ad
1421 #define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
1422 
1423 /*P2_PLROOT0*/
1424 #define R0900_P2_PLROOT0 0xf2ae
1425 #define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
1426 
1427 /*P2_MODCODLST0*/
1428 #define R0900_P2_MODCODLST0 0xf2b0
1429 
1430 /*P2_MODCODLST1*/
1431 #define R0900_P2_MODCODLST1 0xf2b1
1432 #define F0900_P2_DIS_MODCOD29 0xf2b100f0
1433 #define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
1434 
1435 /*P2_MODCODLST2*/
1436 #define R0900_P2_MODCODLST2 0xf2b2
1437 #define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
1438 #define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
1439 
1440 /*P2_MODCODLST3*/
1441 #define R0900_P2_MODCODLST3 0xf2b3
1442 #define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
1443 #define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
1444 
1445 /*P2_MODCODLST4*/
1446 #define R0900_P2_MODCODLST4 0xf2b4
1447 #define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
1448 #define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
1449 
1450 /*P2_MODCODLST5*/
1451 #define R0900_P2_MODCODLST5 0xf2b5
1452 #define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
1453 #define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
1454 
1455 /*P2_MODCODLST6*/
1456 #define R0900_P2_MODCODLST6 0xf2b6
1457 #define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
1458 #define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
1459 
1460 /*P2_MODCODLST7*/
1461 #define R0900_P2_MODCODLST7 0xf2b7
1462 #define F0900_P2_DIS_8P_9_10 0xf2b700f0
1463 #define F0900_P2_DIS_8P_8_9 0xf2b7000f
1464 
1465 /*P2_MODCODLST8*/
1466 #define R0900_P2_MODCODLST8 0xf2b8
1467 #define F0900_P2_DIS_8P_5_6 0xf2b800f0
1468 #define F0900_P2_DIS_8P_3_4 0xf2b8000f
1469 
1470 /*P2_MODCODLST9*/
1471 #define R0900_P2_MODCODLST9 0xf2b9
1472 #define F0900_P2_DIS_8P_2_3 0xf2b900f0
1473 #define F0900_P2_DIS_8P_3_5 0xf2b9000f
1474 
1475 /*P2_MODCODLSTA*/
1476 #define R0900_P2_MODCODLSTA 0xf2ba
1477 #define F0900_P2_DIS_QP_9_10 0xf2ba00f0
1478 #define F0900_P2_DIS_QP_8_9 0xf2ba000f
1479 
1480 /*P2_MODCODLSTB*/
1481 #define R0900_P2_MODCODLSTB 0xf2bb
1482 #define F0900_P2_DIS_QP_5_6 0xf2bb00f0
1483 #define F0900_P2_DIS_QP_4_5 0xf2bb000f
1484 
1485 /*P2_MODCODLSTC*/
1486 #define R0900_P2_MODCODLSTC 0xf2bc
1487 #define F0900_P2_DIS_QP_3_4 0xf2bc00f0
1488 #define F0900_P2_DIS_QP_2_3 0xf2bc000f
1489 
1490 /*P2_MODCODLSTD*/
1491 #define R0900_P2_MODCODLSTD 0xf2bd
1492 #define F0900_P2_DIS_QP_3_5 0xf2bd00f0
1493 #define F0900_P2_DIS_QP_1_2 0xf2bd000f
1494 
1495 /*P2_MODCODLSTE*/
1496 #define R0900_P2_MODCODLSTE 0xf2be
1497 #define F0900_P2_DIS_QP_2_5 0xf2be00f0
1498 #define F0900_P2_DIS_QP_1_3 0xf2be000f
1499 
1500 /*P2_MODCODLSTF*/
1501 #define R0900_P2_MODCODLSTF 0xf2bf
1502 #define F0900_P2_DIS_QP_1_4 0xf2bf00f0
1503 
1504 /*P2_GAUSSR0*/
1505 #define R0900_P2_GAUSSR0 0xf2c0
1506 #define F0900_P2_EN_CCIMODE 0xf2c00080
1507 #define F0900_P2_R0_GAUSSIEN 0xf2c0007f
1508 
1509 /*P2_CCIR0*/
1510 #define R0900_P2_CCIR0 0xf2c1
1511 #define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
1512 #define F0900_P2_R0_CCI 0xf2c1007f
1513 
1514 /*P2_CCIQUANT*/
1515 #define R0900_P2_CCIQUANT 0xf2c2
1516 #define F0900_P2_CCI_BETA 0xf2c200e0
1517 #define F0900_P2_CCI_QUANT 0xf2c2001f
1518 
1519 /*P2_CCITHRES*/
1520 #define R0900_P2_CCITHRES 0xf2c3
1521 #define F0900_P2_CCI_THRESHOLD 0xf2c300ff
1522 
1523 /*P2_CCIACC*/
1524 #define R0900_P2_CCIACC 0xf2c4
1525 #define F0900_P2_CCI_VALUE 0xf2c400ff
1526 
1527 /*P2_DMDRESCFG*/
1528 #define R0900_P2_DMDRESCFG 0xf2c6
1529 #define F0900_P2_DMDRES_RESET 0xf2c60080
1530 #define F0900_P2_DMDRES_STRALL 0xf2c60008
1531 #define F0900_P2_DMDRES_NEWONLY 0xf2c60004
1532 #define F0900_P2_DMDRES_NOSTORE 0xf2c60002
1533 
1534 /*P2_DMDRESADR*/
1535 #define R0900_P2_DMDRESADR 0xf2c7
1536 #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
1537 #define F0900_P2_DMDRES_MEMFULL 0xf2c70030
1538 #define F0900_P2_DMDRES_RESNBR 0xf2c7000f
1539 
1540 /*P2_DMDRESDATA7*/
1541 #define R0900_P2_DMDRESDATA7 0xf2c8
1542 #define F0900_P2_DMDRES_DATA7 0xf2c800ff
1543 
1544 /*P2_DMDRESDATA6*/
1545 #define R0900_P2_DMDRESDATA6 0xf2c9
1546 #define F0900_P2_DMDRES_DATA6 0xf2c900ff
1547 
1548 /*P2_DMDRESDATA5*/
1549 #define R0900_P2_DMDRESDATA5 0xf2ca
1550 #define F0900_P2_DMDRES_DATA5 0xf2ca00ff
1551 
1552 /*P2_DMDRESDATA4*/
1553 #define R0900_P2_DMDRESDATA4 0xf2cb
1554 #define F0900_P2_DMDRES_DATA4 0xf2cb00ff
1555 
1556 /*P2_DMDRESDATA3*/
1557 #define R0900_P2_DMDRESDATA3 0xf2cc
1558 #define F0900_P2_DMDRES_DATA3 0xf2cc00ff
1559 
1560 /*P2_DMDRESDATA2*/
1561 #define R0900_P2_DMDRESDATA2 0xf2cd
1562 #define F0900_P2_DMDRES_DATA2 0xf2cd00ff
1563 
1564 /*P2_DMDRESDATA1*/
1565 #define R0900_P2_DMDRESDATA1 0xf2ce
1566 #define F0900_P2_DMDRES_DATA1 0xf2ce00ff
1567 
1568 /*P2_DMDRESDATA0*/
1569 #define R0900_P2_DMDRESDATA0 0xf2cf
1570 #define F0900_P2_DMDRES_DATA0 0xf2cf00ff
1571 
1572 /*P2_FFEI1*/
1573 #define R0900_P2_FFEI1 0xf2d0
1574 #define F0900_P2_FFE_ACCI1 0xf2d001ff
1575 
1576 /*P2_FFEQ1*/
1577 #define R0900_P2_FFEQ1 0xf2d1
1578 #define F0900_P2_FFE_ACCQ1 0xf2d101ff
1579 
1580 /*P2_FFEI2*/
1581 #define R0900_P2_FFEI2 0xf2d2
1582 #define F0900_P2_FFE_ACCI2 0xf2d201ff
1583 
1584 /*P2_FFEQ2*/
1585 #define R0900_P2_FFEQ2 0xf2d3
1586 #define F0900_P2_FFE_ACCQ2 0xf2d301ff
1587 
1588 /*P2_FFEI3*/
1589 #define R0900_P2_FFEI3 0xf2d4
1590 #define F0900_P2_FFE_ACCI3 0xf2d401ff
1591 
1592 /*P2_FFEQ3*/
1593 #define R0900_P2_FFEQ3 0xf2d5
1594 #define F0900_P2_FFE_ACCQ3 0xf2d501ff
1595 
1596 /*P2_FFEI4*/
1597 #define R0900_P2_FFEI4 0xf2d6
1598 #define F0900_P2_FFE_ACCI4 0xf2d601ff
1599 
1600 /*P2_FFEQ4*/
1601 #define R0900_P2_FFEQ4 0xf2d7
1602 #define F0900_P2_FFE_ACCQ4 0xf2d701ff
1603 
1604 /*P2_FFECFG*/
1605 #define R0900_P2_FFECFG 0xf2d8
1606 #define F0900_P2_EQUALFFE_ON 0xf2d80040
1607 #define F0900_P2_MU_EQUALFFE 0xf2d80007
1608 
1609 /*P2_TNRCFG*/
1610 #define R0900_P2_TNRCFG 0xf2e0
1611 #define F0900_P2_TUN_ACKFAIL 0xf2e00080
1612 #define F0900_P2_TUN_TYPE 0xf2e00070
1613 #define F0900_P2_TUN_SECSTOP 0xf2e00008
1614 #define F0900_P2_TUN_VCOSRCH 0xf2e00004
1615 #define F0900_P2_TUN_MADDRESS 0xf2e00003
1616 
1617 /*P2_TNRCFG2*/
1618 #define R0900_P2_TNRCFG2 0xf2e1
1619 #define F0900_P2_TUN_IQSWAP 0xf2e10080
1620 #define F0900_P2_DIS_BWCALC 0xf2e10004
1621 #define F0900_P2_SHORT_WAITSTATES 0xf2e10002
1622 
1623 /*P2_TNRXTAL*/
1624 #define R0900_P2_TNRXTAL 0xf2e4
1625 #define F0900_P2_TUN_XTALFREQ 0xf2e4001f
1626 
1627 /*P2_TNRSTEPS*/
1628 #define R0900_P2_TNRSTEPS 0xf2e7
1629 #define F0900_P2_TUNER_BW0P125 0xf2e70080
1630 #define F0900_P2_BWINC_OFFSET 0xf2e70170
1631 #define F0900_P2_SOFTSTEP_RNG 0xf2e70008
1632 #define F0900_P2_TUN_BWOFFSET 0xf2e70007
1633 
1634 /*P2_TNRGAIN*/
1635 #define R0900_P2_TNRGAIN 0xf2e8
1636 #define F0900_P2_TUN_KDIVEN 0xf2e800c0
1637 #define F0900_P2_STB6X00_OCK 0xf2e80030
1638 #define F0900_P2_TUN_GAIN 0xf2e8000f
1639 
1640 /*P2_TNRRF1*/
1641 #define R0900_P2_TNRRF1 0xf2e9
1642 #define F0900_P2_TUN_RFFREQ2 0xf2e900ff
1643 
1644 /*P2_TNRRF0*/
1645 #define R0900_P2_TNRRF0 0xf2ea
1646 #define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
1647 
1648 /*P2_TNRBW*/
1649 #define R0900_P2_TNRBW 0xf2eb
1650 #define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
1651 #define F0900_P2_TUN_BW 0xf2eb003f
1652 
1653 /*P2_TNRADJ*/
1654 #define R0900_P2_TNRADJ 0xf2ec
1655 #define F0900_P2_STB61X0_CALTIME 0xf2ec0040
1656 
1657 /*P2_TNRCTL2*/
1658 #define R0900_P2_TNRCTL2 0xf2ed
1659 #define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
1660 #define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
1661 #define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
1662 #define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
1663 #define F0900_P2_STB61X0_CALOFF 0xf2ed0008
1664 #define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
1665 #define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
1666 #define F0900_P2_STB6XX0_SYN 0xf2ed0001
1667 
1668 /*P2_TNRCFG3*/
1669 #define R0900_P2_TNRCFG3 0xf2ee
1670 #define F0900_P2_TUN_PLLFREQ 0xf2ee001c
1671 #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
1672 
1673 /*P2_TNRLAUNCH*/
1674 #define R0900_P2_TNRLAUNCH 0xf2f0
1675 
1676 /*P2_TNRLD*/
1677 #define R0900_P2_TNRLD 0xf2f0
1678 #define F0900_P2_TUNLD_VCOING 0xf2f00080
1679 #define F0900_P2_TUN_REG1FAIL 0xf2f00040
1680 #define F0900_P2_TUN_REG2FAIL 0xf2f00020
1681 #define F0900_P2_TUN_REG3FAIL 0xf2f00010
1682 #define F0900_P2_TUN_REG4FAIL 0xf2f00008
1683 #define F0900_P2_TUN_REG5FAIL 0xf2f00004
1684 #define F0900_P2_TUN_BWING 0xf2f00002
1685 #define F0900_P2_TUN_LOCKED 0xf2f00001
1686 
1687 /*P2_TNROBSL*/
1688 #define R0900_P2_TNROBSL 0xf2f6
1689 #define F0900_P2_TUN_I2CABORTED 0xf2f60080
1690 #define F0900_P2_TUN_LPEN 0xf2f60040
1691 #define F0900_P2_TUN_FCCK 0xf2f60020
1692 #define F0900_P2_TUN_I2CLOCKED 0xf2f60010
1693 #define F0900_P2_TUN_PROGDONE 0xf2f6000c
1694 #define F0900_P2_TUN_RFRESTE1 0xf2f60003
1695 
1696 /*P2_TNRRESTE*/
1697 #define R0900_P2_TNRRESTE 0xf2f7
1698 #define F0900_P2_TUN_RFRESTE0 0xf2f700ff
1699 
1700 /*P2_SMAPCOEF7*/
1701 #define R0900_P2_SMAPCOEF7 0xf300
1702 #define F0900_P2_DIS_QSCALE 0xf3000080
1703 #define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
1704 
1705 /*P2_SMAPCOEF6*/
1706 #define R0900_P2_SMAPCOEF6 0xf301
1707 #define F0900_P2_ADJ_8PSKLLR1 0xf3010004
1708 #define F0900_P2_OLD_8PSKLLR1 0xf3010002
1709 #define F0900_P2_DIS_AB8PSK 0xf3010001
1710 
1711 /*P2_SMAPCOEF5*/
1712 #define R0900_P2_SMAPCOEF5 0xf302
1713 #define F0900_P2_DIS_8SCALE 0xf3020080
1714 #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
1715 
1716 /*P2_NCO2MAX1*/
1717 #define R0900_P2_NCO2MAX1 0xf314
1718 #define F0900_P2_TETA2_MAXVABS1 0xf31400ff
1719 
1720 /*P2_NCO2MAX0*/
1721 #define R0900_P2_NCO2MAX0 0xf315
1722 #define F0900_P2_TETA2_MAXVABS0 0xf31500ff
1723 
1724 /*P2_NCO2FR1*/
1725 #define R0900_P2_NCO2FR1 0xf316
1726 #define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
1727 
1728 /*P2_NCO2FR0*/
1729 #define R0900_P2_NCO2FR0 0xf317
1730 #define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
1731 
1732 /*P2_CFR2AVRGE1*/
1733 #define R0900_P2_CFR2AVRGE1 0xf318
1734 #define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
1735 
1736 /*P2_CFR2AVRGE0*/
1737 #define R0900_P2_CFR2AVRGE0 0xf319
1738 #define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
1739 
1740 /*P2_DMDPLHSTAT*/
1741 #define R0900_P2_DMDPLHSTAT 0xf320
1742 #define F0900_P2_PLH_STATISTIC 0xf32000ff
1743 
1744 /*P2_LOCKTIME3*/
1745 #define R0900_P2_LOCKTIME3 0xf322
1746 #define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
1747 
1748 /*P2_LOCKTIME2*/
1749 #define R0900_P2_LOCKTIME2 0xf323
1750 #define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
1751 
1752 /*P2_LOCKTIME1*/
1753 #define R0900_P2_LOCKTIME1 0xf324
1754 #define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
1755 
1756 /*P2_LOCKTIME0*/
1757 #define R0900_P2_LOCKTIME0 0xf325
1758 #define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
1759 
1760 /*P2_VITSCALE*/
1761 #define R0900_P2_VITSCALE 0xf332
1762 #define F0900_P2_NVTH_NOSRANGE 0xf3320080
1763 #define F0900_P2_VERROR_MAXMODE 0xf3320040
1764 #define F0900_P2_NSLOWSN_LOCKED 0xf3320008
1765 #define F0900_P2_DIS_RSFLOCK 0xf3320002
1766 
1767 /*P2_FECM*/
1768 #define R0900_P2_FECM 0xf333
1769 #define F0900_P2_DSS_DVB 0xf3330080
1770 #define F0900_P2_DSS_SRCH 0xf3330010
1771 #define F0900_P2_SYNCVIT 0xf3330002
1772 #define F0900_P2_IQINV 0xf3330001
1773 
1774 /*P2_VTH12*/
1775 #define R0900_P2_VTH12 0xf334
1776 #define F0900_P2_VTH12 0xf33400ff
1777 
1778 /*P2_VTH23*/
1779 #define R0900_P2_VTH23 0xf335
1780 #define F0900_P2_VTH23 0xf33500ff
1781 
1782 /*P2_VTH34*/
1783 #define R0900_P2_VTH34 0xf336
1784 #define F0900_P2_VTH34 0xf33600ff
1785 
1786 /*P2_VTH56*/
1787 #define R0900_P2_VTH56 0xf337
1788 #define F0900_P2_VTH56 0xf33700ff
1789 
1790 /*P2_VTH67*/
1791 #define R0900_P2_VTH67 0xf338
1792 #define F0900_P2_VTH67 0xf33800ff
1793 
1794 /*P2_VTH78*/
1795 #define R0900_P2_VTH78 0xf339
1796 #define F0900_P2_VTH78 0xf33900ff
1797 
1798 /*P2_VITCURPUN*/
1799 #define R0900_P2_VITCURPUN 0xf33a
1800 #define F0900_P2_VIT_CURPUN 0xf33a001f
1801 
1802 /*P2_VERROR*/
1803 #define R0900_P2_VERROR 0xf33b
1804 #define F0900_P2_REGERR_VIT 0xf33b00ff
1805 
1806 /*P2_PRVIT*/
1807 #define R0900_P2_PRVIT 0xf33c
1808 #define F0900_P2_DIS_VTHLOCK 0xf33c0040
1809 #define F0900_P2_E7_8VIT 0xf33c0020
1810 #define F0900_P2_E6_7VIT 0xf33c0010
1811 #define F0900_P2_E5_6VIT 0xf33c0008
1812 #define F0900_P2_E3_4VIT 0xf33c0004
1813 #define F0900_P2_E2_3VIT 0xf33c0002
1814 #define F0900_P2_E1_2VIT 0xf33c0001
1815 
1816 /*P2_VAVSRVIT*/
1817 #define R0900_P2_VAVSRVIT 0xf33d
1818 #define F0900_P2_AMVIT 0xf33d0080
1819 #define F0900_P2_FROZENVIT 0xf33d0040
1820 #define F0900_P2_SNVIT 0xf33d0030
1821 #define F0900_P2_TOVVIT 0xf33d000c
1822 #define F0900_P2_HYPVIT 0xf33d0003
1823 
1824 /*P2_VSTATUSVIT*/
1825 #define R0900_P2_VSTATUSVIT 0xf33e
1826 #define F0900_P2_PRFVIT 0xf33e0010
1827 #define F0900_P2_LOCKEDVIT 0xf33e0008
1828 
1829 /*P2_VTHINUSE*/
1830 #define R0900_P2_VTHINUSE 0xf33f
1831 #define F0900_P2_VIT_INUSE 0xf33f00ff
1832 
1833 /*P2_KDIV12*/
1834 #define R0900_P2_KDIV12 0xf340
1835 #define F0900_P2_K_DIVIDER_12 0xf340007f
1836 
1837 /*P2_KDIV23*/
1838 #define R0900_P2_KDIV23 0xf341
1839 #define F0900_P2_K_DIVIDER_23 0xf341007f
1840 
1841 /*P2_KDIV34*/
1842 #define R0900_P2_KDIV34 0xf342
1843 #define F0900_P2_K_DIVIDER_34 0xf342007f
1844 
1845 /*P2_KDIV56*/
1846 #define R0900_P2_KDIV56 0xf343
1847 #define F0900_P2_K_DIVIDER_56 0xf343007f
1848 
1849 /*P2_KDIV67*/
1850 #define R0900_P2_KDIV67 0xf344
1851 #define F0900_P2_K_DIVIDER_67 0xf344007f
1852 
1853 /*P2_KDIV78*/
1854 #define R0900_P2_KDIV78 0xf345
1855 #define F0900_P2_K_DIVIDER_78 0xf345007f
1856 
1857 /*P2_PDELCTRL1*/
1858 #define R0900_P2_PDELCTRL1 0xf350
1859 #define F0900_P2_INV_MISMASK 0xf3500080
1860 #define F0900_P2_FILTER_EN 0xf3500020
1861 #define F0900_P2_EN_MIS00 0xf3500002
1862 #define F0900_P2_ALGOSWRST 0xf3500001
1863 
1864 /*P2_PDELCTRL2*/
1865 #define R0900_P2_PDELCTRL2 0xf351
1866 #define F0900_P2_RESET_UPKO_COUNT 0xf3510040
1867 #define F0900_P2_FRAME_MODE 0xf3510002
1868 #define F0900_P2_NOBCHERRFLG_USE 0xf3510001
1869 
1870 /*P2_HYSTTHRESH*/
1871 #define R0900_P2_HYSTTHRESH 0xf354
1872 #define F0900_P2_UNLCK_THRESH 0xf35400f0
1873 #define F0900_P2_DELIN_LCK_THRESH 0xf354000f
1874 
1875 /*P2_ISIENTRY*/
1876 #define R0900_P2_ISIENTRY 0xf35e
1877 #define F0900_P2_ISI_ENTRY 0xf35e00ff
1878 
1879 /*P2_ISIBITENA*/
1880 #define R0900_P2_ISIBITENA 0xf35f
1881 #define F0900_P2_ISI_BIT_EN 0xf35f00ff
1882 
1883 /*P2_MATSTR1*/
1884 #define R0900_P2_MATSTR1 0xf360
1885 #define F0900_P2_MATYPE_CURRENT1 0xf36000ff
1886 
1887 /*P2_MATSTR0*/
1888 #define R0900_P2_MATSTR0 0xf361
1889 #define F0900_P2_MATYPE_CURRENT0 0xf36100ff
1890 
1891 /*P2_UPLSTR1*/
1892 #define R0900_P2_UPLSTR1 0xf362
1893 #define F0900_P2_UPL_CURRENT1 0xf36200ff
1894 
1895 /*P2_UPLSTR0*/
1896 #define R0900_P2_UPLSTR0 0xf363
1897 #define F0900_P2_UPL_CURRENT0 0xf36300ff
1898 
1899 /*P2_DFLSTR1*/
1900 #define R0900_P2_DFLSTR1 0xf364
1901 #define F0900_P2_DFL_CURRENT1 0xf36400ff
1902 
1903 /*P2_DFLSTR0*/
1904 #define R0900_P2_DFLSTR0 0xf365
1905 #define F0900_P2_DFL_CURRENT0 0xf36500ff
1906 
1907 /*P2_SYNCSTR*/
1908 #define R0900_P2_SYNCSTR 0xf366
1909 #define F0900_P2_SYNC_CURRENT 0xf36600ff
1910 
1911 /*P2_SYNCDSTR1*/
1912 #define R0900_P2_SYNCDSTR1 0xf367
1913 #define F0900_P2_SYNCD_CURRENT1 0xf36700ff
1914 
1915 /*P2_SYNCDSTR0*/
1916 #define R0900_P2_SYNCDSTR0 0xf368
1917 #define F0900_P2_SYNCD_CURRENT0 0xf36800ff
1918 
1919 /*P2_PDELSTATUS1*/
1920 #define R0900_P2_PDELSTATUS1 0xf369
1921 #define F0900_P2_PKTDELIN_DELOCK 0xf3690080
1922 #define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
1923 #define F0900_P2_CONTINUOUS_STREAM 0xf3690020
1924 #define F0900_P2_UNACCEPTED_STREAM 0xf3690010
1925 #define F0900_P2_BCH_ERROR_FLAG 0xf3690008
1926 #define F0900_P2_PKTDELIN_LOCK 0xf3690002
1927 #define F0900_P2_FIRST_LOCK 0xf3690001
1928 
1929 /*P2_PDELSTATUS2*/
1930 #define R0900_P2_PDELSTATUS2 0xf36a
1931 #define F0900_P2_FRAME_MODCOD 0xf36a007c
1932 #define F0900_P2_FRAME_TYPE 0xf36a0003
1933 
1934 /*P2_BBFCRCKO1*/
1935 #define R0900_P2_BBFCRCKO1 0xf36b
1936 #define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
1937 
1938 /*P2_BBFCRCKO0*/
1939 #define R0900_P2_BBFCRCKO0 0xf36c
1940 #define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
1941 
1942 /*P2_UPCRCKO1*/
1943 #define R0900_P2_UPCRCKO1 0xf36d
1944 #define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
1945 
1946 /*P2_UPCRCKO0*/
1947 #define R0900_P2_UPCRCKO0 0xf36e
1948 #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
1949 
1950 /*P2_PDELCTRL3*/
1951 #define R0900_P2_PDELCTRL3 0xf36f
1952 #define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
1953 #define F0900_P2_NOFIFO_BCHERR 0xf36f0020
1954 
1955 /*P2_TSSTATEM*/
1956 #define R0900_P2_TSSTATEM 0xf370
1957 #define F0900_P2_TSDIL_ON 0xf3700080
1958 #define F0900_P2_TSRS_ON 0xf3700020
1959 #define F0900_P2_TSDESCRAMB_ON 0xf3700010
1960 #define F0900_P2_TSFRAME_MODE 0xf3700008
1961 #define F0900_P2_TS_DISABLE 0xf3700004
1962 #define F0900_P2_TSOUT_NOSYNC 0xf3700001
1963 
1964 /*P2_TSCFGH*/
1965 #define R0900_P2_TSCFGH 0xf372
1966 #define F0900_P2_TSFIFO_DVBCI 0xf3720080
1967 #define F0900_P2_TSFIFO_SERIAL 0xf3720040
1968 #define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
1969 #define F0900_P2_TSFIFO_DUTY50 0xf3720010
1970 #define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
1971 #define F0900_P2_TSFIFO_ERRMODE 0xf3720006
1972 #define F0900_P2_RST_HWARE 0xf3720001
1973 
1974 /*P2_TSCFGM*/
1975 #define R0900_P2_TSCFGM 0xf373
1976 #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
1977 #define F0900_P2_TSFIFO_PERMDATA 0xf3730020
1978 #define F0900_P2_TSFIFO_DPUNACT 0xf3730002
1979 #define F0900_P2_TSFIFO_INVDATA 0xf3730001
1980 
1981 /*P2_TSCFGL*/
1982 #define R0900_P2_TSCFGL 0xf374
1983 #define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
1984 #define F0900_P2_BCHERROR_MODE 0xf3740030
1985 #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
1986 #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
1987 #define F0900_P2_TSFIFO_BITSPEED 0xf3740003
1988 
1989 /*P2_TSINSDELH*/
1990 #define R0900_P2_TSINSDELH 0xf376
1991 #define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
1992 #define F0900_P2_TSDEL_XXHEADER 0xf3760040
1993 #define F0900_P2_TSDEL_BBHEADER 0xf3760020
1994 #define F0900_P2_TSDEL_DATAFIELD 0xf3760010
1995 #define F0900_P2_TSINSDEL_ISCR 0xf3760008
1996 #define F0900_P2_TSINSDEL_NPD 0xf3760004
1997 #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
1998 #define F0900_P2_TSINSDEL_CRC8 0xf3760001
1999 
2000 /*P2_TSDIVN*/
2001 #define R0900_P2_TSDIVN 0xf379
2002 #define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
2003 
2004 /*P2_TSCFG4*/
2005 #define R0900_P2_TSCFG4 0xf37a
2006 #define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
2007 
2008 /*P2_TSSPEED*/
2009 #define R0900_P2_TSSPEED 0xf380
2010 #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
2011 
2012 /*P2_TSSTATUS*/
2013 #define R0900_P2_TSSTATUS 0xf381
2014 #define F0900_P2_TSFIFO_LINEOK 0xf3810080
2015 #define F0900_P2_TSFIFO_ERROR 0xf3810040
2016 #define F0900_P2_DIL_READY 0xf3810001
2017 
2018 /*P2_TSSTATUS2*/
2019 #define R0900_P2_TSSTATUS2 0xf382
2020 #define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
2021 #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
2022 #define F0900_P2_DILXX_RESET 0xf3820020
2023 #define F0900_P2_TSSERIAL_IMPOS 0xf3820010
2024 #define F0900_P2_SCRAMBDETECT 0xf3820002
2025 
2026 /*P2_TSBITRATE1*/
2027 #define R0900_P2_TSBITRATE1 0xf383
2028 #define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
2029 
2030 /*P2_TSBITRATE0*/
2031 #define R0900_P2_TSBITRATE0 0xf384
2032 #define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
2033 
2034 /*P2_ERRCTRL1*/
2035 #define R0900_P2_ERRCTRL1 0xf398
2036 #define F0900_P2_ERR_SOURCE1 0xf39800f0
2037 #define F0900_P2_NUM_EVENT1 0xf3980007
2038 
2039 /*P2_ERRCNT12*/
2040 #define R0900_P2_ERRCNT12 0xf399
2041 #define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
2042 #define F0900_P2_ERR_CNT12 0xf399007f
2043 
2044 /*P2_ERRCNT11*/
2045 #define R0900_P2_ERRCNT11 0xf39a
2046 #define F0900_P2_ERR_CNT11 0xf39a00ff
2047 
2048 /*P2_ERRCNT10*/
2049 #define R0900_P2_ERRCNT10 0xf39b
2050 #define F0900_P2_ERR_CNT10 0xf39b00ff
2051 
2052 /*P2_ERRCTRL2*/
2053 #define R0900_P2_ERRCTRL2 0xf39c
2054 #define F0900_P2_ERR_SOURCE2 0xf39c00f0
2055 #define F0900_P2_NUM_EVENT2 0xf39c0007
2056 
2057 /*P2_ERRCNT22*/
2058 #define R0900_P2_ERRCNT22 0xf39d
2059 #define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
2060 #define F0900_P2_ERR_CNT22 0xf39d007f
2061 
2062 /*P2_ERRCNT21*/
2063 #define R0900_P2_ERRCNT21 0xf39e
2064 #define F0900_P2_ERR_CNT21 0xf39e00ff
2065 
2066 /*P2_ERRCNT20*/
2067 #define R0900_P2_ERRCNT20 0xf39f
2068 #define F0900_P2_ERR_CNT20 0xf39f00ff
2069 
2070 /*P2_FECSPY*/
2071 #define R0900_P2_FECSPY 0xf3a0
2072 #define F0900_P2_SPY_ENABLE 0xf3a00080
2073 #define F0900_P2_NO_SYNCBYTE 0xf3a00040
2074 #define F0900_P2_SERIAL_MODE 0xf3a00020
2075 #define F0900_P2_UNUSUAL_PACKET 0xf3a00010
2076 #define F0900_P2_BERMETER_DATAMODE 0xf3a00008
2077 #define F0900_P2_BERMETER_LMODE 0xf3a00002
2078 #define F0900_P2_BERMETER_RESET 0xf3a00001
2079 
2080 /*P2_FSPYCFG*/
2081 #define R0900_P2_FSPYCFG 0xf3a1
2082 #define F0900_P2_FECSPY_INPUT 0xf3a100c0
2083 #define F0900_P2_RST_ON_ERROR 0xf3a10020
2084 #define F0900_P2_ONE_SHOT 0xf3a10010
2085 #define F0900_P2_I2C_MODE 0xf3a1000c
2086 #define F0900_P2_SPY_HYSTERESIS 0xf3a10003
2087 
2088 /*P2_FSPYDATA*/
2089 #define R0900_P2_FSPYDATA 0xf3a2
2090 #define F0900_P2_SPY_STUFFING 0xf3a20080
2091 #define F0900_P2_SPY_CNULLPKT 0xf3a20020
2092 #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
2093 
2094 /*P2_FSPYOUT*/
2095 #define R0900_P2_FSPYOUT 0xf3a3
2096 #define F0900_P2_FSPY_DIRECT 0xf3a30080
2097 #define F0900_P2_STUFF_MODE 0xf3a30007
2098 
2099 /*P2_FSTATUS*/
2100 #define R0900_P2_FSTATUS 0xf3a4
2101 #define F0900_P2_SPY_ENDSIM 0xf3a40080
2102 #define F0900_P2_VALID_SIM 0xf3a40040
2103 #define F0900_P2_FOUND_SIGNAL 0xf3a40020
2104 #define F0900_P2_DSS_SYNCBYTE 0xf3a40010
2105 #define F0900_P2_RESULT_STATE 0xf3a4000f
2106 
2107 /*P2_FBERCPT4*/
2108 #define R0900_P2_FBERCPT4 0xf3a8
2109 #define F0900_P2_FBERMETER_CPT4 0xf3a800ff
2110 
2111 /*P2_FBERCPT3*/
2112 #define R0900_P2_FBERCPT3 0xf3a9
2113 #define F0900_P2_FBERMETER_CPT3 0xf3a900ff
2114 
2115 /*P2_FBERCPT2*/
2116 #define R0900_P2_FBERCPT2 0xf3aa
2117 #define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
2118 
2119 /*P2_FBERCPT1*/
2120 #define R0900_P2_FBERCPT1 0xf3ab
2121 #define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
2122 
2123 /*P2_FBERCPT0*/
2124 #define R0900_P2_FBERCPT0 0xf3ac
2125 #define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
2126 
2127 /*P2_FBERERR2*/
2128 #define R0900_P2_FBERERR2 0xf3ad
2129 #define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
2130 
2131 /*P2_FBERERR1*/
2132 #define R0900_P2_FBERERR1 0xf3ae
2133 #define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
2134 
2135 /*P2_FBERERR0*/
2136 #define R0900_P2_FBERERR0 0xf3af
2137 #define F0900_P2_FBERMETER_ERR0 0xf3af00ff
2138 
2139 /*P2_FSPYBER*/
2140 #define R0900_P2_FSPYBER 0xf3b2
2141 #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
2142 #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
2143 #define F0900_P2_FSPYBER_CTIME 0xf3b20007
2144 
2145 /*P1_IQCONST*/
2146 #define R0900_P1_IQCONST 0xf400
2147 #define IQCONST REGx(R0900_P1_IQCONST)
2148 #define F0900_P1_CONSTEL_SELECT 0xf4000060
2149 #define F0900_P1_IQSYMB_SEL 0xf400001f
2150 
2151 /*P1_NOSCFG*/
2152 #define R0900_P1_NOSCFG 0xf401
2153 #define NOSCFG REGx(R0900_P1_NOSCFG)
2154 #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
2155 #define F0900_P1_NOSPLH_BETA 0xf4010018
2156 #define F0900_P1_NOSDATA_BETA 0xf4010007
2157 
2158 /*P1_ISYMB*/
2159 #define R0900_P1_ISYMB 0xf402
2160 #define ISYMB REGx(R0900_P1_ISYMB)
2161 #define F0900_P1_I_SYMBOL 0xf40201ff
2162 
2163 /*P1_QSYMB*/
2164 #define R0900_P1_QSYMB 0xf403
2165 #define QSYMB REGx(R0900_P1_QSYMB)
2166 #define F0900_P1_Q_SYMBOL 0xf40301ff
2167 
2168 /*P1_AGC1CFG*/
2169 #define R0900_P1_AGC1CFG 0xf404
2170 #define AGC1CFG REGx(R0900_P1_AGC1CFG)
2171 #define F0900_P1_DC_FROZEN 0xf4040080
2172 #define F0900_P1_DC_CORRECT 0xf4040040
2173 #define F0900_P1_AMM_FROZEN 0xf4040020
2174 #define F0900_P1_AMM_CORRECT 0xf4040010
2175 #define F0900_P1_QUAD_FROZEN 0xf4040008
2176 #define F0900_P1_QUAD_CORRECT 0xf4040004
2177 
2178 /*P1_AGC1CN*/
2179 #define R0900_P1_AGC1CN 0xf406
2180 #define AGC1CN REGx(R0900_P1_AGC1CN)
2181 #define F0900_P1_AGC1_LOCKED 0xf4060080
2182 #define F0900_P1_AGC1_MINPOWER 0xf4060010
2183 #define F0900_P1_AGCOUT_FAST 0xf4060008
2184 #define F0900_P1_AGCIQ_BETA 0xf4060007
2185 
2186 /*P1_AGC1REF*/
2187 #define R0900_P1_AGC1REF 0xf407
2188 #define AGC1REF REGx(R0900_P1_AGC1REF)
2189 #define F0900_P1_AGCIQ_REF 0xf40700ff
2190 
2191 /*P1_IDCCOMP*/
2192 #define R0900_P1_IDCCOMP 0xf408
2193 #define IDCCOMP REGx(R0900_P1_IDCCOMP)
2194 #define F0900_P1_IAVERAGE_ADJ 0xf40801ff
2195 
2196 /*P1_QDCCOMP*/
2197 #define R0900_P1_QDCCOMP 0xf409
2198 #define QDCCOMP REGx(R0900_P1_QDCCOMP)
2199 #define F0900_P1_QAVERAGE_ADJ 0xf40901ff
2200 
2201 /*P1_POWERI*/
2202 #define R0900_P1_POWERI 0xf40a
2203 #define POWERI REGx(R0900_P1_POWERI)
2204 #define F0900_P1_POWER_I 0xf40a00ff
2205 #define POWER_I FLDx(F0900_P1_POWER_I)
2206 
2207 /*P1_POWERQ*/
2208 #define R0900_P1_POWERQ 0xf40b
2209 #define POWERQ REGx(R0900_P1_POWERQ)
2210 #define F0900_P1_POWER_Q 0xf40b00ff
2211 #define POWER_Q FLDx(F0900_P1_POWER_Q)
2212 
2213 /*P1_AGC1AMM*/
2214 #define R0900_P1_AGC1AMM 0xf40c
2215 #define AGC1AMM REGx(R0900_P1_AGC1AMM)
2216 #define F0900_P1_AMM_VALUE 0xf40c00ff
2217 
2218 /*P1_AGC1QUAD*/
2219 #define R0900_P1_AGC1QUAD 0xf40d
2220 #define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
2221 #define F0900_P1_QUAD_VALUE 0xf40d01ff
2222 
2223 /*P1_AGCIQIN1*/
2224 #define R0900_P1_AGCIQIN1 0xf40e
2225 #define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
2226 #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
2227 #define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
2228 
2229 /*P1_AGCIQIN0*/
2230 #define R0900_P1_AGCIQIN0 0xf40f
2231 #define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
2232 #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
2233 #define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
2234 
2235 /*P1_DEMOD*/
2236 #define R0900_P1_DEMOD 0xf410
2237 #define DEMOD REGx(R0900_P1_DEMOD)
2238 #define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
2239 #define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
2240 
2241 #define F0900_P1_SPECINV_CONTROL 0xf4100030
2242 #define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
2243 #define F0900_P1_FORCE_ENASAMP 0xf4100008
2244 #define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
2245 #define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
2246 #define F0900_P1_ROLLOFF_CONTROL 0xf4100003
2247 #define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
2248 
2249 /*P1_DMDMODCOD*/
2250 #define R0900_P1_DMDMODCOD 0xf411
2251 #define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
2252 #define F0900_P1_MANUAL_MODCOD 0xf4110080
2253 #define F0900_P1_DEMOD_MODCOD 0xf411007c
2254 #define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
2255 #define F0900_P1_DEMOD_TYPE 0xf4110003
2256 #define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
2257 
2258 /*P1_DSTATUS*/
2259 #define R0900_P1_DSTATUS 0xf412
2260 #define DSTATUS REGx(R0900_P1_DSTATUS)
2261 #define F0900_P1_CAR_LOCK 0xf4120080
2262 #define F0900_P1_TMGLOCK_QUALITY 0xf4120060
2263 #define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
2264 #define F0900_P1_LOCK_DEFINITIF 0xf4120008
2265 #define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
2266 #define F0900_P1_OVADC_DETECT 0xf4120001
2267 
2268 /*P1_DSTATUS2*/
2269 #define R0900_P1_DSTATUS2 0xf413
2270 #define DSTATUS2 REGx(R0900_P1_DSTATUS2)
2271 #define F0900_P1_DEMOD_DELOCK 0xf4130080
2272 #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
2273 #define F0900_P1_AGC2_OVERFLOW 0xf4130004
2274 #define F0900_P1_CFR_OVERFLOW 0xf4130002
2275 #define F0900_P1_GAMMA_OVERUNDER 0xf4130001
2276 
2277 /*P1_DMDCFGMD*/
2278 #define R0900_P1_DMDCFGMD 0xf414
2279 #define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
2280 #define F0900_P1_DVBS2_ENABLE 0xf4140080
2281 #define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
2282 #define F0900_P1_DVBS1_ENABLE 0xf4140040
2283 #define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
2284 #define F0900_P1_SCAN_ENABLE 0xf4140010
2285 #define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
2286 #define F0900_P1_CFR_AUTOSCAN 0xf4140008
2287 #define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
2288 #define F0900_P1_TUN_RNG 0xf4140003
2289 
2290 /*P1_DMDCFG2*/
2291 #define R0900_P1_DMDCFG2 0xf415
2292 #define DMDCFG2 REGx(R0900_P1_DMDCFG2)
2293 #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
2294 #define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
2295 #define F0900_P1_INFINITE_RELOCK 0xf4150010
2296 
2297 /*P1_DMDISTATE*/
2298 #define R0900_P1_DMDISTATE 0xf416
2299 #define DMDISTATE REGx(R0900_P1_DMDISTATE)
2300 #define F0900_P1_I2C_DEMOD_MODE 0xf416001f
2301 #define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
2302 
2303 /*P1_DMDT0M*/
2304 #define R0900_P1_DMDT0M 0xf417
2305 #define DMDT0M REGx(R0900_P1_DMDT0M)
2306 #define F0900_P1_DMDT0_MIN 0xf41700ff
2307 
2308 /*P1_DMDSTATE*/
2309 #define R0900_P1_DMDSTATE 0xf41b
2310 #define DMDSTATE REGx(R0900_P1_DMDSTATE)
2311 #define F0900_P1_HEADER_MODE 0xf41b0060
2312 #define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
2313 
2314 /*P1_DMDFLYW*/
2315 #define R0900_P1_DMDFLYW 0xf41c
2316 #define DMDFLYW REGx(R0900_P1_DMDFLYW)
2317 #define F0900_P1_I2C_IRQVAL 0xf41c00f0
2318 #define F0900_P1_FLYWHEEL_CPT 0xf41c000f
2319 #define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
2320 
2321 /*P1_DSTATUS3*/
2322 #define R0900_P1_DSTATUS3 0xf41d
2323 #define DSTATUS3 REGx(R0900_P1_DSTATUS3)
2324 #define F0900_P1_DEMOD_CFGMODE 0xf41d0060
2325 
2326 /*P1_DMDCFG3*/
2327 #define R0900_P1_DMDCFG3 0xf41e
2328 #define DMDCFG3 REGx(R0900_P1_DMDCFG3)
2329 #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
2330 
2331 /*P1_DMDCFG4*/
2332 #define R0900_P1_DMDCFG4 0xf41f
2333 #define DMDCFG4 REGx(R0900_P1_DMDCFG4)
2334 #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
2335 
2336 /*P1_CORRELMANT*/
2337 #define R0900_P1_CORRELMANT 0xf420
2338 #define CORRELMANT REGx(R0900_P1_CORRELMANT)
2339 #define F0900_P1_CORREL_MANT 0xf42000ff
2340 
2341 /*P1_CORRELABS*/
2342 #define R0900_P1_CORRELABS 0xf421
2343 #define CORRELABS REGx(R0900_P1_CORRELABS)
2344 #define F0900_P1_CORREL_ABS 0xf42100ff
2345 
2346 /*P1_CORRELEXP*/
2347 #define R0900_P1_CORRELEXP 0xf422
2348 #define CORRELEXP REGx(R0900_P1_CORRELEXP)
2349 #define F0900_P1_CORREL_ABSEXP 0xf42200f0
2350 #define F0900_P1_CORREL_EXP 0xf422000f
2351 
2352 /*P1_PLHMODCOD*/
2353 #define R0900_P1_PLHMODCOD 0xf424
2354 #define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
2355 #define F0900_P1_SPECINV_DEMOD 0xf4240080
2356 #define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
2357 #define F0900_P1_PLH_MODCOD 0xf424007c
2358 #define F0900_P1_PLH_TYPE 0xf4240003
2359 
2360 /*P1_DMDREG*/
2361 #define R0900_P1_DMDREG 0xf425
2362 #define DMDREG REGx(R0900_P1_DMDREG)
2363 #define F0900_P1_DECIM_PLFRAMES 0xf4250001
2364 
2365 /*P1_AGC2O*/
2366 #define R0900_P1_AGC2O 0xf42c
2367 #define AGC2O REGx(R0900_P1_AGC2O)
2368 #define F0900_P1_AGC2_COEF 0xf42c0007
2369 
2370 /*P1_AGC2REF*/
2371 #define R0900_P1_AGC2REF 0xf42d
2372 #define AGC2REF REGx(R0900_P1_AGC2REF)
2373 #define F0900_P1_AGC2_REF 0xf42d00ff
2374 
2375 /*P1_AGC1ADJ*/
2376 #define R0900_P1_AGC1ADJ 0xf42e
2377 #define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
2378 #define F0900_P1_AGC1_ADJUSTED 0xf42e007f
2379 
2380 /*P1_AGC2I1*/
2381 #define R0900_P1_AGC2I1 0xf436
2382 #define AGC2I1 REGx(R0900_P1_AGC2I1)
2383 #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
2384 
2385 /*P1_AGC2I0*/
2386 #define R0900_P1_AGC2I0 0xf437
2387 #define AGC2I0 REGx(R0900_P1_AGC2I0)
2388 #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
2389 
2390 /*P1_CARCFG*/
2391 #define R0900_P1_CARCFG 0xf438
2392 #define CARCFG REGx(R0900_P1_CARCFG)
2393 #define F0900_P1_CFRUPLOW_AUTO 0xf4380080
2394 #define F0900_P1_CFRUPLOW_TEST 0xf4380040
2395 #define F0900_P1_ROTAON 0xf4380004
2396 #define F0900_P1_PH_DET_ALGO 0xf4380003
2397 
2398 /*P1_ACLC*/
2399 #define R0900_P1_ACLC 0xf439
2400 #define ACLC REGx(R0900_P1_ACLC)
2401 #define F0900_P1_CAR_ALPHA_MANT 0xf4390030
2402 #define F0900_P1_CAR_ALPHA_EXP 0xf439000f
2403 
2404 /*P1_BCLC*/
2405 #define R0900_P1_BCLC 0xf43a
2406 #define BCLC REGx(R0900_P1_BCLC)
2407 #define F0900_P1_CAR_BETA_MANT 0xf43a0030
2408 #define F0900_P1_CAR_BETA_EXP 0xf43a000f
2409 
2410 /*P1_CARFREQ*/
2411 #define R0900_P1_CARFREQ 0xf43d
2412 #define CARFREQ REGx(R0900_P1_CARFREQ)
2413 #define F0900_P1_KC_COARSE_EXP 0xf43d00f0
2414 #define F0900_P1_BETA_FREQ 0xf43d000f
2415 
2416 /*P1_CARHDR*/
2417 #define R0900_P1_CARHDR 0xf43e
2418 #define CARHDR REGx(R0900_P1_CARHDR)
2419 #define F0900_P1_K_FREQ_HDR 0xf43e00ff
2420 
2421 /*P1_LDT*/
2422 #define R0900_P1_LDT 0xf43f
2423 #define LDT REGx(R0900_P1_LDT)
2424 #define F0900_P1_CARLOCK_THRES 0xf43f01ff
2425 
2426 /*P1_LDT2*/
2427 #define R0900_P1_LDT2 0xf440
2428 #define LDT2 REGx(R0900_P1_LDT2)
2429 #define F0900_P1_CARLOCK_THRES2 0xf44001ff
2430 
2431 /*P1_CFRICFG*/
2432 #define R0900_P1_CFRICFG 0xf441
2433 #define CFRICFG REGx(R0900_P1_CFRICFG)
2434 #define F0900_P1_NEG_CFRSTEP 0xf4410001
2435 
2436 /*P1_CFRUP1*/
2437 #define R0900_P1_CFRUP1 0xf442
2438 #define CFRUP1 REGx(R0900_P1_CFRUP1)
2439 #define F0900_P1_CFR_UP1 0xf44201ff
2440 #define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
2441 
2442 /*P1_CFRUP0*/
2443 #define R0900_P1_CFRUP0 0xf443
2444 #define CFRUP0 REGx(R0900_P1_CFRUP0)
2445 #define F0900_P1_CFR_UP0 0xf44300ff
2446 #define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
2447 
2448 /*P1_CFRLOW1*/
2449 #define R0900_P1_CFRLOW1 0xf446
2450 #define CFRLOW1 REGx(R0900_P1_CFRLOW1)
2451 #define F0900_P1_CFR_LOW1 0xf44601ff
2452 #define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
2453 
2454 /*P1_CFRLOW0*/
2455 #define R0900_P1_CFRLOW0 0xf447
2456 #define CFRLOW0 REGx(R0900_P1_CFRLOW0)
2457 #define F0900_P1_CFR_LOW0 0xf44700ff
2458 #define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
2459 
2460 /*P1_CFRINIT1*/
2461 #define R0900_P1_CFRINIT1 0xf448
2462 #define CFRINIT1 REGx(R0900_P1_CFRINIT1)
2463 #define F0900_P1_CFR_INIT1 0xf44801ff
2464 #define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
2465 
2466 /*P1_CFRINIT0*/
2467 #define R0900_P1_CFRINIT0 0xf449
2468 #define CFRINIT0 REGx(R0900_P1_CFRINIT0)
2469 #define F0900_P1_CFR_INIT0 0xf44900ff
2470 #define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
2471 
2472 /*P1_CFRINC1*/
2473 #define R0900_P1_CFRINC1 0xf44a
2474 #define CFRINC1 REGx(R0900_P1_CFRINC1)
2475 #define F0900_P1_MANUAL_CFRINC 0xf44a0080
2476 #define F0900_P1_CFR_INC1 0xf44a003f
2477 
2478 /*P1_CFRINC0*/
2479 #define R0900_P1_CFRINC0 0xf44b
2480 #define CFRINC0 REGx(R0900_P1_CFRINC0)
2481 #define F0900_P1_CFR_INC0 0xf44b00f8
2482 
2483 /*P1_CFR2*/
2484 #define R0900_P1_CFR2 0xf44c
2485 #define CFR2 REGx(R0900_P1_CFR2)
2486 #define F0900_P1_CAR_FREQ2 0xf44c01ff
2487 #define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
2488 
2489 /*P1_CFR1*/
2490 #define R0900_P1_CFR1 0xf44d
2491 #define CFR1 REGx(R0900_P1_CFR1)
2492 #define F0900_P1_CAR_FREQ1 0xf44d00ff
2493 #define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
2494 
2495 /*P1_CFR0*/
2496 #define R0900_P1_CFR0 0xf44e
2497 #define CFR0 REGx(R0900_P1_CFR0)
2498 #define F0900_P1_CAR_FREQ0 0xf44e00ff
2499 #define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
2500 
2501 /*P1_LDI*/
2502 #define R0900_P1_LDI 0xf44f
2503 #define LDI REGx(R0900_P1_LDI)
2504 #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
2505 
2506 /*P1_TMGCFG*/
2507 #define R0900_P1_TMGCFG 0xf450
2508 #define TMGCFG REGx(R0900_P1_TMGCFG)
2509 #define F0900_P1_TMGLOCK_BETA 0xf45000c0
2510 #define F0900_P1_DO_TIMING_CORR 0xf4500010
2511 #define F0900_P1_TMG_MINFREQ 0xf4500003
2512 
2513 /*P1_RTC*/
2514 #define R0900_P1_RTC 0xf451
2515 #define RTC REGx(R0900_P1_RTC)
2516 #define F0900_P1_TMGALPHA_EXP 0xf45100f0
2517 #define F0900_P1_TMGBETA_EXP 0xf451000f
2518 
2519 /*P1_RTCS2*/
2520 #define R0900_P1_RTCS2 0xf452
2521 #define RTCS2 REGx(R0900_P1_RTCS2)
2522 #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
2523 #define F0900_P1_TMGBETAS2_EXP 0xf452000f
2524 
2525 /*P1_TMGTHRISE*/
2526 #define R0900_P1_TMGTHRISE 0xf453
2527 #define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
2528 #define F0900_P1_TMGLOCK_THRISE 0xf45300ff
2529 
2530 /*P1_TMGTHFALL*/
2531 #define R0900_P1_TMGTHFALL 0xf454
2532 #define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
2533 #define F0900_P1_TMGLOCK_THFALL 0xf45400ff
2534 
2535 /*P1_SFRUPRATIO*/
2536 #define R0900_P1_SFRUPRATIO 0xf455
2537 #define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
2538 #define F0900_P1_SFR_UPRATIO 0xf45500ff
2539 
2540 /*P1_SFRLOWRATIO*/
2541 #define R0900_P1_SFRLOWRATIO 0xf456
2542 #define F0900_P1_SFR_LOWRATIO 0xf45600ff
2543 
2544 /*P1_KREFTMG*/
2545 #define R0900_P1_KREFTMG 0xf458
2546 #define KREFTMG REGx(R0900_P1_KREFTMG)
2547 #define F0900_P1_KREF_TMG 0xf45800ff
2548 
2549 /*P1_SFRSTEP*/
2550 #define R0900_P1_SFRSTEP 0xf459
2551 #define SFRSTEP REGx(R0900_P1_SFRSTEP)
2552 #define F0900_P1_SFR_SCANSTEP 0xf45900f0
2553 #define F0900_P1_SFR_CENTERSTEP 0xf459000f
2554 
2555 /*P1_TMGCFG2*/
2556 #define R0900_P1_TMGCFG2 0xf45a
2557 #define TMGCFG2 REGx(R0900_P1_TMGCFG2)
2558 #define F0900_P1_SFRRATIO_FINE 0xf45a0001
2559 
2560 /*P1_KREFTMG2*/
2561 #define R0900_P1_KREFTMG2 0xf45b
2562 #define KREFTMG2 REGx(R0900_P1_KREFTMG2)
2563 #define F0900_P1_KREF_TMG2 0xf45b00ff
2564 
2565 /*P1_SFRINIT1*/
2566 #define R0900_P1_SFRINIT1 0xf45e
2567 #define SFRINIT1 REGx(R0900_P1_SFRINIT1)
2568 #define F0900_P1_SFR_INIT1 0xf45e007f
2569 
2570 /*P1_SFRINIT0*/
2571 #define R0900_P1_SFRINIT0 0xf45f
2572 #define SFRINIT0 REGx(R0900_P1_SFRINIT0)
2573 #define F0900_P1_SFR_INIT0 0xf45f00ff
2574 
2575 /*P1_SFRUP1*/
2576 #define R0900_P1_SFRUP1 0xf460
2577 #define SFRUP1 REGx(R0900_P1_SFRUP1)
2578 #define F0900_P1_AUTO_GUP 0xf4600080
2579 #define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
2580 #define F0900_P1_SYMB_FREQ_UP1 0xf460007f
2581 
2582 /*P1_SFRUP0*/
2583 #define R0900_P1_SFRUP0 0xf461
2584 #define SFRUP0 REGx(R0900_P1_SFRUP0)
2585 #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
2586 
2587 /*P1_SFRLOW1*/
2588 #define R0900_P1_SFRLOW1 0xf462
2589 #define SFRLOW1 REGx(R0900_P1_SFRLOW1)
2590 #define F0900_P1_AUTO_GLOW 0xf4620080
2591 #define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
2592 #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
2593 
2594 /*P1_SFRLOW0*/
2595 #define R0900_P1_SFRLOW0 0xf463
2596 #define SFRLOW0 REGx(R0900_P1_SFRLOW0)
2597 #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
2598 
2599 /*P1_SFR3*/
2600 #define R0900_P1_SFR3 0xf464
2601 #define SFR3 REGx(R0900_P1_SFR3)
2602 #define F0900_P1_SYMB_FREQ3 0xf46400ff
2603 #define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
2604 
2605 /*P1_SFR2*/
2606 #define R0900_P1_SFR2 0xf465
2607 #define SFR2 REGx(R0900_P1_SFR2)
2608 #define F0900_P1_SYMB_FREQ2 0xf46500ff
2609 #define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
2610 
2611 /*P1_SFR1*/
2612 #define R0900_P1_SFR1 0xf466
2613 #define SFR1 REGx(R0900_P1_SFR1)
2614 #define F0900_P1_SYMB_FREQ1 0xf46600ff
2615 #define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
2616 
2617 /*P1_SFR0*/
2618 #define R0900_P1_SFR0 0xf467
2619 #define SFR0 REGx(R0900_P1_SFR0)
2620 #define F0900_P1_SYMB_FREQ0 0xf46700ff
2621 #define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
2622 
2623 /*P1_TMGREG2*/
2624 #define R0900_P1_TMGREG2 0xf468
2625 #define TMGREG2 REGx(R0900_P1_TMGREG2)
2626 #define F0900_P1_TMGREG2 0xf46800ff
2627 
2628 /*P1_TMGREG1*/
2629 #define R0900_P1_TMGREG1 0xf469
2630 #define TMGREG1 REGx(R0900_P1_TMGREG1)
2631 #define F0900_P1_TMGREG1 0xf46900ff
2632 
2633 /*P1_TMGREG0*/
2634 #define R0900_P1_TMGREG0 0xf46a
2635 #define TMGREG0 REGx(R0900_P1_TMGREG0)
2636 #define F0900_P1_TMGREG0 0xf46a00ff
2637 
2638 /*P1_TMGLOCK1*/
2639 #define R0900_P1_TMGLOCK1 0xf46b
2640 #define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
2641 #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
2642 
2643 /*P1_TMGLOCK0*/
2644 #define R0900_P1_TMGLOCK0 0xf46c
2645 #define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
2646 #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
2647 
2648 /*P1_TMGOBS*/
2649 #define R0900_P1_TMGOBS 0xf46d
2650 #define TMGOBS REGx(R0900_P1_TMGOBS)
2651 #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
2652 #define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
2653 
2654 /*P1_EQUALCFG*/
2655 #define R0900_P1_EQUALCFG 0xf46f
2656 #define EQUALCFG REGx(R0900_P1_EQUALCFG)
2657 #define F0900_P1_EQUAL_ON 0xf46f0040
2658 #define F0900_P1_MU_EQUALDFE 0xf46f0007
2659 
2660 /*P1_EQUAI1*/
2661 #define R0900_P1_EQUAI1 0xf470
2662 #define EQUAI1 REGx(R0900_P1_EQUAI1)
2663 #define F0900_P1_EQUA_ACCI1 0xf47001ff
2664 
2665 /*P1_EQUAQ1*/
2666 #define R0900_P1_EQUAQ1 0xf471
2667 #define EQUAQ1 REGx(R0900_P1_EQUAQ1)
2668 #define F0900_P1_EQUA_ACCQ1 0xf47101ff
2669 
2670 /*P1_EQUAI2*/
2671 #define R0900_P1_EQUAI2 0xf472
2672 #define EQUAI2 REGx(R0900_P1_EQUAI2)
2673 #define F0900_P1_EQUA_ACCI2 0xf47201ff
2674 
2675 /*P1_EQUAQ2*/
2676 #define R0900_P1_EQUAQ2 0xf473
2677 #define EQUAQ2 REGx(R0900_P1_EQUAQ2)
2678 #define F0900_P1_EQUA_ACCQ2 0xf47301ff
2679 
2680 /*P1_EQUAI3*/
2681 #define R0900_P1_EQUAI3 0xf474
2682 #define EQUAI3 REGx(R0900_P1_EQUAI3)
2683 #define F0900_P1_EQUA_ACCI3 0xf47401ff
2684 
2685 /*P1_EQUAQ3*/
2686 #define R0900_P1_EQUAQ3 0xf475
2687 #define EQUAQ3 REGx(R0900_P1_EQUAQ3)
2688 #define F0900_P1_EQUA_ACCQ3 0xf47501ff
2689 
2690 /*P1_EQUAI4*/
2691 #define R0900_P1_EQUAI4 0xf476
2692 #define EQUAI4 REGx(R0900_P1_EQUAI4)
2693 #define F0900_P1_EQUA_ACCI4 0xf47601ff
2694 
2695 /*P1_EQUAQ4*/
2696 #define R0900_P1_EQUAQ4 0xf477
2697 #define EQUAQ4 REGx(R0900_P1_EQUAQ4)
2698 #define F0900_P1_EQUA_ACCQ4 0xf47701ff
2699 
2700 /*P1_EQUAI5*/
2701 #define R0900_P1_EQUAI5 0xf478
2702 #define EQUAI5 REGx(R0900_P1_EQUAI5)
2703 #define F0900_P1_EQUA_ACCI5 0xf47801ff
2704 
2705 /*P1_EQUAQ5*/
2706 #define R0900_P1_EQUAQ5 0xf479
2707 #define EQUAQ5 REGx(R0900_P1_EQUAQ5)
2708 #define F0900_P1_EQUA_ACCQ5 0xf47901ff
2709 
2710 /*P1_EQUAI6*/
2711 #define R0900_P1_EQUAI6 0xf47a
2712 #define EQUAI6 REGx(R0900_P1_EQUAI6)
2713 #define F0900_P1_EQUA_ACCI6 0xf47a01ff
2714 
2715 /*P1_EQUAQ6*/
2716 #define R0900_P1_EQUAQ6 0xf47b
2717 #define EQUAQ6 REGx(R0900_P1_EQUAQ6)
2718 #define F0900_P1_EQUA_ACCQ6 0xf47b01ff
2719 
2720 /*P1_EQUAI7*/
2721 #define R0900_P1_EQUAI7 0xf47c
2722 #define EQUAI7 REGx(R0900_P1_EQUAI7)
2723 #define F0900_P1_EQUA_ACCI7 0xf47c01ff
2724 
2725 /*P1_EQUAQ7*/
2726 #define R0900_P1_EQUAQ7 0xf47d
2727 #define EQUAQ7 REGx(R0900_P1_EQUAQ7)
2728 #define F0900_P1_EQUA_ACCQ7 0xf47d01ff
2729 
2730 /*P1_EQUAI8*/
2731 #define R0900_P1_EQUAI8 0xf47e
2732 #define EQUAI8 REGx(R0900_P1_EQUAI8)
2733 #define F0900_P1_EQUA_ACCI8 0xf47e01ff
2734 
2735 /*P1_EQUAQ8*/
2736 #define R0900_P1_EQUAQ8 0xf47f
2737 #define EQUAQ8 REGx(R0900_P1_EQUAQ8)
2738 #define F0900_P1_EQUA_ACCQ8 0xf47f01ff
2739 
2740 /*P1_NNOSDATAT1*/
2741 #define R0900_P1_NNOSDATAT1 0xf480
2742 #define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
2743 #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
2744 #define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
2745 
2746 /*P1_NNOSDATAT0*/
2747 #define R0900_P1_NNOSDATAT0 0xf481
2748 #define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
2749 #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
2750 #define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
2751 
2752 /*P1_NNOSDATA1*/
2753 #define R0900_P1_NNOSDATA1 0xf482
2754 #define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
2755 #define F0900_P1_NOSDATA_NORMED1 0xf48200ff
2756 
2757 /*P1_NNOSDATA0*/
2758 #define R0900_P1_NNOSDATA0 0xf483
2759 #define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
2760 #define F0900_P1_NOSDATA_NORMED0 0xf48300ff
2761 
2762 /*P1_NNOSPLHT1*/
2763 #define R0900_P1_NNOSPLHT1 0xf484
2764 #define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
2765 #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
2766 #define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
2767 
2768 /*P1_NNOSPLHT0*/
2769 #define R0900_P1_NNOSPLHT0 0xf485
2770 #define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
2771 #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
2772 #define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
2773 
2774 /*P1_NNOSPLH1*/
2775 #define R0900_P1_NNOSPLH1 0xf486
2776 #define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
2777 #define F0900_P1_NOSPLH_NORMED1 0xf48600ff
2778 
2779 /*P1_NNOSPLH0*/
2780 #define R0900_P1_NNOSPLH0 0xf487
2781 #define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
2782 #define F0900_P1_NOSPLH_NORMED0 0xf48700ff
2783 
2784 /*P1_NOSDATAT1*/
2785 #define R0900_P1_NOSDATAT1 0xf488
2786 #define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
2787 #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
2788 
2789 /*P1_NOSDATAT0*/
2790 #define R0900_P1_NOSDATAT0 0xf489
2791 #define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
2792 #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
2793 
2794 /*P1_NOSDATA1*/
2795 #define R0900_P1_NOSDATA1 0xf48a
2796 #define NOSDATA1 REGx(R0900_P1_NOSDATA1)
2797 #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
2798 
2799 /*P1_NOSDATA0*/
2800 #define R0900_P1_NOSDATA0 0xf48b
2801 #define NOSDATA0 REGx(R0900_P1_NOSDATA0)
2802 #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
2803 
2804 /*P1_NOSPLHT1*/
2805 #define R0900_P1_NOSPLHT1 0xf48c
2806 #define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
2807 #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
2808 
2809 /*P1_NOSPLHT0*/
2810 #define R0900_P1_NOSPLHT0 0xf48d
2811 #define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
2812 #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
2813 
2814 /*P1_NOSPLH1*/
2815 #define R0900_P1_NOSPLH1 0xf48e
2816 #define NOSPLH1 REGx(R0900_P1_NOSPLH1)
2817 #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
2818 
2819 /*P1_NOSPLH0*/
2820 #define R0900_P1_NOSPLH0 0xf48f
2821 #define NOSPLH0 REGx(R0900_P1_NOSPLH0)
2822 #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
2823 
2824 /*P1_CAR2CFG*/
2825 #define R0900_P1_CAR2CFG 0xf490
2826 #define CAR2CFG REGx(R0900_P1_CAR2CFG)
2827 #define F0900_P1_CARRIER3_DISABLE 0xf4900040
2828 #define F0900_P1_ROTA2ON 0xf4900004
2829 #define F0900_P1_PH_DET_ALGO2 0xf4900003
2830 
2831 /*P1_CFR2CFR1*/
2832 #define R0900_P1_CFR2CFR1 0xf491
2833 #define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
2834 #define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
2835 #define F0900_P1_EN_S2CAR2CENTER 0xf4910020
2836 #define F0900_P1_DIS_BCHERRCFR2 0xf4910010
2837 #define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
2838 
2839 /*P1_CFR22*/
2840 #define R0900_P1_CFR22 0xf493
2841 #define CFR22 REGx(R0900_P1_CFR22)
2842 #define F0900_P1_CAR2_FREQ2 0xf49301ff
2843 
2844 /*P1_CFR21*/
2845 #define R0900_P1_CFR21 0xf494
2846 #define CFR21 REGx(R0900_P1_CFR21)
2847 #define F0900_P1_CAR2_FREQ1 0xf49400ff
2848 
2849 /*P1_CFR20*/
2850 #define R0900_P1_CFR20 0xf495
2851 #define CFR20 REGx(R0900_P1_CFR20)
2852 #define F0900_P1_CAR2_FREQ0 0xf49500ff
2853 
2854 /*P1_ACLC2S2Q*/
2855 #define R0900_P1_ACLC2S2Q 0xf497
2856 #define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
2857 #define F0900_P1_ENAB_SPSKSYMB 0xf4970080
2858 #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
2859 #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
2860 
2861 /*P1_ACLC2S28*/
2862 #define R0900_P1_ACLC2S28 0xf498
2863 #define ACLC2S28 REGx(R0900_P1_ACLC2S28)
2864 #define F0900_P1_OLDI3Q_MODE 0xf4980080
2865 #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
2866 #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
2867 
2868 /*P1_ACLC2S216A*/
2869 #define R0900_P1_ACLC2S216A 0xf499
2870 #define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
2871 #define F0900_P1_DIS_C3STOPA2 0xf4990080
2872 #define F0900_P1_CAR2S2_16ADERAT 0xf4990040
2873 #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
2874 #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
2875 
2876 /*P1_ACLC2S232A*/
2877 #define R0900_P1_ACLC2S232A 0xf49a
2878 #define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
2879 #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
2880 #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
2881 #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
2882 
2883 /*P1_BCLC2S2Q*/
2884 #define R0900_P1_BCLC2S2Q 0xf49c
2885 #define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
2886 #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
2887 #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
2888 
2889 /*P1_BCLC2S28*/
2890 #define R0900_P1_BCLC2S28 0xf49d
2891 #define BCLC2S28 REGx(R0900_P1_BCLC2S28)
2892 #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
2893 #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
2894 
2895 /*P1_BCLC2S216A*/
2896 #define R0900_P1_BCLC2S216A 0xf49e
2897 #define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
2898 
2899 /*P1_BCLC2S232A*/
2900 #define R0900_P1_BCLC2S232A 0xf49f
2901 #define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
2902 
2903 /*P1_PLROOT2*/
2904 #define R0900_P1_PLROOT2 0xf4ac
2905 #define PLROOT2 REGx(R0900_P1_PLROOT2)
2906 #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
2907 #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
2908 
2909 /*P1_PLROOT1*/
2910 #define R0900_P1_PLROOT1 0xf4ad
2911 #define PLROOT1 REGx(R0900_P1_PLROOT1)
2912 #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
2913 
2914 /*P1_PLROOT0*/
2915 #define R0900_P1_PLROOT0 0xf4ae
2916 #define PLROOT0 REGx(R0900_P1_PLROOT0)
2917 #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
2918 
2919 /*P1_MODCODLST0*/
2920 #define R0900_P1_MODCODLST0 0xf4b0
2921 #define MODCODLST0 REGx(R0900_P1_MODCODLST0)
2922 
2923 /*P1_MODCODLST1*/
2924 #define R0900_P1_MODCODLST1 0xf4b1
2925 #define MODCODLST1 REGx(R0900_P1_MODCODLST1)
2926 #define F0900_P1_DIS_MODCOD29 0xf4b100f0
2927 #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
2928 
2929 /*P1_MODCODLST2*/
2930 #define R0900_P1_MODCODLST2 0xf4b2
2931 #define MODCODLST2 REGx(R0900_P1_MODCODLST2)
2932 #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
2933 #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
2934 
2935 /*P1_MODCODLST3*/
2936 #define R0900_P1_MODCODLST3 0xf4b3
2937 #define MODCODLST3 REGx(R0900_P1_MODCODLST3)
2938 #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
2939 #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
2940 
2941 /*P1_MODCODLST4*/
2942 #define R0900_P1_MODCODLST4 0xf4b4
2943 #define MODCODLST4 REGx(R0900_P1_MODCODLST4)
2944 #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
2945 #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
2946 
2947 /*P1_MODCODLST5*/
2948 #define R0900_P1_MODCODLST5 0xf4b5
2949 #define MODCODLST5 REGx(R0900_P1_MODCODLST5)
2950 #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
2951 #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
2952 
2953 /*P1_MODCODLST6*/
2954 #define R0900_P1_MODCODLST6 0xf4b6
2955 #define MODCODLST6 REGx(R0900_P1_MODCODLST6)
2956 #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
2957 #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
2958 
2959 /*P1_MODCODLST7*/
2960 #define R0900_P1_MODCODLST7 0xf4b7
2961 #define MODCODLST7 REGx(R0900_P1_MODCODLST7)
2962 #define F0900_P1_DIS_8P_9_10 0xf4b700f0
2963 #define F0900_P1_DIS_8P_8_9 0xf4b7000f
2964 
2965 /*P1_MODCODLST8*/
2966 #define R0900_P1_MODCODLST8 0xf4b8
2967 #define MODCODLST8 REGx(R0900_P1_MODCODLST8)
2968 #define F0900_P1_DIS_8P_5_6 0xf4b800f0
2969 #define F0900_P1_DIS_8P_3_4 0xf4b8000f
2970 
2971 /*P1_MODCODLST9*/
2972 #define R0900_P1_MODCODLST9 0xf4b9
2973 #define MODCODLST9 REGx(R0900_P1_MODCODLST9)
2974 #define F0900_P1_DIS_8P_2_3 0xf4b900f0
2975 #define F0900_P1_DIS_8P_3_5 0xf4b9000f
2976 
2977 /*P1_MODCODLSTA*/
2978 #define R0900_P1_MODCODLSTA 0xf4ba
2979 #define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
2980 #define F0900_P1_DIS_QP_9_10 0xf4ba00f0
2981 #define F0900_P1_DIS_QP_8_9 0xf4ba000f
2982 
2983 /*P1_MODCODLSTB*/
2984 #define R0900_P1_MODCODLSTB 0xf4bb
2985 #define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
2986 #define F0900_P1_DIS_QP_5_6 0xf4bb00f0
2987 #define F0900_P1_DIS_QP_4_5 0xf4bb000f
2988 
2989 /*P1_MODCODLSTC*/
2990 #define R0900_P1_MODCODLSTC 0xf4bc
2991 #define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
2992 #define F0900_P1_DIS_QP_3_4 0xf4bc00f0
2993 #define F0900_P1_DIS_QP_2_3 0xf4bc000f
2994 
2995 /*P1_MODCODLSTD*/
2996 #define R0900_P1_MODCODLSTD 0xf4bd
2997 #define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
2998 #define F0900_P1_DIS_QP_3_5 0xf4bd00f0
2999 #define F0900_P1_DIS_QP_1_2 0xf4bd000f
3000 
3001 /*P1_MODCODLSTE*/
3002 #define R0900_P1_MODCODLSTE 0xf4be
3003 #define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
3004 #define F0900_P1_DIS_QP_2_5 0xf4be00f0
3005 #define F0900_P1_DIS_QP_1_3 0xf4be000f
3006 
3007 /*P1_MODCODLSTF*/
3008 #define R0900_P1_MODCODLSTF 0xf4bf
3009 #define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
3010 #define F0900_P1_DIS_QP_1_4 0xf4bf00f0
3011 
3012 /*P1_GAUSSR0*/
3013 #define R0900_P1_GAUSSR0 0xf4c0
3014 #define GAUSSR0 REGx(R0900_P1_GAUSSR0)
3015 #define F0900_P1_EN_CCIMODE 0xf4c00080
3016 #define F0900_P1_R0_GAUSSIEN 0xf4c0007f
3017 
3018 /*P1_CCIR0*/
3019 #define R0900_P1_CCIR0 0xf4c1
3020 #define CCIR0 REGx(R0900_P1_CCIR0)
3021 #define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
3022 #define F0900_P1_R0_CCI 0xf4c1007f
3023 
3024 /*P1_CCIQUANT*/
3025 #define R0900_P1_CCIQUANT 0xf4c2
3026 #define CCIQUANT REGx(R0900_P1_CCIQUANT)
3027 #define F0900_P1_CCI_BETA 0xf4c200e0
3028 #define F0900_P1_CCI_QUANT 0xf4c2001f
3029 
3030 /*P1_CCITHRES*/
3031 #define R0900_P1_CCITHRES 0xf4c3
3032 #define CCITHRES REGx(R0900_P1_CCITHRES)
3033 #define F0900_P1_CCI_THRESHOLD 0xf4c300ff
3034 
3035 /*P1_CCIACC*/
3036 #define R0900_P1_CCIACC 0xf4c4
3037 #define CCIACC REGx(R0900_P1_CCIACC)
3038 #define F0900_P1_CCI_VALUE 0xf4c400ff
3039 
3040 /*P1_DMDRESCFG*/
3041 #define R0900_P1_DMDRESCFG 0xf4c6
3042 #define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
3043 #define F0900_P1_DMDRES_RESET 0xf4c60080
3044 #define F0900_P1_DMDRES_STRALL 0xf4c60008
3045 #define F0900_P1_DMDRES_NEWONLY 0xf4c60004
3046 #define F0900_P1_DMDRES_NOSTORE 0xf4c60002
3047 
3048 /*P1_DMDRESADR*/
3049 #define R0900_P1_DMDRESADR 0xf4c7
3050 #define DMDRESADR REGx(R0900_P1_DMDRESADR)
3051 #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
3052 #define F0900_P1_DMDRES_MEMFULL 0xf4c70030
3053 #define F0900_P1_DMDRES_RESNBR 0xf4c7000f
3054 
3055 /*P1_DMDRESDATA7*/
3056 #define R0900_P1_DMDRESDATA7 0xf4c8
3057 #define F0900_P1_DMDRES_DATA7 0xf4c800ff
3058 
3059 /*P1_DMDRESDATA6*/
3060 #define R0900_P1_DMDRESDATA6 0xf4c9
3061 #define F0900_P1_DMDRES_DATA6 0xf4c900ff
3062 
3063 /*P1_DMDRESDATA5*/
3064 #define R0900_P1_DMDRESDATA5 0xf4ca
3065 #define F0900_P1_DMDRES_DATA5 0xf4ca00ff
3066 
3067 /*P1_DMDRESDATA4*/
3068 #define R0900_P1_DMDRESDATA4 0xf4cb
3069 #define F0900_P1_DMDRES_DATA4 0xf4cb00ff
3070 
3071 /*P1_DMDRESDATA3*/
3072 #define R0900_P1_DMDRESDATA3 0xf4cc
3073 #define F0900_P1_DMDRES_DATA3 0xf4cc00ff
3074 
3075 /*P1_DMDRESDATA2*/
3076 #define R0900_P1_DMDRESDATA2 0xf4cd
3077 #define F0900_P1_DMDRES_DATA2 0xf4cd00ff
3078 
3079 /*P1_DMDRESDATA1*/
3080 #define R0900_P1_DMDRESDATA1 0xf4ce
3081 #define F0900_P1_DMDRES_DATA1 0xf4ce00ff
3082 
3083 /*P1_DMDRESDATA0*/
3084 #define R0900_P1_DMDRESDATA0 0xf4cf
3085 #define F0900_P1_DMDRES_DATA0 0xf4cf00ff
3086 
3087 /*P1_FFEI1*/
3088 #define R0900_P1_FFEI1 0xf4d0
3089 #define FFEI1 REGx(R0900_P1_FFEI1)
3090 #define F0900_P1_FFE_ACCI1 0xf4d001ff
3091 
3092 /*P1_FFEQ1*/
3093 #define R0900_P1_FFEQ1 0xf4d1
3094 #define FFEQ1 REGx(R0900_P1_FFEQ1)
3095 #define F0900_P1_FFE_ACCQ1 0xf4d101ff
3096 
3097 /*P1_FFEI2*/
3098 #define R0900_P1_FFEI2 0xf4d2
3099 #define FFEI2 REGx(R0900_P1_FFEI2)
3100 #define F0900_P1_FFE_ACCI2 0xf4d201ff
3101 
3102 /*P1_FFEQ2*/
3103 #define R0900_P1_FFEQ2 0xf4d3
3104 #define FFEQ2 REGx(R0900_P1_FFEQ2)
3105 #define F0900_P1_FFE_ACCQ2 0xf4d301ff
3106 
3107 /*P1_FFEI3*/
3108 #define R0900_P1_FFEI3 0xf4d4
3109 #define FFEI3 REGx(R0900_P1_FFEI3)
3110 #define F0900_P1_FFE_ACCI3 0xf4d401ff
3111 
3112 /*P1_FFEQ3*/
3113 #define R0900_P1_FFEQ3 0xf4d5
3114 #define FFEQ3 REGx(R0900_P1_FFEQ3)
3115 #define F0900_P1_FFE_ACCQ3 0xf4d501ff
3116 
3117 /*P1_FFEI4*/
3118 #define R0900_P1_FFEI4 0xf4d6
3119 #define FFEI4 REGx(R0900_P1_FFEI4)
3120 #define F0900_P1_FFE_ACCI4 0xf4d601ff
3121 
3122 /*P1_FFEQ4*/
3123 #define R0900_P1_FFEQ4 0xf4d7
3124 #define FFEQ4 REGx(R0900_P1_FFEQ4)
3125 #define F0900_P1_FFE_ACCQ4 0xf4d701ff
3126 
3127 /*P1_FFECFG*/
3128 #define R0900_P1_FFECFG 0xf4d8
3129 #define FFECFG REGx(R0900_P1_FFECFG)
3130 #define F0900_P1_EQUALFFE_ON 0xf4d80040
3131 #define F0900_P1_MU_EQUALFFE 0xf4d80007
3132 
3133 /*P1_TNRCFG*/
3134 #define R0900_P1_TNRCFG 0xf4e0
3135 #define TNRCFG REGx(R0900_P1_TNRCFG)
3136 #define F0900_P1_TUN_ACKFAIL 0xf4e00080
3137 #define F0900_P1_TUN_TYPE 0xf4e00070
3138 #define F0900_P1_TUN_SECSTOP 0xf4e00008
3139 #define F0900_P1_TUN_VCOSRCH 0xf4e00004
3140 #define F0900_P1_TUN_MADDRESS 0xf4e00003
3141 
3142 /*P1_TNRCFG2*/
3143 #define R0900_P1_TNRCFG2 0xf4e1
3144 #define TNRCFG2 REGx(R0900_P1_TNRCFG2)
3145 #define F0900_P1_TUN_IQSWAP 0xf4e10080
3146 #define F0900_P1_DIS_BWCALC 0xf4e10004
3147 #define F0900_P1_SHORT_WAITSTATES 0xf4e10002
3148 
3149 /*P1_TNRXTAL*/
3150 #define R0900_P1_TNRXTAL 0xf4e4
3151 #define TNRXTAL REGx(R0900_P1_TNRXTAL)
3152 #define F0900_P1_TUN_XTALFREQ 0xf4e4001f
3153 
3154 /*P1_TNRSTEPS*/
3155 #define R0900_P1_TNRSTEPS 0xf4e7
3156 #define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
3157 #define F0900_P1_TUNER_BW0P125 0xf4e70080
3158 #define F0900_P1_BWINC_OFFSET 0xf4e70170
3159 #define F0900_P1_SOFTSTEP_RNG 0xf4e70008
3160 #define F0900_P1_TUN_BWOFFSET 0xf4e70007
3161 
3162 /*P1_TNRGAIN*/
3163 #define R0900_P1_TNRGAIN 0xf4e8
3164 #define TNRGAIN REGx(R0900_P1_TNRGAIN)
3165 #define F0900_P1_TUN_KDIVEN 0xf4e800c0
3166 #define F0900_P1_STB6X00_OCK 0xf4e80030
3167 #define F0900_P1_TUN_GAIN 0xf4e8000f
3168 
3169 /*P1_TNRRF1*/
3170 #define R0900_P1_TNRRF1 0xf4e9
3171 #define TNRRF1 REGx(R0900_P1_TNRRF1)
3172 #define F0900_P1_TUN_RFFREQ2 0xf4e900ff
3173 #define TUN_RFFREQ2 FLDx(F0900_P1_TUN_RFFREQ2)
3174 
3175 /*P1_TNRRF0*/
3176 #define R0900_P1_TNRRF0 0xf4ea
3177 #define TNRRF0 REGx(R0900_P1_TNRRF0)
3178 #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
3179 #define TUN_RFFREQ1 FLDx(F0900_P1_TUN_RFFREQ1)
3180 
3181 /*P1_TNRBW*/
3182 #define R0900_P1_TNRBW 0xf4eb
3183 #define TNRBW REGx(R0900_P1_TNRBW)
3184 #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
3185 #define TUN_RFFREQ0 FLDx(F0900_P1_TUN_RFFREQ0)
3186 #define F0900_P1_TUN_BW 0xf4eb003f
3187 #define TUN_BW FLDx(F0900_P1_TUN_BW)
3188 
3189 /*P1_TNRADJ*/
3190 #define R0900_P1_TNRADJ 0xf4ec
3191 #define TNRADJ REGx(R0900_P1_TNRADJ)
3192 #define F0900_P1_STB61X0_CALTIME 0xf4ec0040
3193 
3194 /*P1_TNRCTL2*/
3195 #define R0900_P1_TNRCTL2 0xf4ed
3196 #define TNRCTL2 REGx(R0900_P1_TNRCTL2)
3197 #define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
3198 #define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
3199 #define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
3200 #define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
3201 #define F0900_P1_STB61X0_CALOFF 0xf4ed0008
3202 #define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
3203 #define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
3204 #define F0900_P1_STB6XX0_SYN 0xf4ed0001
3205 
3206 /*P1_TNRCFG3*/
3207 #define R0900_P1_TNRCFG3 0xf4ee
3208 #define TNRCFG3 REGx(R0900_P1_TNRCFG3)
3209 #define F0900_P1_TUN_PLLFREQ 0xf4ee001c
3210 #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
3211 
3212 /*P1_TNRLAUNCH*/
3213 #define R0900_P1_TNRLAUNCH 0xf4f0
3214 #define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
3215 
3216 /*P1_TNRLD*/
3217 #define R0900_P1_TNRLD 0xf4f0
3218 #define TNRLD REGx(R0900_P1_TNRLD)
3219 #define F0900_P1_TUNLD_VCOING 0xf4f00080
3220 #define F0900_P1_TUN_REG1FAIL 0xf4f00040
3221 #define F0900_P1_TUN_REG2FAIL 0xf4f00020
3222 #define F0900_P1_TUN_REG3FAIL 0xf4f00010
3223 #define F0900_P1_TUN_REG4FAIL 0xf4f00008
3224 #define F0900_P1_TUN_REG5FAIL 0xf4f00004
3225 #define F0900_P1_TUN_BWING 0xf4f00002
3226 #define F0900_P1_TUN_LOCKED 0xf4f00001
3227 
3228 /*P1_TNROBSL*/
3229 #define R0900_P1_TNROBSL 0xf4f6
3230 #define TNROBSL REGx(R0900_P1_TNROBSL)
3231 #define F0900_P1_TUN_I2CABORTED 0xf4f60080
3232 #define F0900_P1_TUN_LPEN 0xf4f60040
3233 #define F0900_P1_TUN_FCCK 0xf4f60020
3234 #define F0900_P1_TUN_I2CLOCKED 0xf4f60010
3235 #define F0900_P1_TUN_PROGDONE 0xf4f6000c
3236 #define F0900_P1_TUN_RFRESTE1 0xf4f60003
3237 #define TUN_RFRESTE1 FLDx(F0900_P1_TUN_RFRESTE1)
3238 
3239 /*P1_TNRRESTE*/
3240 #define R0900_P1_TNRRESTE 0xf4f7
3241 #define TNRRESTE REGx(R0900_P1_TNRRESTE)
3242 #define F0900_P1_TUN_RFRESTE0 0xf4f700ff
3243 #define TUN_RFRESTE0 FLDx(F0900_P1_TUN_RFRESTE0)
3244 
3245 /*P1_SMAPCOEF7*/
3246 #define R0900_P1_SMAPCOEF7 0xf500
3247 #define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
3248 #define F0900_P1_DIS_QSCALE 0xf5000080
3249 #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
3250 
3251 /*P1_SMAPCOEF6*/
3252 #define R0900_P1_SMAPCOEF6 0xf501
3253 #define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
3254 #define F0900_P1_ADJ_8PSKLLR1 0xf5010004
3255 #define F0900_P1_OLD_8PSKLLR1 0xf5010002
3256 #define F0900_P1_DIS_AB8PSK 0xf5010001
3257 
3258 /*P1_SMAPCOEF5*/
3259 #define R0900_P1_SMAPCOEF5 0xf502
3260 #define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
3261 #define F0900_P1_DIS_8SCALE 0xf5020080
3262 #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
3263 
3264 /*P1_NCO2MAX1*/
3265 #define R0900_P1_NCO2MAX1 0xf514
3266 #define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
3267 #define F0900_P1_TETA2_MAXVABS1 0xf51400ff
3268 
3269 /*P1_NCO2MAX0*/
3270 #define R0900_P1_NCO2MAX0 0xf515
3271 #define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
3272 #define F0900_P1_TETA2_MAXVABS0 0xf51500ff
3273 
3274 /*P1_NCO2FR1*/
3275 #define R0900_P1_NCO2FR1 0xf516
3276 #define NCO2FR1 REGx(R0900_P1_NCO2FR1)
3277 #define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
3278 
3279 /*P1_NCO2FR0*/
3280 #define R0900_P1_NCO2FR0 0xf517
3281 #define NCO2FR0 REGx(R0900_P1_NCO2FR0)
3282 #define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
3283 
3284 /*P1_CFR2AVRGE1*/
3285 #define R0900_P1_CFR2AVRGE1 0xf518
3286 #define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
3287 #define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
3288 
3289 /*P1_CFR2AVRGE0*/
3290 #define R0900_P1_CFR2AVRGE0 0xf519
3291 #define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
3292 #define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
3293 
3294 /*P1_DMDPLHSTAT*/
3295 #define R0900_P1_DMDPLHSTAT 0xf520
3296 #define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
3297 #define F0900_P1_PLH_STATISTIC 0xf52000ff
3298 
3299 /*P1_LOCKTIME3*/
3300 #define R0900_P1_LOCKTIME3 0xf522
3301 #define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
3302 #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
3303 
3304 /*P1_LOCKTIME2*/
3305 #define R0900_P1_LOCKTIME2 0xf523
3306 #define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
3307 #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
3308 
3309 /*P1_LOCKTIME1*/
3310 #define R0900_P1_LOCKTIME1 0xf524
3311 #define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
3312 #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
3313 
3314 /*P1_LOCKTIME0*/
3315 #define R0900_P1_LOCKTIME0 0xf525
3316 #define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
3317 #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
3318 
3319 /*P1_VITSCALE*/
3320 #define R0900_P1_VITSCALE 0xf532
3321 #define VITSCALE REGx(R0900_P1_VITSCALE)
3322 #define F0900_P1_NVTH_NOSRANGE 0xf5320080
3323 #define F0900_P1_VERROR_MAXMODE 0xf5320040
3324 #define F0900_P1_NSLOWSN_LOCKED 0xf5320008
3325 #define F0900_P1_DIS_RSFLOCK 0xf5320002
3326 
3327 /*P1_FECM*/
3328 #define R0900_P1_FECM 0xf533
3329 #define FECM REGx(R0900_P1_FECM)
3330 #define F0900_P1_DSS_DVB 0xf5330080
3331 #define DSS_DVB FLDx(F0900_P1_DSS_DVB)
3332 #define F0900_P1_DSS_SRCH 0xf5330010
3333 #define F0900_P1_SYNCVIT 0xf5330002
3334 #define F0900_P1_IQINV 0xf5330001
3335 #define IQINV FLDx(F0900_P1_IQINV)
3336 
3337 /*P1_VTH12*/
3338 #define R0900_P1_VTH12 0xf534
3339 #define VTH12 REGx(R0900_P1_VTH12)
3340 #define F0900_P1_VTH12 0xf53400ff
3341 
3342 /*P1_VTH23*/
3343 #define R0900_P1_VTH23 0xf535
3344 #define VTH23 REGx(R0900_P1_VTH23)
3345 #define F0900_P1_VTH23 0xf53500ff
3346 
3347 /*P1_VTH34*/
3348 #define R0900_P1_VTH34 0xf536
3349 #define VTH34 REGx(R0900_P1_VTH34)
3350 #define F0900_P1_VTH34 0xf53600ff
3351 
3352 /*P1_VTH56*/
3353 #define R0900_P1_VTH56 0xf537
3354 #define VTH56 REGx(R0900_P1_VTH56)
3355 #define F0900_P1_VTH56 0xf53700ff
3356 
3357 /*P1_VTH67*/
3358 #define R0900_P1_VTH67 0xf538
3359 #define VTH67 REGx(R0900_P1_VTH67)
3360 #define F0900_P1_VTH67 0xf53800ff
3361 
3362 /*P1_VTH78*/
3363 #define R0900_P1_VTH78 0xf539
3364 #define VTH78 REGx(R0900_P1_VTH78)
3365 #define F0900_P1_VTH78 0xf53900ff
3366 
3367 /*P1_VITCURPUN*/
3368 #define R0900_P1_VITCURPUN 0xf53a
3369 #define VITCURPUN REGx(R0900_P1_VITCURPUN)
3370 #define F0900_P1_VIT_CURPUN 0xf53a001f
3371 #define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
3372 
3373 /*P1_VERROR*/
3374 #define R0900_P1_VERROR 0xf53b
3375 #define VERROR REGx(R0900_P1_VERROR)
3376 #define F0900_P1_REGERR_VIT 0xf53b00ff
3377 
3378 /*P1_PRVIT*/
3379 #define R0900_P1_PRVIT 0xf53c
3380 #define PRVIT REGx(R0900_P1_PRVIT)
3381 #define F0900_P1_DIS_VTHLOCK 0xf53c0040
3382 #define F0900_P1_E7_8VIT 0xf53c0020
3383 #define F0900_P1_E6_7VIT 0xf53c0010
3384 #define F0900_P1_E5_6VIT 0xf53c0008
3385 #define F0900_P1_E3_4VIT 0xf53c0004
3386 #define F0900_P1_E2_3VIT 0xf53c0002
3387 #define F0900_P1_E1_2VIT 0xf53c0001
3388 
3389 /*P1_VAVSRVIT*/
3390 #define R0900_P1_VAVSRVIT 0xf53d
3391 #define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
3392 #define F0900_P1_AMVIT 0xf53d0080
3393 #define F0900_P1_FROZENVIT 0xf53d0040
3394 #define F0900_P1_SNVIT 0xf53d0030
3395 #define F0900_P1_TOVVIT 0xf53d000c
3396 #define F0900_P1_HYPVIT 0xf53d0003
3397 
3398 /*P1_VSTATUSVIT*/
3399 #define R0900_P1_VSTATUSVIT 0xf53e
3400 #define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
3401 #define F0900_P1_PRFVIT 0xf53e0010
3402 #define PRFVIT FLDx(F0900_P1_PRFVIT)
3403 #define F0900_P1_LOCKEDVIT 0xf53e0008
3404 #define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
3405 
3406 /*P1_VTHINUSE*/
3407 #define R0900_P1_VTHINUSE 0xf53f
3408 #define VTHINUSE REGx(R0900_P1_VTHINUSE)
3409 #define F0900_P1_VIT_INUSE 0xf53f00ff
3410 
3411 /*P1_KDIV12*/
3412 #define R0900_P1_KDIV12 0xf540
3413 #define KDIV12 REGx(R0900_P1_KDIV12)
3414 #define F0900_P1_K_DIVIDER_12 0xf540007f
3415 
3416 /*P1_KDIV23*/
3417 #define R0900_P1_KDIV23 0xf541
3418 #define KDIV23 REGx(R0900_P1_KDIV23)
3419 #define F0900_P1_K_DIVIDER_23 0xf541007f
3420 
3421 /*P1_KDIV34*/
3422 #define R0900_P1_KDIV34 0xf542
3423 #define KDIV34 REGx(R0900_P1_KDIV34)
3424 #define F0900_P1_K_DIVIDER_34 0xf542007f
3425 
3426 /*P1_KDIV56*/
3427 #define R0900_P1_KDIV56 0xf543
3428 #define KDIV56 REGx(R0900_P1_KDIV56)
3429 #define F0900_P1_K_DIVIDER_56 0xf543007f
3430 
3431 /*P1_KDIV67*/
3432 #define R0900_P1_KDIV67 0xf544
3433 #define KDIV67 REGx(R0900_P1_KDIV67)
3434 #define F0900_P1_K_DIVIDER_67 0xf544007f
3435 
3436 /*P1_KDIV78*/
3437 #define R0900_P1_KDIV78 0xf545
3438 #define KDIV78 REGx(R0900_P1_KDIV78)
3439 #define F0900_P1_K_DIVIDER_78 0xf545007f
3440 
3441 /*P1_PDELCTRL1*/
3442 #define R0900_P1_PDELCTRL1 0xf550
3443 #define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
3444 #define F0900_P1_INV_MISMASK 0xf5500080
3445 #define INV_MISMASK FLDx(F0900_P1_INV_MISMASK)
3446 #define F0900_P1_FILTER_EN 0xf5500020
3447 #define FILTER_EN FLDx(F0900_P1_FILTER_EN)
3448 #define F0900_P1_EN_MIS00 0xf5500002
3449 #define EN_MIS00 FLDx(F0900_P1_EN_MIS00)
3450 #define F0900_P1_ALGOSWRST 0xf5500001
3451 #define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
3452 
3453 /*P1_PDELCTRL2*/
3454 #define R0900_P1_PDELCTRL2 0xf551
3455 #define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
3456 #define F0900_P1_RESET_UPKO_COUNT 0xf5510040
3457 #define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
3458 #define F0900_P1_FRAME_MODE 0xf5510002
3459 #define F0900_P1_NOBCHERRFLG_USE 0xf5510001
3460 
3461 /*P1_HYSTTHRESH*/
3462 #define R0900_P1_HYSTTHRESH 0xf554
3463 #define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
3464 #define F0900_P1_UNLCK_THRESH 0xf55400f0
3465 #define F0900_P1_DELIN_LCK_THRESH 0xf554000f
3466 
3467 /*P1_ISIENTRY*/
3468 #define R0900_P1_ISIENTRY 0xf55e
3469 #define ISIENTRY REGx(R0900_P1_ISIENTRY)
3470 #define F0900_P1_ISI_ENTRY 0xf55e00ff
3471 
3472 /*P1_ISIBITENA*/
3473 #define R0900_P1_ISIBITENA 0xf55f
3474 #define ISIBITENA REGx(R0900_P1_ISIBITENA)
3475 #define F0900_P1_ISI_BIT_EN 0xf55f00ff
3476 
3477 /*P1_MATSTR1*/
3478 #define R0900_P1_MATSTR1 0xf560
3479 #define MATSTR1 REGx(R0900_P1_MATSTR1)
3480 #define F0900_P1_MATYPE_CURRENT1 0xf56000ff
3481 
3482 /*P1_MATSTR0*/
3483 #define R0900_P1_MATSTR0 0xf561
3484 #define MATSTR0 REGx(R0900_P1_MATSTR0)
3485 #define F0900_P1_MATYPE_CURRENT0 0xf56100ff
3486 
3487 /*P1_UPLSTR1*/
3488 #define R0900_P1_UPLSTR1 0xf562
3489 #define UPLSTR1 REGx(R0900_P1_UPLSTR1)
3490 #define F0900_P1_UPL_CURRENT1 0xf56200ff
3491 
3492 /*P1_UPLSTR0*/
3493 #define R0900_P1_UPLSTR0 0xf563
3494 #define UPLSTR0 REGx(R0900_P1_UPLSTR0)
3495 #define F0900_P1_UPL_CURRENT0 0xf56300ff
3496 
3497 /*P1_DFLSTR1*/
3498 #define R0900_P1_DFLSTR1 0xf564
3499 #define DFLSTR1 REGx(R0900_P1_DFLSTR1)
3500 #define F0900_P1_DFL_CURRENT1 0xf56400ff
3501 
3502 /*P1_DFLSTR0*/
3503 #define R0900_P1_DFLSTR0 0xf565
3504 #define DFLSTR0 REGx(R0900_P1_DFLSTR0)
3505 #define F0900_P1_DFL_CURRENT0 0xf56500ff
3506 
3507 /*P1_SYNCSTR*/
3508 #define R0900_P1_SYNCSTR 0xf566
3509 #define SYNCSTR REGx(R0900_P1_SYNCSTR)
3510 #define F0900_P1_SYNC_CURRENT 0xf56600ff
3511 
3512 /*P1_SYNCDSTR1*/
3513 #define R0900_P1_SYNCDSTR1 0xf567
3514 #define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
3515 #define F0900_P1_SYNCD_CURRENT1 0xf56700ff
3516 
3517 /*P1_SYNCDSTR0*/
3518 #define R0900_P1_SYNCDSTR0 0xf568
3519 #define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
3520 #define F0900_P1_SYNCD_CURRENT0 0xf56800ff
3521 
3522 /*P1_PDELSTATUS1*/
3523 #define R0900_P1_PDELSTATUS1 0xf569
3524 #define F0900_P1_PKTDELIN_DELOCK 0xf5690080
3525 #define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
3526 #define F0900_P1_CONTINUOUS_STREAM 0xf5690020
3527 #define F0900_P1_UNACCEPTED_STREAM 0xf5690010
3528 #define F0900_P1_BCH_ERROR_FLAG 0xf5690008
3529 #define F0900_P1_PKTDELIN_LOCK 0xf5690002
3530 #define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
3531 #define F0900_P1_FIRST_LOCK 0xf5690001
3532 
3533 /*P1_PDELSTATUS2*/
3534 #define R0900_P1_PDELSTATUS2 0xf56a
3535 #define F0900_P1_FRAME_MODCOD 0xf56a007c
3536 #define F0900_P1_FRAME_TYPE 0xf56a0003
3537 
3538 /*P1_BBFCRCKO1*/
3539 #define R0900_P1_BBFCRCKO1 0xf56b
3540 #define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
3541 #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
3542 
3543 /*P1_BBFCRCKO0*/
3544 #define R0900_P1_BBFCRCKO0 0xf56c
3545 #define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
3546 #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
3547 
3548 /*P1_UPCRCKO1*/
3549 #define R0900_P1_UPCRCKO1 0xf56d
3550 #define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
3551 #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
3552 
3553 /*P1_UPCRCKO0*/
3554 #define R0900_P1_UPCRCKO0 0xf56e
3555 #define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
3556 #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
3557 
3558 /*P1_PDELCTRL3*/
3559 #define R0900_P1_PDELCTRL3 0xf56f
3560 #define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
3561 #define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
3562 #define F0900_P1_NOFIFO_BCHERR 0xf56f0020
3563 
3564 /*P1_TSSTATEM*/
3565 #define R0900_P1_TSSTATEM 0xf570
3566 #define TSSTATEM REGx(R0900_P1_TSSTATEM)
3567 #define F0900_P1_TSDIL_ON 0xf5700080
3568 #define F0900_P1_TSRS_ON 0xf5700020
3569 #define F0900_P1_TSDESCRAMB_ON 0xf5700010
3570 #define F0900_P1_TSFRAME_MODE 0xf5700008
3571 #define F0900_P1_TS_DISABLE 0xf5700004
3572 #define F0900_P1_TSOUT_NOSYNC 0xf5700001
3573 
3574 /*P1_TSCFGH*/
3575 #define R0900_P1_TSCFGH 0xf572
3576 #define TSCFGH REGx(R0900_P1_TSCFGH)
3577 #define F0900_P1_TSFIFO_DVBCI 0xf5720080
3578 #define F0900_P1_TSFIFO_SERIAL 0xf5720040
3579 #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
3580 #define F0900_P1_TSFIFO_DUTY50 0xf5720010
3581 #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
3582 #define F0900_P1_TSFIFO_ERRMODE 0xf5720006
3583 #define F0900_P1_RST_HWARE 0xf5720001
3584 #define RST_HWARE FLDx(F0900_P1_RST_HWARE)
3585 
3586 /*P1_TSCFGM*/
3587 #define R0900_P1_TSCFGM 0xf573
3588 #define TSCFGM REGx(R0900_P1_TSCFGM)
3589 #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
3590 #define F0900_P1_TSFIFO_PERMDATA 0xf5730020
3591 #define F0900_P1_TSFIFO_DPUNACT 0xf5730002
3592 #define F0900_P1_TSFIFO_INVDATA 0xf5730001
3593 
3594 /*P1_TSCFGL*/
3595 #define R0900_P1_TSCFGL 0xf574
3596 #define TSCFGL REGx(R0900_P1_TSCFGL)
3597 #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
3598 #define F0900_P1_BCHERROR_MODE 0xf5740030
3599 #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
3600 #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
3601 #define F0900_P1_TSFIFO_BITSPEED 0xf5740003
3602 
3603 /*P1_TSINSDELH*/
3604 #define R0900_P1_TSINSDELH 0xf576
3605 #define TSINSDELH REGx(R0900_P1_TSINSDELH)
3606 #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
3607 #define F0900_P1_TSDEL_XXHEADER 0xf5760040
3608 #define F0900_P1_TSDEL_BBHEADER 0xf5760020
3609 #define F0900_P1_TSDEL_DATAFIELD 0xf5760010
3610 #define F0900_P1_TSINSDEL_ISCR 0xf5760008
3611 #define F0900_P1_TSINSDEL_NPD 0xf5760004
3612 #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
3613 #define F0900_P1_TSINSDEL_CRC8 0xf5760001
3614 
3615 /*P1_TSDIVN*/
3616 #define R0900_P1_TSDIVN 0xf579
3617 #define TSDIVN REGx(R0900_P1_TSDIVN)
3618 #define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
3619 
3620 /*P1_TSCFG4*/
3621 #define R0900_P1_TSCFG4 0xf57a
3622 #define TSCFG4 REGx(R0900_P1_TSCFG4)
3623 #define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
3624 
3625 /*P1_TSSPEED*/
3626 #define R0900_P1_TSSPEED 0xf580
3627 #define TSSPEED REGx(R0900_P1_TSSPEED)
3628 #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
3629 
3630 /*P1_TSSTATUS*/
3631 #define R0900_P1_TSSTATUS 0xf581
3632 #define TSSTATUS REGx(R0900_P1_TSSTATUS)
3633 #define F0900_P1_TSFIFO_LINEOK 0xf5810080
3634 #define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
3635 #define F0900_P1_TSFIFO_ERROR 0xf5810040
3636 #define F0900_P1_DIL_READY 0xf5810001
3637 
3638 /*P1_TSSTATUS2*/
3639 #define R0900_P1_TSSTATUS2 0xf582
3640 #define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
3641 #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
3642 #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
3643 #define F0900_P1_DILXX_RESET 0xf5820020
3644 #define F0900_P1_TSSERIAL_IMPOS 0xf5820010
3645 #define F0900_P1_SCRAMBDETECT 0xf5820002
3646 
3647 /*P1_TSBITRATE1*/
3648 #define R0900_P1_TSBITRATE1 0xf583
3649 #define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
3650 #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
3651 
3652 /*P1_TSBITRATE0*/
3653 #define R0900_P1_TSBITRATE0 0xf584
3654 #define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
3655 #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
3656 
3657 /*P1_ERRCTRL1*/
3658 #define R0900_P1_ERRCTRL1 0xf598
3659 #define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
3660 #define F0900_P1_ERR_SOURCE1 0xf59800f0
3661 #define F0900_P1_NUM_EVENT1 0xf5980007
3662 
3663 /*P1_ERRCNT12*/
3664 #define R0900_P1_ERRCNT12 0xf599
3665 #define ERRCNT12 REGx(R0900_P1_ERRCNT12)
3666 #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
3667 #define F0900_P1_ERR_CNT12 0xf599007f
3668 #define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
3669 
3670 /*P1_ERRCNT11*/
3671 #define R0900_P1_ERRCNT11 0xf59a
3672 #define ERRCNT11 REGx(R0900_P1_ERRCNT11)
3673 #define F0900_P1_ERR_CNT11 0xf59a00ff
3674 #define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
3675 
3676 /*P1_ERRCNT10*/
3677 #define R0900_P1_ERRCNT10 0xf59b
3678 #define ERRCNT10 REGx(R0900_P1_ERRCNT10)
3679 #define F0900_P1_ERR_CNT10 0xf59b00ff
3680 #define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
3681 
3682 /*P1_ERRCTRL2*/
3683 #define R0900_P1_ERRCTRL2 0xf59c
3684 #define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
3685 #define F0900_P1_ERR_SOURCE2 0xf59c00f0
3686 #define F0900_P1_NUM_EVENT2 0xf59c0007
3687 
3688 /*P1_ERRCNT22*/
3689 #define R0900_P1_ERRCNT22 0xf59d
3690 #define ERRCNT22 REGx(R0900_P1_ERRCNT22)
3691 #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
3692 #define F0900_P1_ERR_CNT22 0xf59d007f
3693 #define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
3694 
3695 /*P1_ERRCNT21*/
3696 #define R0900_P1_ERRCNT21 0xf59e
3697 #define ERRCNT21 REGx(R0900_P1_ERRCNT21)
3698 #define F0900_P1_ERR_CNT21 0xf59e00ff
3699 #define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
3700 
3701 /*P1_ERRCNT20*/
3702 #define R0900_P1_ERRCNT20 0xf59f
3703 #define ERRCNT20 REGx(R0900_P1_ERRCNT20)
3704 #define F0900_P1_ERR_CNT20 0xf59f00ff
3705 #define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
3706 
3707 /*P1_FECSPY*/
3708 #define R0900_P1_FECSPY 0xf5a0
3709 #define FECSPY REGx(R0900_P1_FECSPY)
3710 #define F0900_P1_SPY_ENABLE 0xf5a00080
3711 #define F0900_P1_NO_SYNCBYTE 0xf5a00040
3712 #define F0900_P1_SERIAL_MODE 0xf5a00020
3713 #define F0900_P1_UNUSUAL_PACKET 0xf5a00010
3714 #define F0900_P1_BERMETER_DATAMODE 0xf5a00008
3715 #define F0900_P1_BERMETER_LMODE 0xf5a00002
3716 #define F0900_P1_BERMETER_RESET 0xf5a00001
3717 
3718 /*P1_FSPYCFG*/
3719 #define R0900_P1_FSPYCFG 0xf5a1
3720 #define FSPYCFG REGx(R0900_P1_FSPYCFG)
3721 #define F0900_P1_FECSPY_INPUT 0xf5a100c0
3722 #define F0900_P1_RST_ON_ERROR 0xf5a10020
3723 #define F0900_P1_ONE_SHOT 0xf5a10010
3724 #define F0900_P1_I2C_MODE 0xf5a1000c
3725 #define F0900_P1_SPY_HYSTERESIS 0xf5a10003
3726 
3727 /*P1_FSPYDATA*/
3728 #define R0900_P1_FSPYDATA 0xf5a2
3729 #define FSPYDATA REGx(R0900_P1_FSPYDATA)
3730 #define F0900_P1_SPY_STUFFING 0xf5a20080
3731 #define F0900_P1_SPY_CNULLPKT 0xf5a20020
3732 #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
3733 
3734 /*P1_FSPYOUT*/
3735 #define R0900_P1_FSPYOUT 0xf5a3
3736 #define FSPYOUT REGx(R0900_P1_FSPYOUT)
3737 #define F0900_P1_FSPY_DIRECT 0xf5a30080
3738 #define F0900_P1_STUFF_MODE 0xf5a30007
3739 
3740 /*P1_FSTATUS*/
3741 #define R0900_P1_FSTATUS 0xf5a4
3742 #define FSTATUS REGx(R0900_P1_FSTATUS)
3743 #define F0900_P1_SPY_ENDSIM 0xf5a40080
3744 #define F0900_P1_VALID_SIM 0xf5a40040
3745 #define F0900_P1_FOUND_SIGNAL 0xf5a40020
3746 #define F0900_P1_DSS_SYNCBYTE 0xf5a40010
3747 #define F0900_P1_RESULT_STATE 0xf5a4000f
3748 
3749 /*P1_FBERCPT4*/
3750 #define R0900_P1_FBERCPT4 0xf5a8
3751 #define FBERCPT4 REGx(R0900_P1_FBERCPT4)
3752 #define F0900_P1_FBERMETER_CPT4 0xf5a800ff
3753 
3754 /*P1_FBERCPT3*/
3755 #define R0900_P1_FBERCPT3 0xf5a9
3756 #define FBERCPT3 REGx(R0900_P1_FBERCPT3)
3757 #define F0900_P1_FBERMETER_CPT3 0xf5a900ff
3758 
3759 /*P1_FBERCPT2*/
3760 #define R0900_P1_FBERCPT2 0xf5aa
3761 #define FBERCPT2 REGx(R0900_P1_FBERCPT2)
3762 #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
3763 
3764 /*P1_FBERCPT1*/
3765 #define R0900_P1_FBERCPT1 0xf5ab
3766 #define FBERCPT1 REGx(R0900_P1_FBERCPT1)
3767 #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
3768 
3769 /*P1_FBERCPT0*/
3770 #define R0900_P1_FBERCPT0 0xf5ac
3771 #define FBERCPT0 REGx(R0900_P1_FBERCPT0)
3772 #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
3773 
3774 /*P1_FBERERR2*/
3775 #define R0900_P1_FBERERR2 0xf5ad
3776 #define FBERERR2 REGx(R0900_P1_FBERERR2)
3777 #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
3778 
3779 /*P1_FBERERR1*/
3780 #define R0900_P1_FBERERR1 0xf5ae
3781 #define FBERERR1 REGx(R0900_P1_FBERERR1)
3782 #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
3783 
3784 /*P1_FBERERR0*/
3785 #define R0900_P1_FBERERR0 0xf5af
3786 #define FBERERR0 REGx(R0900_P1_FBERERR0)
3787 #define F0900_P1_FBERMETER_ERR0 0xf5af00ff
3788 
3789 /*P1_FSPYBER*/
3790 #define R0900_P1_FSPYBER 0xf5b2
3791 #define FSPYBER REGx(R0900_P1_FSPYBER)
3792 #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
3793 #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
3794 #define F0900_P1_FSPYBER_CTIME 0xf5b20007
3795 
3796 /*RCCFG2*/
3797 #define R0900_RCCFG2 0xf600
3798 
3799 /*TSGENERAL*/
3800 #define R0900_TSGENERAL 0xf630
3801 #define F0900_TSFIFO_DISTS2PAR 0xf6300040
3802 #define F0900_MUXSTREAM_OUTMODE 0xf6300008
3803 #define F0900_TSFIFO_PERMPARAL 0xf6300006
3804 
3805 /*TSGENERAL1X*/
3806 #define R0900_TSGENERAL1X 0xf670
3807 
3808 /*NBITER_NF4*/
3809 #define R0900_NBITER_NF4 0xfa03
3810 #define F0900_NBITER_NF_QP_1_2 0xfa0300ff
3811 
3812 /*NBITER_NF5*/
3813 #define R0900_NBITER_NF5 0xfa04
3814 #define F0900_NBITER_NF_QP_3_5 0xfa0400ff
3815 
3816 /*NBITER_NF6*/
3817 #define R0900_NBITER_NF6 0xfa05
3818 #define F0900_NBITER_NF_QP_2_3 0xfa0500ff
3819 
3820 /*NBITER_NF7*/
3821 #define R0900_NBITER_NF7 0xfa06
3822 #define F0900_NBITER_NF_QP_3_4 0xfa0600ff
3823 
3824 /*NBITER_NF8*/
3825 #define R0900_NBITER_NF8 0xfa07
3826 #define F0900_NBITER_NF_QP_4_5 0xfa0700ff
3827 
3828 /*NBITER_NF9*/
3829 #define R0900_NBITER_NF9 0xfa08
3830 #define F0900_NBITER_NF_QP_5_6 0xfa0800ff
3831 
3832 /*NBITER_NF10*/
3833 #define R0900_NBITER_NF10 0xfa09
3834 #define F0900_NBITER_NF_QP_8_9 0xfa0900ff
3835 
3836 /*NBITER_NF11*/
3837 #define R0900_NBITER_NF11 0xfa0a
3838 #define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
3839 
3840 /*NBITER_NF12*/
3841 #define R0900_NBITER_NF12 0xfa0b
3842 #define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
3843 
3844 /*NBITER_NF13*/
3845 #define R0900_NBITER_NF13 0xfa0c
3846 #define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
3847 
3848 /*NBITER_NF14*/
3849 #define R0900_NBITER_NF14 0xfa0d
3850 #define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
3851 
3852 /*NBITER_NF15*/
3853 #define R0900_NBITER_NF15 0xfa0e
3854 #define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
3855 
3856 /*NBITER_NF16*/
3857 #define R0900_NBITER_NF16 0xfa0f
3858 #define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
3859 
3860 /*NBITER_NF17*/
3861 #define R0900_NBITER_NF17 0xfa10
3862 #define F0900_NBITER_NF_8P_9_10 0xfa1000ff
3863 
3864 /*NBITERNOERR*/
3865 #define R0900_NBITERNOERR 0xfa3f
3866 #define F0900_NBITER_STOP_CRIT 0xfa3f000f
3867 
3868 /*GAINLLR_NF4*/
3869 #define R0900_GAINLLR_NF4 0xfa43
3870 #define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
3871 
3872 /*GAINLLR_NF5*/
3873 #define R0900_GAINLLR_NF5 0xfa44
3874 #define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
3875 
3876 /*GAINLLR_NF6*/
3877 #define R0900_GAINLLR_NF6 0xfa45
3878 #define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
3879 
3880 /*GAINLLR_NF7*/
3881 #define R0900_GAINLLR_NF7 0xfa46
3882 #define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
3883 
3884 /*GAINLLR_NF8*/
3885 #define R0900_GAINLLR_NF8 0xfa47
3886 #define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
3887 
3888 /*GAINLLR_NF9*/
3889 #define R0900_GAINLLR_NF9 0xfa48
3890 #define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
3891 
3892 /*GAINLLR_NF10*/
3893 #define R0900_GAINLLR_NF10 0xfa49
3894 #define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
3895 
3896 /*GAINLLR_NF11*/
3897 #define R0900_GAINLLR_NF11 0xfa4a
3898 #define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
3899 
3900 /*GAINLLR_NF12*/
3901 #define R0900_GAINLLR_NF12 0xfa4b
3902 #define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
3903 
3904 /*GAINLLR_NF13*/
3905 #define R0900_GAINLLR_NF13 0xfa4c
3906 #define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
3907 
3908 /*GAINLLR_NF14*/
3909 #define R0900_GAINLLR_NF14 0xfa4d
3910 #define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
3911 
3912 /*GAINLLR_NF15*/
3913 #define R0900_GAINLLR_NF15 0xfa4e
3914 #define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
3915 
3916 /*GAINLLR_NF16*/
3917 #define R0900_GAINLLR_NF16 0xfa4f
3918 #define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
3919 
3920 /*GAINLLR_NF17*/
3921 #define R0900_GAINLLR_NF17 0xfa50
3922 #define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
3923 
3924 /*CFGEXT*/
3925 #define R0900_CFGEXT 0xfa80
3926 #define F0900_STAGMODE 0xfa800080
3927 #define F0900_BYPBCH 0xfa800040
3928 #define F0900_BYPLDPC 0xfa800020
3929 #define F0900_LDPCMODE 0xfa800010
3930 #define F0900_INVLLRSIGN 0xfa800008
3931 #define F0900_SHORTMULT 0xfa800004
3932 #define F0900_EXTERNTX 0xfa800001
3933 
3934 /*GENCFG*/
3935 #define R0900_GENCFG 0xfa86
3936 #define F0900_BROADCAST 0xfa860010
3937 #define F0900_PRIORITY 0xfa860002
3938 #define F0900_DDEMOD 0xfa860001
3939 
3940 /*LDPCERR1*/
3941 #define R0900_LDPCERR1 0xfa96
3942 #define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
3943 
3944 /*LDPCERR0*/
3945 #define R0900_LDPCERR0 0xfa97
3946 #define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
3947 
3948 /*BCHERR*/
3949 #define R0900_BCHERR 0xfa98
3950 #define F0900_ERRORFLAG 0xfa980010
3951 #define F0900_BCH_ERRORS_COUNTER 0xfa98000f
3952 
3953 /*TSTRES0*/
3954 #define R0900_TSTRES0 0xff11
3955 #define F0900_FRESFEC 0xff110080
3956 
3957 /*P2_TCTL4*/
3958 #define R0900_P2_TCTL4 0xff28
3959 #define F0900_P2_PN4_SELECT 0xff280020
3960 
3961 /*P1_TCTL4*/
3962 #define R0900_P1_TCTL4 0xff48
3963 #define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
3964 #define F0900_P1_PN4_SELECT 0xff480020
3965 
3966 /*P2_TSTDISRX*/
3967 #define R0900_P2_TSTDISRX 0xff65
3968 #define F0900_P2_PIN_SELECT1 0xff650008
3969 
3970 /*P1_TSTDISRX*/
3971 #define R0900_P1_TSTDISRX 0xff67
3972 #define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
3973 #define F0900_P1_PIN_SELECT1 0xff670008
3974 #define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
3975 
3976 #define STV0900_NBREGS 723
3977 #define STV0900_NBFIELDS 1420
3978 
3979 #endif
3980 
3981