1 /* 2 * Copyright (C) 2014 Renesas Solutions Corp. 3 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 */ 9 10 #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ 11 #define __DT_BINDINGS_CLOCK_R7S72100_H__ 12 13 #define R7S72100_CLK_PLL 0 14 #define R7S72100_CLK_I 1 15 #define R7S72100_CLK_G 2 16 17 /* MSTP2 */ 18 #define R7S72100_CLK_CORESIGHT 0 19 20 /* MSTP3 */ 21 #define R7S72100_CLK_IEBUS 7 22 #define R7S72100_CLK_IRDA 6 23 #define R7S72100_CLK_LIN0 5 24 #define R7S72100_CLK_LIN1 4 25 #define R7S72100_CLK_MTU2 3 26 #define R7S72100_CLK_CAN 2 27 #define R7S72100_CLK_ADCPWR 1 28 #define R7S72100_CLK_PWM 0 29 30 /* MSTP4 */ 31 #define R7S72100_CLK_SCIF0 7 32 #define R7S72100_CLK_SCIF1 6 33 #define R7S72100_CLK_SCIF2 5 34 #define R7S72100_CLK_SCIF3 4 35 #define R7S72100_CLK_SCIF4 3 36 #define R7S72100_CLK_SCIF5 2 37 #define R7S72100_CLK_SCIF6 1 38 #define R7S72100_CLK_SCIF7 0 39 40 /* MSTP5 */ 41 #define R7S72100_CLK_SCI0 7 42 #define R7S72100_CLK_SCI1 6 43 #define R7S72100_CLK_SG0 5 44 #define R7S72100_CLK_SG1 4 45 #define R7S72100_CLK_SG2 3 46 #define R7S72100_CLK_SG3 2 47 #define R7S72100_CLK_OSTM0 1 48 #define R7S72100_CLK_OSTM1 0 49 50 /* MSTP6 */ 51 #define R7S72100_CLK_ADC 7 52 #define R7S72100_CLK_CEU 6 53 #define R7S72100_CLK_DOC0 5 54 #define R7S72100_CLK_DOC1 4 55 #define R7S72100_CLK_DRC0 3 56 #define R7S72100_CLK_DRC1 2 57 #define R7S72100_CLK_JCU 1 58 #define R7S72100_CLK_RTC 0 59 60 /* MSTP7 */ 61 #define R7S72100_CLK_VDEC0 7 62 #define R7S72100_CLK_VDEC1 6 63 #define R7S72100_CLK_ETHER 4 64 #define R7S72100_CLK_NAND 3 65 #define R7S72100_CLK_USB0 1 66 #define R7S72100_CLK_USB1 0 67 68 /* MSTP8 */ 69 #define R7S72100_CLK_IMR0 7 70 #define R7S72100_CLK_IMR1 6 71 #define R7S72100_CLK_IMRDISP 5 72 #define R7S72100_CLK_MMCIF 4 73 #define R7S72100_CLK_MLB 3 74 #define R7S72100_CLK_ETHAVB 2 75 #define R7S72100_CLK_SCUX 1 76 77 /* MSTP9 */ 78 #define R7S72100_CLK_I2C0 7 79 #define R7S72100_CLK_I2C1 6 80 #define R7S72100_CLK_I2C2 5 81 #define R7S72100_CLK_I2C3 4 82 #define R7S72100_CLK_SPIBSC0 3 83 #define R7S72100_CLK_SPIBSC1 2 84 #define R7S72100_CLK_VDC50 1 /* and LVDS */ 85 #define R7S72100_CLK_VDC51 0 86 87 /* MSTP10 */ 88 #define R7S72100_CLK_SPI0 7 89 #define R7S72100_CLK_SPI1 6 90 #define R7S72100_CLK_SPI2 5 91 #define R7S72100_CLK_SPI3 4 92 #define R7S72100_CLK_SPI4 3 93 #define R7S72100_CLK_CDROM 2 94 #define R7S72100_CLK_SPDIF 1 95 #define R7S72100_CLK_RGPVG2 0 96 97 /* MSTP11 */ 98 #define R7S72100_CLK_SSI0 5 99 #define R7S72100_CLK_SSI1 4 100 #define R7S72100_CLK_SSI2 3 101 #define R7S72100_CLK_SSI3 2 102 #define R7S72100_CLK_SSI4 1 103 #define R7S72100_CLK_SSI5 0 104 105 /* MSTP12 */ 106 #define R7S72100_CLK_SDHI00 3 107 #define R7S72100_CLK_SDHI01 2 108 #define R7S72100_CLK_SDHI10 1 109 #define R7S72100_CLK_SDHI11 0 110 111 /* MSTP13 */ 112 #define R7S72100_CLK_PIX1 2 113 #define R7S72100_CLK_PIX0 1 114 115 #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ 116