1 /*
2 * Core driver interface to access RICOH_RC5T583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #ifndef __LINUX_MFD_RC5T583_H
25 #define __LINUX_MFD_RC5T583_H
26
27 #include <linux/mutex.h>
28 #include <linux/types.h>
29 #include <linux/regmap.h>
30
31 /* Maximum number of main interrupts */
32 #define MAX_MAIN_INTERRUPT 5
33 #define RC5T583_MAX_GPEDGE_REG 2
34 #define RC5T583_MAX_INTERRUPT_EN_REGS 8
35 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9
36
37 /* Interrupt enable register */
38 #define RC5T583_INT_EN_SYS1 0x19
39 #define RC5T583_INT_EN_SYS2 0x1D
40 #define RC5T583_INT_EN_DCDC 0x41
41 #define RC5T583_INT_EN_RTC 0xED
42 #define RC5T583_INT_EN_ADC1 0x90
43 #define RC5T583_INT_EN_ADC2 0x91
44 #define RC5T583_INT_EN_ADC3 0x92
45
46 /* Interrupt status registers (monitor regs in Ricoh)*/
47 #define RC5T583_INTC_INTPOL 0xAD
48 #define RC5T583_INTC_INTEN 0xAE
49 #define RC5T583_INTC_INTMON 0xAF
50
51 #define RC5T583_INT_MON_GRP 0xAF
52 #define RC5T583_INT_MON_SYS1 0x1B
53 #define RC5T583_INT_MON_SYS2 0x1F
54 #define RC5T583_INT_MON_DCDC 0x43
55 #define RC5T583_INT_MON_RTC 0xEE
56
57 /* Interrupt clearing registers */
58 #define RC5T583_INT_IR_SYS1 0x1A
59 #define RC5T583_INT_IR_SYS2 0x1E
60 #define RC5T583_INT_IR_DCDC 0x42
61 #define RC5T583_INT_IR_RTC 0xEE
62 #define RC5T583_INT_IR_ADCL 0x94
63 #define RC5T583_INT_IR_ADCH 0x95
64 #define RC5T583_INT_IR_ADCEND 0x96
65 #define RC5T583_INT_IR_GPIOR 0xA9
66 #define RC5T583_INT_IR_GPIOF 0xAA
67
68 /* Sleep sequence registers */
69 #define RC5T583_SLPSEQ1 0x21
70 #define RC5T583_SLPSEQ2 0x22
71 #define RC5T583_SLPSEQ3 0x23
72 #define RC5T583_SLPSEQ4 0x24
73 #define RC5T583_SLPSEQ5 0x25
74 #define RC5T583_SLPSEQ6 0x26
75 #define RC5T583_SLPSEQ7 0x27
76 #define RC5T583_SLPSEQ8 0x28
77 #define RC5T583_SLPSEQ9 0x29
78 #define RC5T583_SLPSEQ10 0x2A
79 #define RC5T583_SLPSEQ11 0x2B
80
81 /* Regulator registers */
82 #define RC5T583_REG_DC0CTL 0x30
83 #define RC5T583_REG_DC0DAC 0x31
84 #define RC5T583_REG_DC0LATCTL 0x32
85 #define RC5T583_REG_SR0CTL 0x33
86
87 #define RC5T583_REG_DC1CTL 0x34
88 #define RC5T583_REG_DC1DAC 0x35
89 #define RC5T583_REG_DC1LATCTL 0x36
90 #define RC5T583_REG_SR1CTL 0x37
91
92 #define RC5T583_REG_DC2CTL 0x38
93 #define RC5T583_REG_DC2DAC 0x39
94 #define RC5T583_REG_DC2LATCTL 0x3A
95 #define RC5T583_REG_SR2CTL 0x3B
96
97 #define RC5T583_REG_DC3CTL 0x3C
98 #define RC5T583_REG_DC3DAC 0x3D
99 #define RC5T583_REG_DC3LATCTL 0x3E
100 #define RC5T583_REG_SR3CTL 0x3F
101
102
103 #define RC5T583_REG_LDOEN1 0x50
104 #define RC5T583_REG_LDOEN2 0x51
105 #define RC5T583_REG_LDODIS1 0x52
106 #define RC5T583_REG_LDODIS2 0x53
107
108 #define RC5T583_REG_LDO0DAC 0x54
109 #define RC5T583_REG_LDO1DAC 0x55
110 #define RC5T583_REG_LDO2DAC 0x56
111 #define RC5T583_REG_LDO3DAC 0x57
112 #define RC5T583_REG_LDO4DAC 0x58
113 #define RC5T583_REG_LDO5DAC 0x59
114 #define RC5T583_REG_LDO6DAC 0x5A
115 #define RC5T583_REG_LDO7DAC 0x5B
116 #define RC5T583_REG_LDO8DAC 0x5C
117 #define RC5T583_REG_LDO9DAC 0x5D
118
119 #define RC5T583_REG_DC0DAC_DS 0x60
120 #define RC5T583_REG_DC1DAC_DS 0x61
121 #define RC5T583_REG_DC2DAC_DS 0x62
122 #define RC5T583_REG_DC3DAC_DS 0x63
123
124 #define RC5T583_REG_LDO0DAC_DS 0x64
125 #define RC5T583_REG_LDO1DAC_DS 0x65
126 #define RC5T583_REG_LDO2DAC_DS 0x66
127 #define RC5T583_REG_LDO3DAC_DS 0x67
128 #define RC5T583_REG_LDO4DAC_DS 0x68
129 #define RC5T583_REG_LDO5DAC_DS 0x69
130 #define RC5T583_REG_LDO6DAC_DS 0x6A
131 #define RC5T583_REG_LDO7DAC_DS 0x6B
132 #define RC5T583_REG_LDO8DAC_DS 0x6C
133 #define RC5T583_REG_LDO9DAC_DS 0x6D
134
135 /* GPIO register base address */
136 #define RC5T583_GPIO_IOSEL 0xA0
137 #define RC5T583_GPIO_PDEN 0xA1
138 #define RC5T583_GPIO_IOOUT 0xA2
139 #define RC5T583_GPIO_PGSEL 0xA3
140 #define RC5T583_GPIO_GPINV 0xA4
141 #define RC5T583_GPIO_GPDEB 0xA5
142 #define RC5T583_GPIO_GPEDGE1 0xA6
143 #define RC5T583_GPIO_GPEDGE2 0xA7
144 #define RC5T583_GPIO_EN_INT 0xA8
145 #define RC5T583_GPIO_MON_IOIN 0xAB
146 #define RC5T583_GPIO_GPOFUNC 0xAC
147
148 /* RTC registers */
149 #define RC5T583_RTC_SEC 0xE0
150 #define RC5T583_RTC_MIN 0xE1
151 #define RC5T583_RTC_HOUR 0xE2
152 #define RC5T583_RTC_WDAY 0xE3
153 #define RC5T583_RTC_DAY 0xE4
154 #define RC5T583_RTC_MONTH 0xE5
155 #define RC5T583_RTC_YEAR 0xE6
156 #define RC5T583_RTC_ADJ 0xE7
157 #define RC5T583_RTC_AW_MIN 0xE8
158 #define RC5T583_RTC_AW_HOUR 0xE9
159 #define RC5T583_RTC_AW_WEEK 0xEA
160 #define RC5T583_RTC_AD_MIN 0xEB
161 #define RC5T583_RTC_AD_HOUR 0xEC
162 #define RC5T583_RTC_CTL1 0xED
163 #define RC5T583_RTC_CTL2 0xEE
164 #define RC5T583_RTC_AY_MIN 0xF0
165 #define RC5T583_RTC_AY_HOUR 0xF1
166 #define RC5T583_RTC_AY_DAY 0xF2
167 #define RC5T583_RTC_AY_MONTH 0xF3
168 #define RC5T583_RTC_AY_YEAR 0xF4
169
170 #define RC5T583_MAX_REG 0xF7
171 #define RC5T583_NUM_REGS (RC5T583_MAX_REG + 1)
172
173 /* RICOH_RC5T583 IRQ definitions */
174 enum {
175 RC5T583_IRQ_ONKEY,
176 RC5T583_IRQ_ACOK,
177 RC5T583_IRQ_LIDOPEN,
178 RC5T583_IRQ_PREOT,
179 RC5T583_IRQ_CLKSTP,
180 RC5T583_IRQ_ONKEY_OFF,
181 RC5T583_IRQ_WD,
182 RC5T583_IRQ_EN_PWRREQ1,
183 RC5T583_IRQ_EN_PWRREQ2,
184 RC5T583_IRQ_PRE_VINDET,
185
186 RC5T583_IRQ_DC0LIM,
187 RC5T583_IRQ_DC1LIM,
188 RC5T583_IRQ_DC2LIM,
189 RC5T583_IRQ_DC3LIM,
190
191 RC5T583_IRQ_CTC,
192 RC5T583_IRQ_YALE,
193 RC5T583_IRQ_DALE,
194 RC5T583_IRQ_WALE,
195
196 RC5T583_IRQ_AIN1L,
197 RC5T583_IRQ_AIN2L,
198 RC5T583_IRQ_AIN3L,
199 RC5T583_IRQ_VBATL,
200 RC5T583_IRQ_VIN3L,
201 RC5T583_IRQ_VIN8L,
202 RC5T583_IRQ_AIN1H,
203 RC5T583_IRQ_AIN2H,
204 RC5T583_IRQ_AIN3H,
205 RC5T583_IRQ_VBATH,
206 RC5T583_IRQ_VIN3H,
207 RC5T583_IRQ_VIN8H,
208 RC5T583_IRQ_ADCEND,
209
210 RC5T583_IRQ_GPIO0,
211 RC5T583_IRQ_GPIO1,
212 RC5T583_IRQ_GPIO2,
213 RC5T583_IRQ_GPIO3,
214 RC5T583_IRQ_GPIO4,
215 RC5T583_IRQ_GPIO5,
216 RC5T583_IRQ_GPIO6,
217 RC5T583_IRQ_GPIO7,
218
219 /* Should be last entry */
220 RC5T583_MAX_IRQS,
221 };
222
223 /* Ricoh583 gpio definitions */
224 enum {
225 RC5T583_GPIO0,
226 RC5T583_GPIO1,
227 RC5T583_GPIO2,
228 RC5T583_GPIO3,
229 RC5T583_GPIO4,
230 RC5T583_GPIO5,
231 RC5T583_GPIO6,
232 RC5T583_GPIO7,
233
234 /* Should be last entry */
235 RC5T583_MAX_GPIO,
236 };
237
238 enum {
239 RC5T583_DS_NONE,
240 RC5T583_DS_DC0,
241 RC5T583_DS_DC1,
242 RC5T583_DS_DC2,
243 RC5T583_DS_DC3,
244 RC5T583_DS_LDO0,
245 RC5T583_DS_LDO1,
246 RC5T583_DS_LDO2,
247 RC5T583_DS_LDO3,
248 RC5T583_DS_LDO4,
249 RC5T583_DS_LDO5,
250 RC5T583_DS_LDO6,
251 RC5T583_DS_LDO7,
252 RC5T583_DS_LDO8,
253 RC5T583_DS_LDO9,
254 RC5T583_DS_PSO0,
255 RC5T583_DS_PSO1,
256 RC5T583_DS_PSO2,
257 RC5T583_DS_PSO3,
258 RC5T583_DS_PSO4,
259 RC5T583_DS_PSO5,
260 RC5T583_DS_PSO6,
261 RC5T583_DS_PSO7,
262
263 /* Should be last entry */
264 RC5T583_DS_MAX,
265 };
266
267 /*
268 * Ricoh pmic RC5T583 supports sleep through two external controls.
269 * The output of gpios and regulator can be enable/disable through
270 * this external signals.
271 */
272 enum {
273 RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
274 RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
275 };
276
277 enum {
278 RC5T583_REGULATOR_DC0,
279 RC5T583_REGULATOR_DC1,
280 RC5T583_REGULATOR_DC2,
281 RC5T583_REGULATOR_DC3,
282 RC5T583_REGULATOR_LDO0,
283 RC5T583_REGULATOR_LDO1,
284 RC5T583_REGULATOR_LDO2,
285 RC5T583_REGULATOR_LDO3,
286 RC5T583_REGULATOR_LDO4,
287 RC5T583_REGULATOR_LDO5,
288 RC5T583_REGULATOR_LDO6,
289 RC5T583_REGULATOR_LDO7,
290 RC5T583_REGULATOR_LDO8,
291 RC5T583_REGULATOR_LDO9,
292
293 /* Should be last entry */
294 RC5T583_REGULATOR_MAX,
295 };
296
297 struct rc5t583 {
298 struct device *dev;
299 struct regmap *regmap;
300 int chip_irq;
301 int irq_base;
302 struct mutex irq_lock;
303 unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
304
305 /* For main interrupt bits in INTC */
306 uint8_t intc_inten_reg;
307
308 /* For group interrupt bits and address */
309 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];
310
311 /* For gpio edge */
312 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
313 };
314
315 /*
316 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
317 * The board specific data is provided through this structure.
318 * @irq_base: Irq base number on which this device registers their interrupts.
319 * @gpio_base: GPIO base from which gpio of this device will start.
320 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
321 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
322 * in device sleep mode.
323 * @regulator_ext_pwr_control: External power request regulator control. The
324 * regulator output enable/disable is controlled by the external
325 * power request input state.
326 * @reg_init_data: Regulator init data.
327 */
328
329 struct rc5t583_platform_data {
330 int irq_base;
331 int gpio_base;
332 bool enable_shutdown;
333 int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
334 unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
335 struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
336 };
337
rc5t583_write(struct device * dev,uint8_t reg,uint8_t val)338 static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
339 {
340 struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
341 return regmap_write(rc5t583->regmap, reg, val);
342 }
343
rc5t583_read(struct device * dev,uint8_t reg,uint8_t * val)344 static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
345 {
346 struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
347 unsigned int ival;
348 int ret;
349 ret = regmap_read(rc5t583->regmap, reg, &ival);
350 if (!ret)
351 *val = (uint8_t)ival;
352 return ret;
353 }
354
rc5t583_set_bits(struct device * dev,unsigned int reg,unsigned int bit_mask)355 static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
356 unsigned int bit_mask)
357 {
358 struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
359 return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
360 }
361
rc5t583_clear_bits(struct device * dev,unsigned int reg,unsigned int bit_mask)362 static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
363 unsigned int bit_mask)
364 {
365 struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
366 return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
367 }
368
rc5t583_update(struct device * dev,unsigned int reg,unsigned int val,unsigned int mask)369 static inline int rc5t583_update(struct device *dev, unsigned int reg,
370 unsigned int val, unsigned int mask)
371 {
372 struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
373 return regmap_update_bits(rc5t583->regmap, reg, mask, val);
374 }
375
376 int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
377 int ext_pwr_req, int deepsleep_slot_nr);
378 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
379 int rc5t583_irq_exit(struct rc5t583 *rc5t583);
380
381 #endif
382