1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * This is i.MX low power i2c controller driver.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/errno.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26
27 #define DRIVER_NAME "imx-lpi2c"
28
29 #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */
30 #define LPI2C_MCR 0x10 /* i2c contrl register */
31 #define LPI2C_MSR 0x14 /* i2c status register */
32 #define LPI2C_MIER 0x18 /* i2c interrupt enable */
33 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */
34 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */
35 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */
36 #define LPI2C_MCFGR3 0x2C /* i2c master configuration */
37 #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */
38 #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */
39 #define LPI2C_MFCR 0x58 /* i2c master FIFO control */
40 #define LPI2C_MFSR 0x5C /* i2c master FIFO status */
41 #define LPI2C_MTDR 0x60 /* i2c master TX data register */
42 #define LPI2C_MRDR 0x70 /* i2c master RX data register */
43
44 /* i2c command */
45 #define TRAN_DATA 0X00
46 #define RECV_DATA 0X01
47 #define GEN_STOP 0X02
48 #define RECV_DISCARD 0X03
49 #define GEN_START 0X04
50 #define START_NACK 0X05
51 #define START_HIGH 0X06
52 #define START_HIGH_NACK 0X07
53
54 #define MCR_MEN BIT(0)
55 #define MCR_RST BIT(1)
56 #define MCR_DOZEN BIT(2)
57 #define MCR_DBGEN BIT(3)
58 #define MCR_RTF BIT(8)
59 #define MCR_RRF BIT(9)
60 #define MSR_TDF BIT(0)
61 #define MSR_RDF BIT(1)
62 #define MSR_SDF BIT(9)
63 #define MSR_NDF BIT(10)
64 #define MSR_ALF BIT(11)
65 #define MSR_MBF BIT(24)
66 #define MSR_BBF BIT(25)
67 #define MIER_TDIE BIT(0)
68 #define MIER_RDIE BIT(1)
69 #define MIER_SDIE BIT(9)
70 #define MIER_NDIE BIT(10)
71 #define MCFGR1_AUTOSTOP BIT(8)
72 #define MCFGR1_IGNACK BIT(9)
73 #define MRDR_RXEMPTY BIT(14)
74
75 #define I2C_CLK_RATIO 2
76 #define CHUNK_DATA 256
77
78 #define LPI2C_DEFAULT_RATE 100000
79 #define STARDARD_MAX_BITRATE 400000
80 #define FAST_MAX_BITRATE 1000000
81 #define FAST_PLUS_MAX_BITRATE 3400000
82 #define HIGHSPEED_MAX_BITRATE 5000000
83
84 #define I2C_PM_TIMEOUT 10 /* ms */
85
86 enum lpi2c_imx_mode {
87 STANDARD, /* 100+Kbps */
88 FAST, /* 400+Kbps */
89 FAST_PLUS, /* 1.0+Mbps */
90 HS, /* 3.4+Mbps */
91 ULTRA_FAST, /* 5.0+Mbps */
92 };
93
94 enum lpi2c_imx_pincfg {
95 TWO_PIN_OD,
96 TWO_PIN_OO,
97 TWO_PIN_PP,
98 FOUR_PIN_PP,
99 };
100
101 struct lpi2c_imx_struct {
102 struct i2c_adapter adapter;
103 struct clk *clk;
104 void __iomem *base;
105 __u8 *rx_buf;
106 __u8 *tx_buf;
107 struct completion complete;
108 unsigned int msglen;
109 unsigned int delivered;
110 unsigned int block_data;
111 unsigned int bitrate;
112 unsigned int txfifosize;
113 unsigned int rxfifosize;
114 enum lpi2c_imx_mode mode;
115 };
116
lpi2c_imx_intctrl(struct lpi2c_imx_struct * lpi2c_imx,unsigned int enable)117 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
118 unsigned int enable)
119 {
120 writel(enable, lpi2c_imx->base + LPI2C_MIER);
121 }
122
lpi2c_imx_bus_busy(struct lpi2c_imx_struct * lpi2c_imx)123 static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
124 {
125 unsigned long orig_jiffies = jiffies;
126 unsigned int temp;
127
128 while (1) {
129 temp = readl(lpi2c_imx->base + LPI2C_MSR);
130
131 /* check for arbitration lost, clear if set */
132 if (temp & MSR_ALF) {
133 writel(temp, lpi2c_imx->base + LPI2C_MSR);
134 return -EAGAIN;
135 }
136
137 if (temp & (MSR_BBF | MSR_MBF))
138 break;
139
140 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
141 dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
142 return -ETIMEDOUT;
143 }
144 schedule();
145 }
146
147 return 0;
148 }
149
lpi2c_imx_set_mode(struct lpi2c_imx_struct * lpi2c_imx)150 static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
151 {
152 unsigned int bitrate = lpi2c_imx->bitrate;
153 enum lpi2c_imx_mode mode;
154
155 if (bitrate < STARDARD_MAX_BITRATE)
156 mode = STANDARD;
157 else if (bitrate < FAST_MAX_BITRATE)
158 mode = FAST;
159 else if (bitrate < FAST_PLUS_MAX_BITRATE)
160 mode = FAST_PLUS;
161 else if (bitrate < HIGHSPEED_MAX_BITRATE)
162 mode = HS;
163 else
164 mode = ULTRA_FAST;
165
166 lpi2c_imx->mode = mode;
167 }
168
lpi2c_imx_start(struct lpi2c_imx_struct * lpi2c_imx,struct i2c_msg * msgs)169 static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
170 struct i2c_msg *msgs)
171 {
172 unsigned int temp;
173
174 temp = readl(lpi2c_imx->base + LPI2C_MCR);
175 temp |= MCR_RRF | MCR_RTF;
176 writel(temp, lpi2c_imx->base + LPI2C_MCR);
177 writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
178
179 temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8);
180 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
181
182 return lpi2c_imx_bus_busy(lpi2c_imx);
183 }
184
lpi2c_imx_stop(struct lpi2c_imx_struct * lpi2c_imx)185 static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
186 {
187 unsigned long orig_jiffies = jiffies;
188 unsigned int temp;
189
190 writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
191
192 do {
193 temp = readl(lpi2c_imx->base + LPI2C_MSR);
194 if (temp & MSR_SDF)
195 break;
196
197 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
198 dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
199 break;
200 }
201 schedule();
202
203 } while (1);
204 }
205
206 /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
lpi2c_imx_config(struct lpi2c_imx_struct * lpi2c_imx)207 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
208 {
209 u8 prescale, filt, sethold, datavd;
210 unsigned int clk_rate, clk_cycle, clkhi, clklo;
211 enum lpi2c_imx_pincfg pincfg;
212 unsigned int temp;
213
214 lpi2c_imx_set_mode(lpi2c_imx);
215
216 clk_rate = clk_get_rate(lpi2c_imx->clk);
217 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
218 filt = 0;
219 else
220 filt = 2;
221
222 for (prescale = 0; prescale <= 7; prescale++) {
223 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
224 - 3 - (filt >> 1);
225 clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
226 clklo = clk_cycle - clkhi;
227 if (clklo < 64)
228 break;
229 }
230
231 if (prescale > 7)
232 return -EINVAL;
233
234 /* set MCFGR1: PINCFG, PRESCALE, IGNACK */
235 if (lpi2c_imx->mode == ULTRA_FAST)
236 pincfg = TWO_PIN_OO;
237 else
238 pincfg = TWO_PIN_OD;
239 temp = prescale | pincfg << 24;
240
241 if (lpi2c_imx->mode == ULTRA_FAST)
242 temp |= MCFGR1_IGNACK;
243
244 writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
245
246 /* set MCFGR2: FILTSDA, FILTSCL */
247 temp = (filt << 16) | (filt << 24);
248 writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
249
250 /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */
251 sethold = clkhi;
252 datavd = clkhi >> 1;
253 temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo;
254
255 if (lpi2c_imx->mode == HS)
256 writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
257 else
258 writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
259
260 return 0;
261 }
262
lpi2c_imx_master_enable(struct lpi2c_imx_struct * lpi2c_imx)263 static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
264 {
265 unsigned int temp;
266 int ret;
267
268 ret = pm_runtime_get_sync(lpi2c_imx->adapter.dev.parent);
269 if (ret < 0)
270 return ret;
271
272 temp = MCR_RST;
273 writel(temp, lpi2c_imx->base + LPI2C_MCR);
274 writel(0, lpi2c_imx->base + LPI2C_MCR);
275
276 ret = lpi2c_imx_config(lpi2c_imx);
277 if (ret)
278 goto rpm_put;
279
280 temp = readl(lpi2c_imx->base + LPI2C_MCR);
281 temp |= MCR_MEN;
282 writel(temp, lpi2c_imx->base + LPI2C_MCR);
283
284 return 0;
285
286 rpm_put:
287 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
288 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
289
290 return ret;
291 }
292
lpi2c_imx_master_disable(struct lpi2c_imx_struct * lpi2c_imx)293 static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx)
294 {
295 u32 temp;
296
297 temp = readl(lpi2c_imx->base + LPI2C_MCR);
298 temp &= ~MCR_MEN;
299 writel(temp, lpi2c_imx->base + LPI2C_MCR);
300
301 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
302 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
303
304 return 0;
305 }
306
lpi2c_imx_msg_complete(struct lpi2c_imx_struct * lpi2c_imx)307 static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
308 {
309 unsigned long timeout;
310
311 timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ);
312
313 return timeout ? 0 : -ETIMEDOUT;
314 }
315
lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct * lpi2c_imx)316 static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx)
317 {
318 unsigned long orig_jiffies = jiffies;
319 u32 txcnt;
320
321 do {
322 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
323
324 if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) {
325 dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n");
326 return -EIO;
327 }
328
329 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
330 dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n");
331 return -ETIMEDOUT;
332 }
333 schedule();
334
335 } while (txcnt);
336
337 return 0;
338 }
339
lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct * lpi2c_imx)340 static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
341 {
342 writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
343 }
344
lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct * lpi2c_imx)345 static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
346 {
347 unsigned int temp, remaining;
348
349 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
350
351 if (remaining > (lpi2c_imx->rxfifosize >> 1))
352 temp = lpi2c_imx->rxfifosize >> 1;
353 else
354 temp = 0;
355
356 writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
357 }
358
lpi2c_imx_write_txfifo(struct lpi2c_imx_struct * lpi2c_imx)359 static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx)
360 {
361 unsigned int data, txcnt;
362
363 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
364
365 while (txcnt < lpi2c_imx->txfifosize) {
366 if (lpi2c_imx->delivered == lpi2c_imx->msglen)
367 break;
368
369 data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++];
370 writel(data, lpi2c_imx->base + LPI2C_MTDR);
371 txcnt++;
372 }
373
374 if (lpi2c_imx->delivered < lpi2c_imx->msglen)
375 lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE);
376 else
377 complete(&lpi2c_imx->complete);
378 }
379
lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct * lpi2c_imx)380 static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx)
381 {
382 unsigned int blocklen, remaining;
383 unsigned int temp, data;
384
385 do {
386 data = readl(lpi2c_imx->base + LPI2C_MRDR);
387 if (data & MRDR_RXEMPTY)
388 break;
389
390 lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff;
391 } while (1);
392
393 /*
394 * First byte is the length of remaining packet in the SMBus block
395 * data read. Add it to msgs->len.
396 */
397 if (lpi2c_imx->block_data) {
398 blocklen = lpi2c_imx->rx_buf[0];
399 lpi2c_imx->msglen += blocklen;
400 }
401
402 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
403
404 if (!remaining) {
405 complete(&lpi2c_imx->complete);
406 return;
407 }
408
409 /* not finished, still waiting for rx data */
410 lpi2c_imx_set_rx_watermark(lpi2c_imx);
411
412 /* multiple receive commands */
413 if (lpi2c_imx->block_data) {
414 lpi2c_imx->block_data = 0;
415 temp = remaining;
416 temp |= (RECV_DATA << 8);
417 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
418 } else if (!(lpi2c_imx->delivered & 0xff)) {
419 temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1;
420 temp |= (RECV_DATA << 8);
421 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
422 }
423
424 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE);
425 }
426
lpi2c_imx_write(struct lpi2c_imx_struct * lpi2c_imx,struct i2c_msg * msgs)427 static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx,
428 struct i2c_msg *msgs)
429 {
430 lpi2c_imx->tx_buf = msgs->buf;
431 lpi2c_imx_set_tx_watermark(lpi2c_imx);
432 lpi2c_imx_write_txfifo(lpi2c_imx);
433 }
434
lpi2c_imx_read(struct lpi2c_imx_struct * lpi2c_imx,struct i2c_msg * msgs)435 static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx,
436 struct i2c_msg *msgs)
437 {
438 unsigned int temp;
439
440 lpi2c_imx->rx_buf = msgs->buf;
441 lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN;
442
443 lpi2c_imx_set_rx_watermark(lpi2c_imx);
444 temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1;
445 temp |= (RECV_DATA << 8);
446 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
447
448 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE);
449 }
450
lpi2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)451 static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
452 struct i2c_msg *msgs, int num)
453 {
454 struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter);
455 unsigned int temp;
456 int i, result;
457
458 result = lpi2c_imx_master_enable(lpi2c_imx);
459 if (result)
460 return result;
461
462 for (i = 0; i < num; i++) {
463 result = lpi2c_imx_start(lpi2c_imx, &msgs[i]);
464 if (result)
465 goto disable;
466
467 /* quick smbus */
468 if (num == 1 && msgs[0].len == 0)
469 goto stop;
470
471 lpi2c_imx->rx_buf = NULL;
472 lpi2c_imx->tx_buf = NULL;
473 lpi2c_imx->delivered = 0;
474 lpi2c_imx->msglen = msgs[i].len;
475 init_completion(&lpi2c_imx->complete);
476
477 if (msgs[i].flags & I2C_M_RD)
478 lpi2c_imx_read(lpi2c_imx, &msgs[i]);
479 else
480 lpi2c_imx_write(lpi2c_imx, &msgs[i]);
481
482 result = lpi2c_imx_msg_complete(lpi2c_imx);
483 if (result)
484 goto stop;
485
486 if (!(msgs[i].flags & I2C_M_RD)) {
487 result = lpi2c_imx_txfifo_empty(lpi2c_imx);
488 if (result)
489 goto stop;
490 }
491 }
492
493 stop:
494 lpi2c_imx_stop(lpi2c_imx);
495
496 temp = readl(lpi2c_imx->base + LPI2C_MSR);
497 if ((temp & MSR_NDF) && !result)
498 result = -EIO;
499
500 disable:
501 lpi2c_imx_master_disable(lpi2c_imx);
502
503 dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
504 (result < 0) ? "error" : "success msg",
505 (result < 0) ? result : num);
506
507 return (result < 0) ? result : num;
508 }
509
lpi2c_imx_isr(int irq,void * dev_id)510 static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
511 {
512 struct lpi2c_imx_struct *lpi2c_imx = dev_id;
513 unsigned int enabled;
514 unsigned int temp;
515
516 enabled = readl(lpi2c_imx->base + LPI2C_MIER);
517
518 lpi2c_imx_intctrl(lpi2c_imx, 0);
519 temp = readl(lpi2c_imx->base + LPI2C_MSR);
520 temp &= enabled;
521
522 if (temp & MSR_RDF)
523 lpi2c_imx_read_rxfifo(lpi2c_imx);
524
525 if (temp & MSR_TDF)
526 lpi2c_imx_write_txfifo(lpi2c_imx);
527
528 if (temp & MSR_NDF)
529 complete(&lpi2c_imx->complete);
530
531 return IRQ_HANDLED;
532 }
533
lpi2c_imx_func(struct i2c_adapter * adapter)534 static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
535 {
536 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
537 I2C_FUNC_SMBUS_READ_BLOCK_DATA;
538 }
539
540 static const struct i2c_algorithm lpi2c_imx_algo = {
541 .master_xfer = lpi2c_imx_xfer,
542 .functionality = lpi2c_imx_func,
543 };
544
545 static const struct of_device_id lpi2c_imx_of_match[] = {
546 { .compatible = "fsl,imx7ulp-lpi2c" },
547 { },
548 };
549 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
550
lpi2c_imx_probe(struct platform_device * pdev)551 static int lpi2c_imx_probe(struct platform_device *pdev)
552 {
553 struct lpi2c_imx_struct *lpi2c_imx;
554 struct resource *res;
555 unsigned int temp;
556 int irq, ret;
557
558 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL);
559 if (!lpi2c_imx)
560 return -ENOMEM;
561
562 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
563 lpi2c_imx->base = devm_ioremap_resource(&pdev->dev, res);
564 if (IS_ERR(lpi2c_imx->base))
565 return PTR_ERR(lpi2c_imx->base);
566
567 irq = platform_get_irq(pdev, 0);
568 if (irq < 0) {
569 dev_err(&pdev->dev, "can't get irq number\n");
570 return irq;
571 }
572
573 lpi2c_imx->adapter.owner = THIS_MODULE;
574 lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
575 lpi2c_imx->adapter.dev.parent = &pdev->dev;
576 lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
577 strlcpy(lpi2c_imx->adapter.name, pdev->name,
578 sizeof(lpi2c_imx->adapter.name));
579
580 lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
581 if (IS_ERR(lpi2c_imx->clk)) {
582 dev_err(&pdev->dev, "can't get I2C peripheral clock\n");
583 return PTR_ERR(lpi2c_imx->clk);
584 }
585
586 ret = of_property_read_u32(pdev->dev.of_node,
587 "clock-frequency", &lpi2c_imx->bitrate);
588 if (ret)
589 lpi2c_imx->bitrate = LPI2C_DEFAULT_RATE;
590
591 ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
592 pdev->name, lpi2c_imx);
593 if (ret) {
594 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
595 return ret;
596 }
597
598 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx);
599 platform_set_drvdata(pdev, lpi2c_imx);
600
601 ret = clk_prepare_enable(lpi2c_imx->clk);
602 if (ret) {
603 dev_err(&pdev->dev, "clk enable failed %d\n", ret);
604 return ret;
605 }
606
607 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
608 pm_runtime_use_autosuspend(&pdev->dev);
609 pm_runtime_get_noresume(&pdev->dev);
610 pm_runtime_set_active(&pdev->dev);
611 pm_runtime_enable(&pdev->dev);
612
613 temp = readl(lpi2c_imx->base + LPI2C_PARAM);
614 lpi2c_imx->txfifosize = 1 << (temp & 0x0f);
615 lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f);
616
617 ret = i2c_add_adapter(&lpi2c_imx->adapter);
618 if (ret)
619 goto rpm_disable;
620
621 pm_runtime_mark_last_busy(&pdev->dev);
622 pm_runtime_put_autosuspend(&pdev->dev);
623
624 dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n");
625
626 return 0;
627
628 rpm_disable:
629 pm_runtime_put(&pdev->dev);
630 pm_runtime_disable(&pdev->dev);
631 pm_runtime_dont_use_autosuspend(&pdev->dev);
632
633 return ret;
634 }
635
lpi2c_imx_remove(struct platform_device * pdev)636 static int lpi2c_imx_remove(struct platform_device *pdev)
637 {
638 struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev);
639
640 i2c_del_adapter(&lpi2c_imx->adapter);
641
642 pm_runtime_disable(&pdev->dev);
643 pm_runtime_dont_use_autosuspend(&pdev->dev);
644
645 return 0;
646 }
647
648 #ifdef CONFIG_PM_SLEEP
lpi2c_runtime_suspend(struct device * dev)649 static int lpi2c_runtime_suspend(struct device *dev)
650 {
651 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
652
653 clk_disable_unprepare(lpi2c_imx->clk);
654 pinctrl_pm_select_sleep_state(dev);
655
656 return 0;
657 }
658
lpi2c_runtime_resume(struct device * dev)659 static int lpi2c_runtime_resume(struct device *dev)
660 {
661 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
662 int ret;
663
664 pinctrl_pm_select_default_state(dev);
665 ret = clk_prepare_enable(lpi2c_imx->clk);
666 if (ret) {
667 dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
668 return ret;
669 }
670
671 return 0;
672 }
673
674 static const struct dev_pm_ops lpi2c_pm_ops = {
675 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
676 pm_runtime_force_resume)
677 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
678 lpi2c_runtime_resume, NULL)
679 };
680 #define IMX_LPI2C_PM (&lpi2c_pm_ops)
681 #else
682 #define IMX_LPI2C_PM NULL
683 #endif
684
685 static struct platform_driver lpi2c_imx_driver = {
686 .probe = lpi2c_imx_probe,
687 .remove = lpi2c_imx_remove,
688 .driver = {
689 .name = DRIVER_NAME,
690 .of_match_table = lpi2c_imx_of_match,
691 .pm = IMX_LPI2C_PM,
692 },
693 };
694
695 module_platform_driver(lpi2c_imx_driver);
696
697 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
698 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus");
699 MODULE_LICENSE("GPL");
700