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Searched refs:REG_CON0 (Results 1 – 1 of 1) sorted by relevance

/linux-4.19.296/drivers/clk/mediatek/
Dclk-pll.c24 #define REG_CON0 0 macro
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
123 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; in mtk_pll_set_rate_regs()
259 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
261 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
268 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
270 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
282 r = readl(pll->base_addr + REG_CON0); in mtk_pll_unprepare()
284 writel(r, pll->base_addr + REG_CON0); in mtk_pll_unprepare()
289 r = readl(pll->base_addr + REG_CON0); in mtk_pll_unprepare()
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