1 /* 2 * s2mpu02.h 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd 5 * http://www.samsung.com 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __LINUX_MFD_S2MPU02_H 20 #define __LINUX_MFD_S2MPU02_H 21 22 /* S2MPU02 registers */ 23 enum S2MPU02_reg { 24 S2MPU02_REG_ID, 25 S2MPU02_REG_INT1, 26 S2MPU02_REG_INT2, 27 S2MPU02_REG_INT3, 28 S2MPU02_REG_INT1M, 29 S2MPU02_REG_INT2M, 30 S2MPU02_REG_INT3M, 31 S2MPU02_REG_ST1, 32 S2MPU02_REG_ST2, 33 S2MPU02_REG_PWRONSRC, 34 S2MPU02_REG_OFFSRC, 35 S2MPU02_REG_BU_CHG, 36 S2MPU02_REG_RTCCTRL, 37 S2MPU02_REG_PMCTRL1, 38 S2MPU02_REG_RSVD1, 39 S2MPU02_REG_RSVD2, 40 S2MPU02_REG_RSVD3, 41 S2MPU02_REG_RSVD4, 42 S2MPU02_REG_RSVD5, 43 S2MPU02_REG_RSVD6, 44 S2MPU02_REG_RSVD7, 45 S2MPU02_REG_WRSTEN, 46 S2MPU02_REG_RSVD8, 47 S2MPU02_REG_RSVD9, 48 S2MPU02_REG_RSVD10, 49 S2MPU02_REG_B1CTRL1, 50 S2MPU02_REG_B1CTRL2, 51 S2MPU02_REG_B2CTRL1, 52 S2MPU02_REG_B2CTRL2, 53 S2MPU02_REG_B3CTRL1, 54 S2MPU02_REG_B3CTRL2, 55 S2MPU02_REG_B4CTRL1, 56 S2MPU02_REG_B4CTRL2, 57 S2MPU02_REG_B5CTRL1, 58 S2MPU02_REG_B5CTRL2, 59 S2MPU02_REG_B5CTRL3, 60 S2MPU02_REG_B5CTRL4, 61 S2MPU02_REG_B5CTRL5, 62 S2MPU02_REG_B6CTRL1, 63 S2MPU02_REG_B6CTRL2, 64 S2MPU02_REG_B7CTRL1, 65 S2MPU02_REG_B7CTRL2, 66 S2MPU02_REG_RAMP1, 67 S2MPU02_REG_RAMP2, 68 S2MPU02_REG_L1CTRL, 69 S2MPU02_REG_L2CTRL1, 70 S2MPU02_REG_L2CTRL2, 71 S2MPU02_REG_L2CTRL3, 72 S2MPU02_REG_L2CTRL4, 73 S2MPU02_REG_L3CTRL, 74 S2MPU02_REG_L4CTRL, 75 S2MPU02_REG_L5CTRL, 76 S2MPU02_REG_L6CTRL, 77 S2MPU02_REG_L7CTRL, 78 S2MPU02_REG_L8CTRL, 79 S2MPU02_REG_L9CTRL, 80 S2MPU02_REG_L10CTRL, 81 S2MPU02_REG_L11CTRL, 82 S2MPU02_REG_L12CTRL, 83 S2MPU02_REG_L13CTRL, 84 S2MPU02_REG_L14CTRL, 85 S2MPU02_REG_L15CTRL, 86 S2MPU02_REG_L16CTRL, 87 S2MPU02_REG_L17CTRL, 88 S2MPU02_REG_L18CTRL, 89 S2MPU02_REG_L19CTRL, 90 S2MPU02_REG_L20CTRL, 91 S2MPU02_REG_L21CTRL, 92 S2MPU02_REG_L22CTRL, 93 S2MPU02_REG_L23CTRL, 94 S2MPU02_REG_L24CTRL, 95 S2MPU02_REG_L25CTRL, 96 S2MPU02_REG_L26CTRL, 97 S2MPU02_REG_L27CTRL, 98 S2MPU02_REG_L28CTRL, 99 S2MPU02_REG_LDODSCH1, 100 S2MPU02_REG_LDODSCH2, 101 S2MPU02_REG_LDODSCH3, 102 S2MPU02_REG_LDODSCH4, 103 S2MPU02_REG_SELMIF, 104 S2MPU02_REG_RSVD11, 105 S2MPU02_REG_RSVD12, 106 S2MPU02_REG_RSVD13, 107 S2MPU02_REG_DVSSEL, 108 S2MPU02_REG_DVSPTR, 109 S2MPU02_REG_DVSDATA, 110 }; 111 112 /* S2MPU02 regulator ids */ 113 enum S2MPU02_regulators { 114 S2MPU02_LDO1, 115 S2MPU02_LDO2, 116 S2MPU02_LDO3, 117 S2MPU02_LDO4, 118 S2MPU02_LDO5, 119 S2MPU02_LDO6, 120 S2MPU02_LDO7, 121 S2MPU02_LDO8, 122 S2MPU02_LDO9, 123 S2MPU02_LDO10, 124 S2MPU02_LDO11, 125 S2MPU02_LDO12, 126 S2MPU02_LDO13, 127 S2MPU02_LDO14, 128 S2MPU02_LDO15, 129 S2MPU02_LDO16, 130 S2MPU02_LDO17, 131 S2MPU02_LDO18, 132 S2MPU02_LDO19, 133 S2MPU02_LDO20, 134 S2MPU02_LDO21, 135 S2MPU02_LDO22, 136 S2MPU02_LDO23, 137 S2MPU02_LDO24, 138 S2MPU02_LDO25, 139 S2MPU02_LDO26, 140 S2MPU02_LDO27, 141 S2MPU02_LDO28, 142 S2MPU02_BUCK1, 143 S2MPU02_BUCK2, 144 S2MPU02_BUCK3, 145 S2MPU02_BUCK4, 146 S2MPU02_BUCK5, 147 S2MPU02_BUCK6, 148 S2MPU02_BUCK7, 149 150 S2MPU02_REGULATOR_MAX, 151 }; 152 153 /* Regulator constraints for BUCKx */ 154 #define S2MPU02_BUCK1234_MIN_600MV 600000 155 #define S2MPU02_BUCK5_MIN_1081_25MV 1081250 156 #define S2MPU02_BUCK6_MIN_1700MV 1700000 157 #define S2MPU02_BUCK7_MIN_900MV 900000 158 159 #define S2MPU02_BUCK1234_STEP_6_25MV 6250 160 #define S2MPU02_BUCK5_STEP_6_25MV 6250 161 #define S2MPU02_BUCK6_STEP_2_50MV 2500 162 #define S2MPU02_BUCK7_STEP_6_25MV 6250 163 164 #define S2MPU02_BUCK1234_START_SEL 0x00 165 #define S2MPU02_BUCK5_START_SEL 0x4D 166 #define S2MPU02_BUCK6_START_SEL 0x28 167 #define S2MPU02_BUCK7_START_SEL 0x30 168 169 #define S2MPU02_BUCK_RAMP_DELAY 12500 170 171 /* Regulator constraints for different types of LDOx */ 172 #define S2MPU02_LDO_MIN_900MV 900000 173 #define S2MPU02_LDO_MIN_1050MV 1050000 174 #define S2MPU02_LDO_MIN_1600MV 1600000 175 #define S2MPU02_LDO_STEP_12_5MV 12500 176 #define S2MPU02_LDO_STEP_25MV 25000 177 #define S2MPU02_LDO_STEP_50MV 50000 178 179 #define S2MPU02_LDO_GROUP1_START_SEL 0x8 180 #define S2MPU02_LDO_GROUP2_START_SEL 0xA 181 #define S2MPU02_LDO_GROUP3_START_SEL 0x10 182 183 #define S2MPU02_LDO_VSEL_MASK 0x3F 184 #define S2MPU02_BUCK_VSEL_MASK 0xFF 185 #define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT) 186 #define S2MPU02_ENABLE_SHIFT 6 187 188 /* On/Off controlled by PWREN */ 189 #define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT) 190 #define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT) 191 #define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1) 192 #define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1) 193 194 /* RAMP delay for BUCK1234*/ 195 #define S2MPU02_BUCK1_RAMP_SHIFT 6 196 #define S2MPU02_BUCK2_RAMP_SHIFT 4 197 #define S2MPU02_BUCK3_RAMP_SHIFT 2 198 #define S2MPU02_BUCK4_RAMP_SHIFT 0 199 #define S2MPU02_BUCK1234_RAMP_MASK 0x3 200 201 #endif /* __LINUX_MFD_S2MPU02_H */ 202