Searched refs:SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE (Results 1 – 1 of 1) sorted by relevance
192 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) macro550 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; in tegra210_set_sata_pll_seq_sw()555 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; in tegra210_set_sata_pll_seq_sw()